PCI: tegra: Overhaul regulator usage
[deliverable/linux.git] / arch / arm / boot / dts / tegra20-trimslice.dts
CommitLineData
a7db2c15
SW
1/dts-v1/;
2
6bccbd5e 3#include <dt-bindings/input/input.h>
1bd0bd49 4#include "tegra20.dtsi"
a7db2c15
SW
5
6/ {
7 model = "Compulab TrimSlice board";
8 compatible = "compulab,trimslice", "nvidia,tegra20";
9
553c0a20
SW
10 aliases {
11 rtc0 = "/i2c@7000c500/rtc@56";
12 rtc1 = "/rtc@7000e000";
13 };
14
f9eb26a4 15 memory {
95decf84 16 reg = <0x00000000 0x40000000>;
a7db2c15
SW
17 };
18
58ecb23f
SW
19 host1x@50000000 {
20 hdmi@54280000 {
dced3e3e
TR
21 status = "okay";
22
23 vdd-supply = <&hdmi_vdd_reg>;
24 pll-supply = <&hdmi_pll_reg>;
25
26 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
3325f1bc
SW
27 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
28 GPIO_ACTIVE_HIGH>;
dced3e3e
TR
29 };
30 };
31
58ecb23f 32 pinmux@70000014 {
ecc295bb
SW
33 pinctrl-names = "default";
34 pinctrl-0 = <&state_default>;
35
36 state_default: pinmux {
37 ata {
38 nvidia,pins = "ata";
39 nvidia,function = "ide";
40 };
41 atb {
42 nvidia,pins = "atb", "gma";
43 nvidia,function = "sdio4";
44 };
45 atc {
46 nvidia,pins = "atc", "gmb";
47 nvidia,function = "nand";
48 };
49 atd {
50 nvidia,pins = "atd", "ate", "gme", "pta";
51 nvidia,function = "gmi";
52 };
53 cdev1 {
54 nvidia,pins = "cdev1";
55 nvidia,function = "plla_out";
56 };
57 cdev2 {
58 nvidia,pins = "cdev2";
59 nvidia,function = "pllp_out4";
60 };
61 crtp {
62 nvidia,pins = "crtp";
63 nvidia,function = "crt";
64 };
65 csus {
66 nvidia,pins = "csus";
67 nvidia,function = "vi_sensor_clk";
68 };
69 dap1 {
70 nvidia,pins = "dap1";
71 nvidia,function = "dap1";
72 };
73 dap2 {
74 nvidia,pins = "dap2";
75 nvidia,function = "dap2";
76 };
77 dap3 {
78 nvidia,pins = "dap3";
79 nvidia,function = "dap3";
80 };
81 dap4 {
82 nvidia,pins = "dap4";
83 nvidia,function = "dap4";
84 };
85 ddc {
86 nvidia,pins = "ddc";
87 nvidia,function = "i2c2";
88 };
89 dta {
90 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
91 nvidia,function = "vi";
92 };
93 dtf {
94 nvidia,pins = "dtf";
95 nvidia,function = "i2c3";
96 };
97 gmc {
98 nvidia,pins = "gmc", "gmd";
99 nvidia,function = "sflash";
100 };
101 gpu {
102 nvidia,pins = "gpu";
103 nvidia,function = "uarta";
104 };
105 gpu7 {
106 nvidia,pins = "gpu7";
107 nvidia,function = "rtck";
108 };
109 gpv {
110 nvidia,pins = "gpv", "slxa", "slxk";
111 nvidia,function = "pcie";
112 };
113 hdint {
114 nvidia,pins = "hdint";
115 nvidia,function = "hdmi";
116 };
117 i2cp {
118 nvidia,pins = "i2cp";
119 nvidia,function = "i2cp";
120 };
121 irrx {
122 nvidia,pins = "irrx", "irtx";
123 nvidia,function = "uartb";
124 };
125 kbca {
126 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
127 "kbce", "kbcf";
128 nvidia,function = "kbc";
129 };
130 lcsn {
131 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
132 "ld3", "ld4", "ld5", "ld6", "ld7",
133 "ld8", "ld9", "ld10", "ld11", "ld12",
134 "ld13", "ld14", "ld15", "ld16", "ld17",
135 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
136 "lhs", "lm0", "lm1", "lpp", "lpw0",
137 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
138 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
139 "lvs";
140 nvidia,function = "displaya";
141 };
142 owc {
143 nvidia,pins = "owc", "uac";
144 nvidia,function = "rsvd2";
145 };
146 pmc {
147 nvidia,pins = "pmc";
148 nvidia,function = "pwr_on";
149 };
150 rm {
151 nvidia,pins = "rm";
152 nvidia,function = "i2c1";
153 };
154 sdb {
155 nvidia,pins = "sdb", "sdc", "sdd";
156 nvidia,function = "pwm";
157 };
158 sdio1 {
159 nvidia,pins = "sdio1";
160 nvidia,function = "sdio1";
161 };
162 slxc {
163 nvidia,pins = "slxc", "slxd";
164 nvidia,function = "sdio3";
165 };
166 spdi {
167 nvidia,pins = "spdi", "spdo";
168 nvidia,function = "spdif";
169 };
170 spia {
171 nvidia,pins = "spia", "spib", "spic";
172 nvidia,function = "spi2";
173 };
174 spid {
175 nvidia,pins = "spid", "spie", "spif";
176 nvidia,function = "spi1";
177 };
178 spig {
179 nvidia,pins = "spig", "spih";
180 nvidia,function = "spi2_alt";
181 };
182 uaa {
183 nvidia,pins = "uaa", "uab", "uda";
184 nvidia,function = "ulpi";
185 };
186 uad {
187 nvidia,pins = "uad";
188 nvidia,function = "irda";
189 };
190 uca {
191 nvidia,pins = "uca", "ucb";
192 nvidia,function = "uartc";
193 };
194 conf_ata {
195 nvidia,pins = "ata", "atc", "atd", "ate",
196 "crtp", "dap2", "dap3", "dap4", "dta",
197 "dtb", "dtc", "dtd", "dte", "gmb",
198 "gme", "i2cp", "pta", "slxc", "slxd",
199 "spdi", "spdo", "uda";
ba4104e7
LD
200 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
201 nvidia,tristate = <TEGRA_PIN_ENABLE>;
ecc295bb
SW
202 };
203 conf_atb {
563da21b
SW
204 nvidia,pins = "atb", "cdev1", "cdev2", "dap1",
205 "gma", "gmc", "gmd", "gpu", "gpu7",
206 "gpv", "sdio1", "slxa", "slxk", "uac";
ba4104e7
LD
207 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
208 nvidia,tristate = <TEGRA_PIN_DISABLE>;
ecc295bb 209 };
ecc295bb
SW
210 conf_ck32 {
211 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
212 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
ba4104e7 213 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
ecc295bb 214 };
563da21b
SW
215 conf_csus {
216 nvidia,pins = "csus", "spia", "spib",
217 "spid", "spif";
ba4104e7
LD
218 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
219 nvidia,tristate = <TEGRA_PIN_ENABLE>;
563da21b 220 };
ecc295bb
SW
221 conf_ddc {
222 nvidia,pins = "ddc", "dtf", "rm", "sdc", "sdd";
ba4104e7
LD
223 nvidia,pull = <TEGRA_PIN_PULL_UP>;
224 nvidia,tristate = <TEGRA_PIN_DISABLE>;
ecc295bb
SW
225 };
226 conf_hdint {
227 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
228 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
229 "lvp0", "pmc";
ba4104e7 230 nvidia,tristate = <TEGRA_PIN_ENABLE>;
ecc295bb
SW
231 };
232 conf_irrx {
233 nvidia,pins = "irrx", "irtx", "kbca", "kbcb",
234 "kbcc", "kbcd", "kbce", "kbcf", "owc",
235 "spic", "spie", "spig", "spih", "uaa",
236 "uab", "uad", "uca", "ucb";
ba4104e7
LD
237 nvidia,pull = <TEGRA_PIN_PULL_UP>;
238 nvidia,tristate = <TEGRA_PIN_ENABLE>;
ecc295bb
SW
239 };
240 conf_lc {
241 nvidia,pins = "lc", "ls";
ba4104e7 242 nvidia,pull = <TEGRA_PIN_PULL_UP>;
ecc295bb
SW
243 };
244 conf_ld0 {
245 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
246 "ld5", "ld6", "ld7", "ld8", "ld9",
247 "ld10", "ld11", "ld12", "ld13", "ld14",
248 "ld15", "ld16", "ld17", "ldi", "lhp0",
249 "lhp1", "lhp2", "lhs", "lm0", "lpp",
250 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
251 "lvs", "sdb";
ba4104e7 252 nvidia,tristate = <TEGRA_PIN_DISABLE>;
ecc295bb
SW
253 };
254 conf_ld17_0 {
255 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
256 "ld23_22";
ba4104e7 257 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
ecc295bb 258 };
bff1ea70
SW
259 conf_spif {
260 nvidia,pins = "spif";
ba4104e7
LD
261 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
262 nvidia,tristate = <TEGRA_PIN_DISABLE>;
bff1ea70 263 };
ecc295bb
SW
264 };
265 };
266
2a5fdc9a
SW
267 i2s@70002800 {
268 status = "okay";
c04abb3a
SW
269 };
270
271 serial@70006000 {
2a5fdc9a 272 status = "okay";
c04abb3a
SW
273 };
274
dced3e3e 275 dvi_ddc: i2c@7000c000 {
2a5fdc9a 276 status = "okay";
dced3e3e 277 clock-frequency = <100000>;
a7db2c15
SW
278 };
279
fea221e2
SW
280 spi@7000c380 {
281 status = "okay";
282 spi-max-frequency = <48000000>;
283 spi-flash@0 {
284 compatible = "winbond,w25q80bl";
285 reg = <0>;
286 spi-max-frequency = <48000000>;
287 };
288 };
289
dced3e3e 290 hdmi_ddc: i2c@7000c400 {
2a5fdc9a 291 status = "okay";
dced3e3e 292 clock-frequency = <100000>;
a7db2c15
SW
293 };
294
295 i2c@7000c500 {
2a5fdc9a 296 status = "okay";
a7db2c15 297 clock-frequency = <400000>;
a7db2c15 298
22bfe102
SW
299 codec: codec@1a {
300 compatible = "ti,tlv320aic23";
301 reg = <0x1a>;
302 };
303
081cc0a5
SW
304 rtc@56 {
305 compatible = "emmicro,em3027";
306 reg = <0x56>;
307 };
88950f3b
SW
308 };
309
58ecb23f 310 pmc@7000e400 {
47d2d63b 311 nvidia,suspend-mode = <1>;
a44a019d
JL
312 nvidia,cpu-pwr-good-time = <5000>;
313 nvidia,cpu-pwr-off-time = <5000>;
314 nvidia,core-pwr-good-time = <3845 3845>;
315 nvidia,core-pwr-off-time = <3875>;
316 nvidia,sys-clock-req-active-high;
317 };
318
58ecb23f 319 pcie-controller@80003000 {
1798efda
TR
320 status = "okay";
321 pex-clk-supply = <&pci_clk_reg>;
322 vdd-supply = <&pci_vdd_reg>;
323
324 pci@1,0 {
325 status = "okay";
326 };
327 };
328
2a5fdc9a
SW
329 usb@c5000000 {
330 status = "okay";
797acf70
SW
331 };
332
4c94c8b5
VB
333 usb-phy@c5000000 {
334 status = "okay";
335 vbus-supply = <&vbus_reg>;
336 };
337
c04abb3a 338 usb@c5004000 {
a6a3dd1a 339 status = "okay";
3325f1bc
SW
340 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
341 GPIO_ACTIVE_LOW>;
31c1ec92
SW
342 };
343
9dffe3be 344 usb-phy@c5004000 {
4c94c8b5 345 status = "okay";
3325f1bc
SW
346 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 0)
347 GPIO_ACTIVE_LOW>;
1292c129
SW
348 };
349
9dffe3be
VB
350 usb@c5008000 {
351 status = "okay";
40e8b3a6
VB
352 };
353
4c94c8b5
VB
354 usb-phy@c5008000 {
355 status = "okay";
356 };
357
2a5fdc9a
SW
358 sdhci@c8000000 {
359 status = "okay";
deb88cc3 360 bus-width = <4>;
1292c129
SW
361 };
362
a7db2c15 363 sdhci@c8000600 {
2a5fdc9a 364 status = "okay";
3325f1bc
SW
365 cd-gpios = <&gpio TEGRA_GPIO(P, 1) GPIO_ACTIVE_LOW>;
366 wp-gpios = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>;
deb88cc3 367 bus-width = <4>;
a7db2c15 368 };
aa607ebf 369
7021d122
JL
370 clocks {
371 compatible = "simple-bus";
372 #address-cells = <1>;
373 #size-cells = <0>;
374
58ecb23f 375 clk32k_in: clock@0 {
7021d122
JL
376 compatible = "fixed-clock";
377 reg=<0>;
378 #clock-cells = <0>;
379 clock-frequency = <32768>;
380 };
381 };
382
5741a256
JL
383 gpio-keys {
384 compatible = "gpio-keys";
385
386 power {
387 label = "Power";
3325f1bc 388 gpios = <&gpio TEGRA_GPIO(X, 6) GPIO_ACTIVE_LOW>;
6bccbd5e 389 linux,code = <KEY_POWER>;
5741a256
JL
390 gpio-key,wakeup;
391 };
392 };
393
bff1ea70
SW
394 poweroff {
395 compatible = "gpio-poweroff";
3325f1bc 396 gpios = <&gpio TEGRA_GPIO(X, 7) GPIO_ACTIVE_LOW>;
bff1ea70
SW
397 };
398
dced3e3e
TR
399 regulators {
400 compatible = "simple-bus";
401 #address-cells = <1>;
402 #size-cells = <0>;
403
404 hdmi_vdd_reg: regulator@0 {
405 compatible = "regulator-fixed";
406 reg = <0>;
407 regulator-name = "avdd_hdmi";
408 regulator-min-microvolt = <3300000>;
409 regulator-max-microvolt = <3300000>;
410 regulator-always-on;
411 };
412
413 hdmi_pll_reg: regulator@1 {
414 compatible = "regulator-fixed";
415 reg = <1>;
416 regulator-name = "avdd_hdmi_pll";
417 regulator-min-microvolt = <1800000>;
418 regulator-max-microvolt = <1800000>;
419 regulator-always-on;
420 };
4c94c8b5
VB
421
422 vbus_reg: regulator@2 {
423 compatible = "regulator-fixed";
424 reg = <2>;
425 regulator-name = "usb1_vbus";
426 regulator-min-microvolt = <5000000>;
427 regulator-max-microvolt = <5000000>;
9f310ded 428 enable-active-high;
23f95ef2 429 gpio = <&gpio TEGRA_GPIO(V, 2) 0>;
30ca2226
SW
430 regulator-always-on;
431 regulator-boot-on;
4c94c8b5 432 };
1798efda
TR
433
434 pci_clk_reg: regulator@3 {
435 compatible = "regulator-fixed";
436 reg = <3>;
437 regulator-name = "pci_clk";
438 regulator-min-microvolt = <3300000>;
439 regulator-max-microvolt = <3300000>;
440 regulator-always-on;
441 };
442
443 pci_vdd_reg: regulator@4 {
444 compatible = "regulator-fixed";
445 reg = <4>;
446 regulator-name = "pci_vdd";
447 regulator-min-microvolt = <1050000>;
448 regulator-max-microvolt = <1050000>;
449 regulator-always-on;
450 };
dced3e3e
TR
451 };
452
c04abb3a
SW
453 sound {
454 compatible = "nvidia,tegra-audio-trimslice";
455 nvidia,i2s-controller = <&tegra_i2s1>;
456 nvidia,audio-codec = <&codec>;
f9cd2b3b 457
885a8cfa
HD
458 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
459 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
460 <&tegra_car TEGRA20_CLK_CDEV1>;
f9cd2b3b 461 clock-names = "pll_a", "pll_a_out0", "mclk";
aa607ebf 462 };
a7db2c15 463};
This page took 0.262179 seconds and 5 git commands to generate.