Commit | Line | Data |
---|---|---|
add29e61 PDS |
1 | /dts-v1/; |
2 | ||
6bccbd5e | 3 | #include <dt-bindings/input/input.h> |
1bd0bd49 | 4 | #include "tegra20.dtsi" |
add29e61 PDS |
5 | |
6 | / { | |
8fef5dff | 7 | model = "NVIDIA Tegra20 Ventana evaluation board"; |
add29e61 PDS |
8 | compatible = "nvidia,ventana", "nvidia,tegra20"; |
9 | ||
553c0a20 SW |
10 | aliases { |
11 | rtc0 = "/i2c@7000d000/tps6586x@34"; | |
12 | rtc1 = "/rtc@7000e000"; | |
13 | }; | |
14 | ||
add29e61 | 15 | memory { |
95decf84 | 16 | reg = <0x00000000 0x40000000>; |
add29e61 PDS |
17 | }; |
18 | ||
58ecb23f SW |
19 | host1x@50000000 { |
20 | hdmi@54280000 { | |
97d5520f SW |
21 | status = "okay"; |
22 | ||
23 | vdd-supply = <&hdmi_vdd_reg>; | |
24 | pll-supply = <&hdmi_pll_reg>; | |
25 | ||
26 | nvidia,ddc-i2c-bus = <&hdmi_ddc>; | |
3325f1bc SW |
27 | nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7) |
28 | GPIO_ACTIVE_HIGH>; | |
97d5520f SW |
29 | }; |
30 | }; | |
31 | ||
58ecb23f | 32 | pinmux@70000014 { |
ecc295bb SW |
33 | pinctrl-names = "default"; |
34 | pinctrl-0 = <&state_default>; | |
35 | ||
36 | state_default: pinmux { | |
37 | ata { | |
38 | nvidia,pins = "ata"; | |
39 | nvidia,function = "ide"; | |
40 | }; | |
41 | atb { | |
42 | nvidia,pins = "atb", "gma", "gme"; | |
43 | nvidia,function = "sdio4"; | |
44 | }; | |
45 | atc { | |
46 | nvidia,pins = "atc"; | |
47 | nvidia,function = "nand"; | |
48 | }; | |
49 | atd { | |
50 | nvidia,pins = "atd", "ate", "gmb", "spia", | |
51 | "spib", "spic"; | |
52 | nvidia,function = "gmi"; | |
53 | }; | |
54 | cdev1 { | |
55 | nvidia,pins = "cdev1"; | |
56 | nvidia,function = "plla_out"; | |
57 | }; | |
58 | cdev2 { | |
59 | nvidia,pins = "cdev2"; | |
60 | nvidia,function = "pllp_out4"; | |
61 | }; | |
62 | crtp { | |
63 | nvidia,pins = "crtp", "lm1"; | |
64 | nvidia,function = "crt"; | |
65 | }; | |
66 | csus { | |
67 | nvidia,pins = "csus"; | |
68 | nvidia,function = "vi_sensor_clk"; | |
69 | }; | |
70 | dap1 { | |
71 | nvidia,pins = "dap1"; | |
72 | nvidia,function = "dap1"; | |
73 | }; | |
74 | dap2 { | |
75 | nvidia,pins = "dap2"; | |
76 | nvidia,function = "dap2"; | |
77 | }; | |
78 | dap3 { | |
79 | nvidia,pins = "dap3"; | |
80 | nvidia,function = "dap3"; | |
81 | }; | |
82 | dap4 { | |
83 | nvidia,pins = "dap4"; | |
84 | nvidia,function = "dap4"; | |
85 | }; | |
ecc295bb SW |
86 | dta { |
87 | nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte"; | |
88 | nvidia,function = "vi"; | |
89 | }; | |
90 | dtf { | |
91 | nvidia,pins = "dtf"; | |
92 | nvidia,function = "i2c3"; | |
93 | }; | |
94 | gmc { | |
95 | nvidia,pins = "gmc"; | |
96 | nvidia,function = "uartd"; | |
97 | }; | |
98 | gmd { | |
99 | nvidia,pins = "gmd"; | |
100 | nvidia,function = "sflash"; | |
101 | }; | |
102 | gpu { | |
103 | nvidia,pins = "gpu"; | |
104 | nvidia,function = "pwm"; | |
105 | }; | |
106 | gpu7 { | |
107 | nvidia,pins = "gpu7"; | |
108 | nvidia,function = "rtck"; | |
109 | }; | |
110 | gpv { | |
111 | nvidia,pins = "gpv", "slxa", "slxk"; | |
112 | nvidia,function = "pcie"; | |
113 | }; | |
114 | hdint { | |
cf633464 | 115 | nvidia,pins = "hdint"; |
ecc295bb SW |
116 | nvidia,function = "hdmi"; |
117 | }; | |
118 | i2cp { | |
119 | nvidia,pins = "i2cp"; | |
120 | nvidia,function = "i2cp"; | |
121 | }; | |
122 | irrx { | |
123 | nvidia,pins = "irrx", "irtx"; | |
124 | nvidia,function = "uartb"; | |
125 | }; | |
126 | kbca { | |
127 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
128 | "kbce", "kbcf"; | |
129 | nvidia,function = "kbc"; | |
130 | }; | |
131 | lcsn { | |
132 | nvidia,pins = "lcsn", "ldc", "lm0", "lpw1", | |
133 | "lsdi", "lvp0"; | |
134 | nvidia,function = "rsvd4"; | |
135 | }; | |
136 | ld0 { | |
137 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
138 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
139 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
140 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
141 | "lhp1", "lhp2", "lhs", "lpp", "lpw0", | |
142 | "lpw2", "lsc0", "lsc1", "lsck", "lsda", | |
143 | "lspi", "lvp1", "lvs"; | |
144 | nvidia,function = "displaya"; | |
145 | }; | |
cf633464 MZ |
146 | owc { |
147 | nvidia,pins = "owc", "spdi", "spdo", "uac"; | |
148 | nvidia,function = "rsvd2"; | |
149 | }; | |
ecc295bb SW |
150 | pmc { |
151 | nvidia,pins = "pmc"; | |
152 | nvidia,function = "pwr_on"; | |
153 | }; | |
154 | rm { | |
155 | nvidia,pins = "rm"; | |
156 | nvidia,function = "i2c1"; | |
157 | }; | |
158 | sdb { | |
159 | nvidia,pins = "sdb", "sdc", "sdd", "slxc"; | |
160 | nvidia,function = "sdio3"; | |
161 | }; | |
162 | sdio1 { | |
163 | nvidia,pins = "sdio1"; | |
164 | nvidia,function = "sdio1"; | |
165 | }; | |
166 | slxd { | |
167 | nvidia,pins = "slxd"; | |
168 | nvidia,function = "spdif"; | |
169 | }; | |
170 | spid { | |
171 | nvidia,pins = "spid", "spie", "spif"; | |
172 | nvidia,function = "spi1"; | |
173 | }; | |
174 | spig { | |
175 | nvidia,pins = "spig", "spih"; | |
176 | nvidia,function = "spi2_alt"; | |
177 | }; | |
178 | uaa { | |
179 | nvidia,pins = "uaa", "uab", "uda"; | |
180 | nvidia,function = "ulpi"; | |
181 | }; | |
182 | uad { | |
183 | nvidia,pins = "uad"; | |
184 | nvidia,function = "irda"; | |
185 | }; | |
186 | uca { | |
187 | nvidia,pins = "uca", "ucb"; | |
188 | nvidia,function = "uartc"; | |
189 | }; | |
190 | conf_ata { | |
191 | nvidia,pins = "ata", "atb", "atc", "atd", | |
192 | "cdev1", "cdev2", "dap1", "dap2", | |
193 | "dap4", "ddc", "dtf", "gma", "gmc", | |
194 | "gme", "gpu", "gpu7", "i2cp", "irrx", | |
195 | "irtx", "pta", "rm", "sdc", "sdd", | |
196 | "slxc", "slxd", "slxk", "spdi", "spdo", | |
197 | "uac", "uad", "uca", "ucb", "uda"; | |
ba4104e7 LD |
198 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
199 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb SW |
200 | }; |
201 | conf_ate { | |
202 | nvidia,pins = "ate", "csus", "dap3", "gmd", | |
203 | "gpv", "owc", "spia", "spib", "spic", | |
204 | "spid", "spie", "spig"; | |
ba4104e7 LD |
205 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
206 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
207 | }; |
208 | conf_ck32 { | |
209 | nvidia,pins = "ck32", "ddrc", "pmca", "pmcb", | |
210 | "pmcc", "pmcd", "pmce", "xm2c", "xm2d"; | |
ba4104e7 | 211 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
ecc295bb SW |
212 | }; |
213 | conf_crtp { | |
214 | nvidia,pins = "crtp", "gmb", "slxa", "spih"; | |
ba4104e7 LD |
215 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
216 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
217 | }; |
218 | conf_dta { | |
219 | nvidia,pins = "dta", "dtb", "dtc", "dtd"; | |
ba4104e7 LD |
220 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
221 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb SW |
222 | }; |
223 | conf_dte { | |
224 | nvidia,pins = "dte", "spif"; | |
ba4104e7 LD |
225 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
226 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
ecc295bb SW |
227 | }; |
228 | conf_hdint { | |
229 | nvidia,pins = "hdint", "lcsn", "ldc", "lm1", | |
230 | "lpw1", "lsck", "lsda", "lsdi", "lvp0"; | |
ba4104e7 | 231 | nvidia,tristate = <TEGRA_PIN_ENABLE>; |
ecc295bb SW |
232 | }; |
233 | conf_kbca { | |
234 | nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd", | |
235 | "kbce", "kbcf", "sdio1", "uaa", "uab"; | |
ba4104e7 LD |
236 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
237 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
ecc295bb SW |
238 | }; |
239 | conf_lc { | |
240 | nvidia,pins = "lc", "ls"; | |
ba4104e7 | 241 | nvidia,pull = <TEGRA_PIN_PULL_UP>; |
ecc295bb SW |
242 | }; |
243 | conf_ld0 { | |
244 | nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4", | |
245 | "ld5", "ld6", "ld7", "ld8", "ld9", | |
246 | "ld10", "ld11", "ld12", "ld13", "ld14", | |
247 | "ld15", "ld16", "ld17", "ldi", "lhp0", | |
248 | "lhp1", "lhp2", "lhs", "lm0", "lpp", | |
249 | "lpw0", "lpw2", "lsc0", "lsc1", "lspi", | |
250 | "lvp1", "lvs", "pmc", "sdb"; | |
ba4104e7 | 251 | nvidia,tristate = <TEGRA_PIN_DISABLE>; |
ecc295bb SW |
252 | }; |
253 | conf_ld17_0 { | |
254 | nvidia,pins = "ld17_0", "ld19_18", "ld21_20", | |
255 | "ld23_22"; | |
ba4104e7 | 256 | nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
ecc295bb | 257 | }; |
c729429e WN |
258 | drive_sdio1 { |
259 | nvidia,pins = "drive_sdio1"; | |
ba4104e7 LD |
260 | nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>; |
261 | nvidia,schmitt = <TEGRA_PIN_ENABLE>; | |
262 | nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; | |
c729429e WN |
263 | nvidia,pull-down-strength = <31>; |
264 | nvidia,pull-up-strength = <31>; | |
ba4104e7 LD |
265 | nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_SLOWEST>; |
266 | nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_SLOWEST>; | |
c729429e | 267 | }; |
ecc295bb | 268 | }; |
cf633464 MZ |
269 | |
270 | state_i2cmux_ddc: pinmux_i2cmux_ddc { | |
271 | ddc { | |
272 | nvidia,pins = "ddc"; | |
273 | nvidia,function = "i2c2"; | |
274 | }; | |
275 | pta { | |
276 | nvidia,pins = "pta"; | |
277 | nvidia,function = "rsvd4"; | |
278 | }; | |
279 | }; | |
280 | ||
281 | state_i2cmux_pta: pinmux_i2cmux_pta { | |
282 | ddc { | |
283 | nvidia,pins = "ddc"; | |
284 | nvidia,function = "rsvd4"; | |
285 | }; | |
286 | pta { | |
287 | nvidia,pins = "pta"; | |
288 | nvidia,function = "i2c2"; | |
289 | }; | |
290 | }; | |
291 | ||
292 | state_i2cmux_idle: pinmux_i2cmux_idle { | |
293 | ddc { | |
294 | nvidia,pins = "ddc"; | |
295 | nvidia,function = "rsvd4"; | |
296 | }; | |
297 | pta { | |
298 | nvidia,pins = "pta"; | |
299 | nvidia,function = "rsvd4"; | |
300 | }; | |
301 | }; | |
ecc295bb SW |
302 | }; |
303 | ||
2a5fdc9a SW |
304 | i2s@70002800 { |
305 | status = "okay"; | |
c04abb3a SW |
306 | }; |
307 | ||
308 | serial@70006300 { | |
2a5fdc9a | 309 | status = "okay"; |
c04abb3a SW |
310 | }; |
311 | ||
88950f3b | 312 | i2c@7000c000 { |
2a5fdc9a | 313 | status = "okay"; |
88950f3b | 314 | clock-frequency = <400000>; |
797acf70 SW |
315 | |
316 | wm8903: wm8903@1a { | |
317 | compatible = "wlf,wm8903"; | |
318 | reg = <0x1a>; | |
319 | interrupt-parent = <&gpio>; | |
6cecf916 | 320 | interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>; |
797acf70 SW |
321 | |
322 | gpio-controller; | |
323 | #gpio-cells = <2>; | |
324 | ||
325 | micdet-cfg = <0>; | |
326 | micdet-delay = <100>; | |
95decf84 | 327 | gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>; |
797acf70 | 328 | }; |
b46b0b54 LD |
329 | |
330 | /* ALS and proximity sensor */ | |
331 | isl29018@44 { | |
332 | compatible = "isil,isl29018"; | |
333 | reg = <0x44>; | |
334 | interrupt-parent = <&gpio>; | |
6cecf916 | 335 | interrupts = <TEGRA_GPIO(Z, 2) IRQ_TYPE_LEVEL_HIGH>; |
b46b0b54 | 336 | }; |
88950f3b SW |
337 | }; |
338 | ||
339 | i2c@7000c400 { | |
2a5fdc9a | 340 | status = "okay"; |
97d5520f | 341 | clock-frequency = <100000>; |
88950f3b SW |
342 | }; |
343 | ||
cf633464 MZ |
344 | i2cmux { |
345 | compatible = "i2c-mux-pinctrl"; | |
346 | #address-cells = <1>; | |
347 | #size-cells = <0>; | |
348 | ||
349 | i2c-parent = <&{/i2c@7000c400}>; | |
350 | ||
351 | pinctrl-names = "ddc", "pta", "idle"; | |
352 | pinctrl-0 = <&state_i2cmux_ddc>; | |
353 | pinctrl-1 = <&state_i2cmux_pta>; | |
354 | pinctrl-2 = <&state_i2cmux_idle>; | |
355 | ||
97d5520f | 356 | hdmi_ddc: i2c@0 { |
cf633464 MZ |
357 | reg = <0>; |
358 | #address-cells = <1>; | |
359 | #size-cells = <0>; | |
360 | }; | |
361 | ||
362 | i2c@1 { | |
363 | reg = <1>; | |
364 | #address-cells = <1>; | |
365 | #size-cells = <0>; | |
366 | }; | |
367 | }; | |
368 | ||
88950f3b | 369 | i2c@7000c500 { |
2a5fdc9a | 370 | status = "okay"; |
88950f3b SW |
371 | clock-frequency = <400000>; |
372 | }; | |
373 | ||
374 | i2c@7000d000 { | |
2a5fdc9a | 375 | status = "okay"; |
88950f3b | 376 | clock-frequency = <400000>; |
017a0104 SW |
377 | |
378 | pmic: tps6586x@34 { | |
379 | compatible = "ti,tps6586x"; | |
380 | reg = <0x34>; | |
6cecf916 | 381 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; |
017a0104 | 382 | |
44b12ef7 SW |
383 | ti,system-power-controller; |
384 | ||
017a0104 SW |
385 | #gpio-cells = <2>; |
386 | gpio-controller; | |
387 | ||
388 | sys-supply = <&vdd_5v0_reg>; | |
389 | vin-sm0-supply = <&sys_reg>; | |
390 | vin-sm1-supply = <&sys_reg>; | |
391 | vin-sm2-supply = <&sys_reg>; | |
392 | vinldo01-supply = <&sm2_reg>; | |
393 | vinldo23-supply = <&sm2_reg>; | |
394 | vinldo4-supply = <&sm2_reg>; | |
395 | vinldo678-supply = <&sm2_reg>; | |
396 | vinldo9-supply = <&sm2_reg>; | |
397 | ||
398 | regulators { | |
b9c665d7 | 399 | sys_reg: sys { |
017a0104 SW |
400 | regulator-name = "vdd_sys"; |
401 | regulator-always-on; | |
402 | }; | |
403 | ||
b9c665d7 | 404 | sm0 { |
017a0104 SW |
405 | regulator-name = "vdd_sm0,vdd_core"; |
406 | regulator-min-microvolt = <1200000>; | |
407 | regulator-max-microvolt = <1200000>; | |
408 | regulator-always-on; | |
409 | }; | |
410 | ||
b9c665d7 | 411 | sm1 { |
017a0104 SW |
412 | regulator-name = "vdd_sm1,vdd_cpu"; |
413 | regulator-min-microvolt = <1000000>; | |
414 | regulator-max-microvolt = <1000000>; | |
415 | regulator-always-on; | |
416 | }; | |
417 | ||
b9c665d7 | 418 | sm2_reg: sm2 { |
017a0104 SW |
419 | regulator-name = "vdd_sm2,vin_ldo*"; |
420 | regulator-min-microvolt = <3700000>; | |
421 | regulator-max-microvolt = <3700000>; | |
422 | regulator-always-on; | |
423 | }; | |
424 | ||
425 | /* LDO0 is not connected to anything */ | |
426 | ||
b9c665d7 | 427 | ldo1 { |
017a0104 SW |
428 | regulator-name = "vdd_ldo1,avdd_pll*"; |
429 | regulator-min-microvolt = <1100000>; | |
430 | regulator-max-microvolt = <1100000>; | |
431 | regulator-always-on; | |
432 | }; | |
433 | ||
b9c665d7 | 434 | ldo2 { |
017a0104 SW |
435 | regulator-name = "vdd_ldo2,vdd_rtc"; |
436 | regulator-min-microvolt = <1200000>; | |
437 | regulator-max-microvolt = <1200000>; | |
438 | }; | |
439 | ||
b9c665d7 | 440 | ldo3 { |
017a0104 SW |
441 | regulator-name = "vdd_ldo3,avdd_usb*"; |
442 | regulator-min-microvolt = <3300000>; | |
443 | regulator-max-microvolt = <3300000>; | |
444 | regulator-always-on; | |
445 | }; | |
446 | ||
b9c665d7 | 447 | ldo4 { |
017a0104 SW |
448 | regulator-name = "vdd_ldo4,avdd_osc,vddio_sys"; |
449 | regulator-min-microvolt = <1800000>; | |
450 | regulator-max-microvolt = <1800000>; | |
451 | regulator-always-on; | |
452 | }; | |
453 | ||
b9c665d7 | 454 | ldo5 { |
017a0104 SW |
455 | regulator-name = "vdd_ldo5,vcore_mmc"; |
456 | regulator-min-microvolt = <2850000>; | |
457 | regulator-max-microvolt = <2850000>; | |
458 | regulator-always-on; | |
459 | }; | |
460 | ||
b9c665d7 | 461 | ldo6 { |
017a0104 SW |
462 | regulator-name = "vdd_ldo6,avdd_vdac"; |
463 | regulator-min-microvolt = <1800000>; | |
464 | regulator-max-microvolt = <1800000>; | |
465 | }; | |
466 | ||
97d5520f | 467 | hdmi_vdd_reg: ldo7 { |
017a0104 SW |
468 | regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse"; |
469 | regulator-min-microvolt = <3300000>; | |
470 | regulator-max-microvolt = <3300000>; | |
471 | }; | |
472 | ||
97d5520f | 473 | hdmi_pll_reg: ldo8 { |
017a0104 SW |
474 | regulator-name = "vdd_ldo8,avdd_hdmi_pll"; |
475 | regulator-min-microvolt = <1800000>; | |
476 | regulator-max-microvolt = <1800000>; | |
477 | }; | |
478 | ||
b9c665d7 | 479 | ldo9 { |
017a0104 SW |
480 | regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx"; |
481 | regulator-min-microvolt = <2850000>; | |
482 | regulator-max-microvolt = <2850000>; | |
483 | regulator-always-on; | |
484 | }; | |
485 | ||
b9c665d7 | 486 | ldo_rtc { |
017a0104 SW |
487 | regulator-name = "vdd_rtc_out,vdd_cell"; |
488 | regulator-min-microvolt = <3300000>; | |
489 | regulator-max-microvolt = <3300000>; | |
490 | regulator-always-on; | |
491 | }; | |
492 | }; | |
493 | }; | |
ee9f7260 TR |
494 | |
495 | temperature-sensor@4c { | |
496 | compatible = "onnn,nct1008"; | |
497 | reg = <0x4c>; | |
498 | }; | |
017a0104 SW |
499 | }; |
500 | ||
58ecb23f | 501 | pmc@7000e400 { |
017a0104 | 502 | nvidia,invert-interrupt; |
47d2d63b | 503 | nvidia,suspend-mode = <1>; |
a44a019d JL |
504 | nvidia,cpu-pwr-good-time = <2000>; |
505 | nvidia,cpu-pwr-off-time = <100>; | |
506 | nvidia,core-pwr-good-time = <3845 3845>; | |
507 | nvidia,core-pwr-off-time = <458>; | |
508 | nvidia,sys-clock-req-active-high; | |
88950f3b SW |
509 | }; |
510 | ||
2a5fdc9a SW |
511 | usb@c5000000 { |
512 | status = "okay"; | |
c04abb3a SW |
513 | }; |
514 | ||
4c94c8b5 VB |
515 | usb-phy@c5000000 { |
516 | status = "okay"; | |
517 | }; | |
518 | ||
2a5fdc9a SW |
519 | usb@c5004000 { |
520 | status = "okay"; | |
3325f1bc SW |
521 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
522 | GPIO_ACTIVE_LOW>; | |
797acf70 SW |
523 | }; |
524 | ||
9dffe3be | 525 | usb-phy@c5004000 { |
4c94c8b5 | 526 | status = "okay"; |
3325f1bc SW |
527 | nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1) |
528 | GPIO_ACTIVE_LOW>; | |
c04abb3a SW |
529 | }; |
530 | ||
9dffe3be VB |
531 | usb@c5008000 { |
532 | status = "okay"; | |
40e8b3a6 VB |
533 | }; |
534 | ||
4c94c8b5 VB |
535 | usb-phy@c5008000 { |
536 | status = "okay"; | |
537 | }; | |
538 | ||
c729429e WN |
539 | sdhci@c8000000 { |
540 | status = "okay"; | |
3325f1bc | 541 | power-gpios = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
c729429e | 542 | bus-width = <4>; |
7a2617a6 | 543 | keep-power-in-suspend; |
c729429e WN |
544 | }; |
545 | ||
c04abb3a | 546 | sdhci@c8000400 { |
2a5fdc9a | 547 | status = "okay"; |
3325f1bc SW |
548 | cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>; |
549 | wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>; | |
550 | power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>; | |
deb88cc3 | 551 | bus-width = <4>; |
c04abb3a SW |
552 | }; |
553 | ||
554 | sdhci@c8000600 { | |
2a5fdc9a | 555 | status = "okay"; |
deb88cc3 | 556 | bus-width = <8>; |
7a2617a6 | 557 | non-removable; |
c04abb3a SW |
558 | }; |
559 | ||
7021d122 JL |
560 | clocks { |
561 | compatible = "simple-bus"; | |
562 | #address-cells = <1>; | |
563 | #size-cells = <0>; | |
564 | ||
58ecb23f | 565 | clk32k_in: clock@0 { |
7021d122 JL |
566 | compatible = "fixed-clock"; |
567 | reg=<0>; | |
568 | #clock-cells = <0>; | |
569 | clock-frequency = <32768>; | |
570 | }; | |
571 | }; | |
572 | ||
5741a256 JL |
573 | gpio-keys { |
574 | compatible = "gpio-keys"; | |
575 | ||
576 | power { | |
577 | label = "Power"; | |
3325f1bc | 578 | gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>; |
6bccbd5e | 579 | linux,code = <KEY_POWER>; |
5741a256 JL |
580 | gpio-key,wakeup; |
581 | }; | |
582 | }; | |
583 | ||
017a0104 SW |
584 | regulators { |
585 | compatible = "simple-bus"; | |
586 | #address-cells = <1>; | |
587 | #size-cells = <0>; | |
588 | ||
589 | vdd_5v0_reg: regulator@0 { | |
590 | compatible = "regulator-fixed"; | |
591 | reg = <0>; | |
592 | regulator-name = "vdd_5v0"; | |
593 | regulator-min-microvolt = <5000000>; | |
594 | regulator-max-microvolt = <5000000>; | |
595 | regulator-always-on; | |
596 | }; | |
597 | ||
598 | regulator@1 { | |
599 | compatible = "regulator-fixed"; | |
600 | reg = <1>; | |
601 | regulator-name = "vdd_1v5"; | |
602 | regulator-min-microvolt = <1500000>; | |
603 | regulator-max-microvolt = <1500000>; | |
3325f1bc | 604 | gpio = <&pmic 0 GPIO_ACTIVE_HIGH>; |
017a0104 SW |
605 | }; |
606 | ||
607 | regulator@2 { | |
608 | compatible = "regulator-fixed"; | |
609 | reg = <2>; | |
610 | regulator-name = "vdd_1v2"; | |
611 | regulator-min-microvolt = <1200000>; | |
612 | regulator-max-microvolt = <1200000>; | |
3325f1bc | 613 | gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
017a0104 SW |
614 | enable-active-high; |
615 | }; | |
616 | ||
617 | regulator@3 { | |
618 | compatible = "regulator-fixed"; | |
619 | reg = <3>; | |
620 | regulator-name = "vdd_pnl"; | |
621 | regulator-min-microvolt = <2800000>; | |
622 | regulator-max-microvolt = <2800000>; | |
3325f1bc | 623 | gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>; |
017a0104 SW |
624 | enable-active-high; |
625 | }; | |
626 | ||
627 | regulator@4 { | |
628 | compatible = "regulator-fixed"; | |
629 | reg = <4>; | |
630 | regulator-name = "vdd_bl"; | |
631 | regulator-min-microvolt = <2800000>; | |
632 | regulator-max-microvolt = <2800000>; | |
3325f1bc | 633 | gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>; |
017a0104 SW |
634 | enable-active-high; |
635 | }; | |
636 | }; | |
637 | ||
797acf70 SW |
638 | sound { |
639 | compatible = "nvidia,tegra-audio-wm8903-ventana", | |
640 | "nvidia,tegra-audio-wm8903"; | |
641 | nvidia,model = "NVIDIA Tegra Ventana"; | |
642 | ||
643 | nvidia,audio-routing = | |
644 | "Headphone Jack", "HPOUTR", | |
645 | "Headphone Jack", "HPOUTL", | |
646 | "Int Spk", "ROP", | |
647 | "Int Spk", "RON", | |
648 | "Int Spk", "LOP", | |
649 | "Int Spk", "LON", | |
650 | "Mic Jack", "MICBIAS", | |
651 | "IN1L", "Mic Jack"; | |
652 | ||
653 | nvidia,i2s-controller = <&tegra_i2s1>; | |
654 | nvidia,audio-codec = <&wm8903>; | |
655 | ||
3325f1bc SW |
656 | nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>; |
657 | nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2) GPIO_ACTIVE_HIGH>; | |
658 | nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0) | |
659 | GPIO_ACTIVE_HIGH>; | |
660 | nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1) | |
661 | GPIO_ACTIVE_HIGH>; | |
f9cd2b3b | 662 | |
885a8cfa HD |
663 | clocks = <&tegra_car TEGRA20_CLK_PLL_A>, |
664 | <&tegra_car TEGRA20_CLK_PLL_A_OUT0>, | |
665 | <&tegra_car TEGRA20_CLK_CDEV1>; | |
f9cd2b3b | 666 | clock-names = "pll_a", "pll_a_out0", "mclk"; |
797acf70 | 667 | }; |
add29e61 | 668 | }; |