ARM: tegra: move serial clock-frequency attr into the Tegra20 dtsi
[deliverable/linux.git] / arch / arm / boot / dts / tegra20-ventana.dts
CommitLineData
add29e61
PDS
1/dts-v1/;
2
add29e61
PDS
3/include/ "tegra20.dtsi"
4
5/ {
8fef5dff 6 model = "NVIDIA Tegra20 Ventana evaluation board";
add29e61
PDS
7 compatible = "nvidia,ventana", "nvidia,tegra20";
8
add29e61 9 memory {
95decf84 10 reg = <0x00000000 0x40000000>;
add29e61
PDS
11 };
12
97d5520f
SW
13 host1x {
14 hdmi {
15 status = "okay";
16
17 vdd-supply = <&hdmi_vdd_reg>;
18 pll-supply = <&hdmi_pll_reg>;
19
20 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
21 nvidia,hpd-gpio = <&gpio 111 0>; /* PN7 */
22 };
23 };
24
f9eb26a4 25 pinmux {
ecc295bb
SW
26 pinctrl-names = "default";
27 pinctrl-0 = <&state_default>;
28
29 state_default: pinmux {
30 ata {
31 nvidia,pins = "ata";
32 nvidia,function = "ide";
33 };
34 atb {
35 nvidia,pins = "atb", "gma", "gme";
36 nvidia,function = "sdio4";
37 };
38 atc {
39 nvidia,pins = "atc";
40 nvidia,function = "nand";
41 };
42 atd {
43 nvidia,pins = "atd", "ate", "gmb", "spia",
44 "spib", "spic";
45 nvidia,function = "gmi";
46 };
47 cdev1 {
48 nvidia,pins = "cdev1";
49 nvidia,function = "plla_out";
50 };
51 cdev2 {
52 nvidia,pins = "cdev2";
53 nvidia,function = "pllp_out4";
54 };
55 crtp {
56 nvidia,pins = "crtp", "lm1";
57 nvidia,function = "crt";
58 };
59 csus {
60 nvidia,pins = "csus";
61 nvidia,function = "vi_sensor_clk";
62 };
63 dap1 {
64 nvidia,pins = "dap1";
65 nvidia,function = "dap1";
66 };
67 dap2 {
68 nvidia,pins = "dap2";
69 nvidia,function = "dap2";
70 };
71 dap3 {
72 nvidia,pins = "dap3";
73 nvidia,function = "dap3";
74 };
75 dap4 {
76 nvidia,pins = "dap4";
77 nvidia,function = "dap4";
78 };
ecc295bb
SW
79 dta {
80 nvidia,pins = "dta", "dtb", "dtc", "dtd", "dte";
81 nvidia,function = "vi";
82 };
83 dtf {
84 nvidia,pins = "dtf";
85 nvidia,function = "i2c3";
86 };
87 gmc {
88 nvidia,pins = "gmc";
89 nvidia,function = "uartd";
90 };
91 gmd {
92 nvidia,pins = "gmd";
93 nvidia,function = "sflash";
94 };
95 gpu {
96 nvidia,pins = "gpu";
97 nvidia,function = "pwm";
98 };
99 gpu7 {
100 nvidia,pins = "gpu7";
101 nvidia,function = "rtck";
102 };
103 gpv {
104 nvidia,pins = "gpv", "slxa", "slxk";
105 nvidia,function = "pcie";
106 };
107 hdint {
cf633464 108 nvidia,pins = "hdint";
ecc295bb
SW
109 nvidia,function = "hdmi";
110 };
111 i2cp {
112 nvidia,pins = "i2cp";
113 nvidia,function = "i2cp";
114 };
115 irrx {
116 nvidia,pins = "irrx", "irtx";
117 nvidia,function = "uartb";
118 };
119 kbca {
120 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
121 "kbce", "kbcf";
122 nvidia,function = "kbc";
123 };
124 lcsn {
125 nvidia,pins = "lcsn", "ldc", "lm0", "lpw1",
126 "lsdi", "lvp0";
127 nvidia,function = "rsvd4";
128 };
129 ld0 {
130 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
131 "ld5", "ld6", "ld7", "ld8", "ld9",
132 "ld10", "ld11", "ld12", "ld13", "ld14",
133 "ld15", "ld16", "ld17", "ldi", "lhp0",
134 "lhp1", "lhp2", "lhs", "lpp", "lpw0",
135 "lpw2", "lsc0", "lsc1", "lsck", "lsda",
136 "lspi", "lvp1", "lvs";
137 nvidia,function = "displaya";
138 };
cf633464
MZ
139 owc {
140 nvidia,pins = "owc", "spdi", "spdo", "uac";
141 nvidia,function = "rsvd2";
142 };
ecc295bb
SW
143 pmc {
144 nvidia,pins = "pmc";
145 nvidia,function = "pwr_on";
146 };
147 rm {
148 nvidia,pins = "rm";
149 nvidia,function = "i2c1";
150 };
151 sdb {
152 nvidia,pins = "sdb", "sdc", "sdd", "slxc";
153 nvidia,function = "sdio3";
154 };
155 sdio1 {
156 nvidia,pins = "sdio1";
157 nvidia,function = "sdio1";
158 };
159 slxd {
160 nvidia,pins = "slxd";
161 nvidia,function = "spdif";
162 };
163 spid {
164 nvidia,pins = "spid", "spie", "spif";
165 nvidia,function = "spi1";
166 };
167 spig {
168 nvidia,pins = "spig", "spih";
169 nvidia,function = "spi2_alt";
170 };
171 uaa {
172 nvidia,pins = "uaa", "uab", "uda";
173 nvidia,function = "ulpi";
174 };
175 uad {
176 nvidia,pins = "uad";
177 nvidia,function = "irda";
178 };
179 uca {
180 nvidia,pins = "uca", "ucb";
181 nvidia,function = "uartc";
182 };
183 conf_ata {
184 nvidia,pins = "ata", "atb", "atc", "atd",
185 "cdev1", "cdev2", "dap1", "dap2",
186 "dap4", "ddc", "dtf", "gma", "gmc",
187 "gme", "gpu", "gpu7", "i2cp", "irrx",
188 "irtx", "pta", "rm", "sdc", "sdd",
189 "slxc", "slxd", "slxk", "spdi", "spdo",
190 "uac", "uad", "uca", "ucb", "uda";
191 nvidia,pull = <0>;
192 nvidia,tristate = <0>;
193 };
194 conf_ate {
195 nvidia,pins = "ate", "csus", "dap3", "gmd",
196 "gpv", "owc", "spia", "spib", "spic",
197 "spid", "spie", "spig";
198 nvidia,pull = <0>;
199 nvidia,tristate = <1>;
200 };
201 conf_ck32 {
202 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
203 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
204 nvidia,pull = <0>;
205 };
206 conf_crtp {
207 nvidia,pins = "crtp", "gmb", "slxa", "spih";
208 nvidia,pull = <2>;
209 nvidia,tristate = <1>;
210 };
211 conf_dta {
212 nvidia,pins = "dta", "dtb", "dtc", "dtd";
213 nvidia,pull = <1>;
214 nvidia,tristate = <0>;
215 };
216 conf_dte {
217 nvidia,pins = "dte", "spif";
218 nvidia,pull = <1>;
219 nvidia,tristate = <1>;
220 };
221 conf_hdint {
222 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
223 "lpw1", "lsck", "lsda", "lsdi", "lvp0";
224 nvidia,tristate = <1>;
225 };
226 conf_kbca {
227 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
228 "kbce", "kbcf", "sdio1", "uaa", "uab";
229 nvidia,pull = <2>;
230 nvidia,tristate = <0>;
231 };
232 conf_lc {
233 nvidia,pins = "lc", "ls";
234 nvidia,pull = <2>;
235 };
236 conf_ld0 {
237 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
238 "ld5", "ld6", "ld7", "ld8", "ld9",
239 "ld10", "ld11", "ld12", "ld13", "ld14",
240 "ld15", "ld16", "ld17", "ldi", "lhp0",
241 "lhp1", "lhp2", "lhs", "lm0", "lpp",
242 "lpw0", "lpw2", "lsc0", "lsc1", "lspi",
243 "lvp1", "lvs", "pmc", "sdb";
244 nvidia,tristate = <0>;
245 };
246 conf_ld17_0 {
247 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
248 "ld23_22";
249 nvidia,pull = <1>;
250 };
c729429e
WN
251 drive_sdio1 {
252 nvidia,pins = "drive_sdio1";
253 nvidia,high-speed-mode = <0>;
254 nvidia,schmitt = <1>;
255 nvidia,low-power-mode = <3>;
256 nvidia,pull-down-strength = <31>;
257 nvidia,pull-up-strength = <31>;
258 nvidia,slew-rate-rising = <3>;
259 nvidia,slew-rate-falling = <3>;
260 };
ecc295bb 261 };
cf633464
MZ
262
263 state_i2cmux_ddc: pinmux_i2cmux_ddc {
264 ddc {
265 nvidia,pins = "ddc";
266 nvidia,function = "i2c2";
267 };
268 pta {
269 nvidia,pins = "pta";
270 nvidia,function = "rsvd4";
271 };
272 };
273
274 state_i2cmux_pta: pinmux_i2cmux_pta {
275 ddc {
276 nvidia,pins = "ddc";
277 nvidia,function = "rsvd4";
278 };
279 pta {
280 nvidia,pins = "pta";
281 nvidia,function = "i2c2";
282 };
283 };
284
285 state_i2cmux_idle: pinmux_i2cmux_idle {
286 ddc {
287 nvidia,pins = "ddc";
288 nvidia,function = "rsvd4";
289 };
290 pta {
291 nvidia,pins = "pta";
292 nvidia,function = "rsvd4";
293 };
294 };
ecc295bb
SW
295 };
296
2a5fdc9a
SW
297 i2s@70002800 {
298 status = "okay";
c04abb3a
SW
299 };
300
301 serial@70006300 {
2a5fdc9a 302 status = "okay";
c04abb3a
SW
303 };
304
88950f3b 305 i2c@7000c000 {
2a5fdc9a 306 status = "okay";
88950f3b 307 clock-frequency = <400000>;
797acf70
SW
308
309 wm8903: wm8903@1a {
310 compatible = "wlf,wm8903";
311 reg = <0x1a>;
312 interrupt-parent = <&gpio>;
95decf84 313 interrupts = <187 0x04>;
797acf70
SW
314
315 gpio-controller;
316 #gpio-cells = <2>;
317
318 micdet-cfg = <0>;
319 micdet-delay = <100>;
95decf84 320 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
797acf70 321 };
b46b0b54
LD
322
323 /* ALS and proximity sensor */
324 isl29018@44 {
325 compatible = "isil,isl29018";
326 reg = <0x44>;
327 interrupt-parent = <&gpio>;
328 interrupts = <202 0x04>; /*gpio PZ2 */
329 };
88950f3b
SW
330 };
331
332 i2c@7000c400 {
2a5fdc9a 333 status = "okay";
97d5520f 334 clock-frequency = <100000>;
88950f3b
SW
335 };
336
cf633464
MZ
337 i2cmux {
338 compatible = "i2c-mux-pinctrl";
339 #address-cells = <1>;
340 #size-cells = <0>;
341
342 i2c-parent = <&{/i2c@7000c400}>;
343
344 pinctrl-names = "ddc", "pta", "idle";
345 pinctrl-0 = <&state_i2cmux_ddc>;
346 pinctrl-1 = <&state_i2cmux_pta>;
347 pinctrl-2 = <&state_i2cmux_idle>;
348
97d5520f 349 hdmi_ddc: i2c@0 {
cf633464
MZ
350 reg = <0>;
351 #address-cells = <1>;
352 #size-cells = <0>;
353 };
354
355 i2c@1 {
356 reg = <1>;
357 #address-cells = <1>;
358 #size-cells = <0>;
359 };
360 };
361
88950f3b 362 i2c@7000c500 {
2a5fdc9a 363 status = "okay";
88950f3b
SW
364 clock-frequency = <400000>;
365 };
366
367 i2c@7000d000 {
2a5fdc9a 368 status = "okay";
88950f3b 369 clock-frequency = <400000>;
017a0104
SW
370
371 pmic: tps6586x@34 {
372 compatible = "ti,tps6586x";
373 reg = <0x34>;
374 interrupts = <0 86 0x4>;
375
44b12ef7
SW
376 ti,system-power-controller;
377
017a0104
SW
378 #gpio-cells = <2>;
379 gpio-controller;
380
381 sys-supply = <&vdd_5v0_reg>;
382 vin-sm0-supply = <&sys_reg>;
383 vin-sm1-supply = <&sys_reg>;
384 vin-sm2-supply = <&sys_reg>;
385 vinldo01-supply = <&sm2_reg>;
386 vinldo23-supply = <&sm2_reg>;
387 vinldo4-supply = <&sm2_reg>;
388 vinldo678-supply = <&sm2_reg>;
389 vinldo9-supply = <&sm2_reg>;
390
391 regulators {
b9c665d7 392 sys_reg: sys {
017a0104
SW
393 regulator-name = "vdd_sys";
394 regulator-always-on;
395 };
396
b9c665d7 397 sm0 {
017a0104
SW
398 regulator-name = "vdd_sm0,vdd_core";
399 regulator-min-microvolt = <1200000>;
400 regulator-max-microvolt = <1200000>;
401 regulator-always-on;
402 };
403
b9c665d7 404 sm1 {
017a0104
SW
405 regulator-name = "vdd_sm1,vdd_cpu";
406 regulator-min-microvolt = <1000000>;
407 regulator-max-microvolt = <1000000>;
408 regulator-always-on;
409 };
410
b9c665d7 411 sm2_reg: sm2 {
017a0104
SW
412 regulator-name = "vdd_sm2,vin_ldo*";
413 regulator-min-microvolt = <3700000>;
414 regulator-max-microvolt = <3700000>;
415 regulator-always-on;
416 };
417
418 /* LDO0 is not connected to anything */
419
b9c665d7 420 ldo1 {
017a0104
SW
421 regulator-name = "vdd_ldo1,avdd_pll*";
422 regulator-min-microvolt = <1100000>;
423 regulator-max-microvolt = <1100000>;
424 regulator-always-on;
425 };
426
b9c665d7 427 ldo2 {
017a0104
SW
428 regulator-name = "vdd_ldo2,vdd_rtc";
429 regulator-min-microvolt = <1200000>;
430 regulator-max-microvolt = <1200000>;
431 };
432
b9c665d7 433 ldo3 {
017a0104
SW
434 regulator-name = "vdd_ldo3,avdd_usb*";
435 regulator-min-microvolt = <3300000>;
436 regulator-max-microvolt = <3300000>;
437 regulator-always-on;
438 };
439
b9c665d7 440 ldo4 {
017a0104
SW
441 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
442 regulator-min-microvolt = <1800000>;
443 regulator-max-microvolt = <1800000>;
444 regulator-always-on;
445 };
446
b9c665d7 447 ldo5 {
017a0104
SW
448 regulator-name = "vdd_ldo5,vcore_mmc";
449 regulator-min-microvolt = <2850000>;
450 regulator-max-microvolt = <2850000>;
451 regulator-always-on;
452 };
453
b9c665d7 454 ldo6 {
017a0104
SW
455 regulator-name = "vdd_ldo6,avdd_vdac";
456 regulator-min-microvolt = <1800000>;
457 regulator-max-microvolt = <1800000>;
458 };
459
97d5520f 460 hdmi_vdd_reg: ldo7 {
017a0104
SW
461 regulator-name = "vdd_ldo7,avdd_hdmi,vdd_fuse";
462 regulator-min-microvolt = <3300000>;
463 regulator-max-microvolt = <3300000>;
464 };
465
97d5520f 466 hdmi_pll_reg: ldo8 {
017a0104
SW
467 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
468 regulator-min-microvolt = <1800000>;
469 regulator-max-microvolt = <1800000>;
470 };
471
b9c665d7 472 ldo9 {
017a0104
SW
473 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
474 regulator-min-microvolt = <2850000>;
475 regulator-max-microvolt = <2850000>;
476 regulator-always-on;
477 };
478
b9c665d7 479 ldo_rtc {
017a0104
SW
480 regulator-name = "vdd_rtc_out,vdd_cell";
481 regulator-min-microvolt = <3300000>;
482 regulator-max-microvolt = <3300000>;
483 regulator-always-on;
484 };
485 };
486 };
ee9f7260
TR
487
488 temperature-sensor@4c {
489 compatible = "onnn,nct1008";
490 reg = <0x4c>;
491 };
017a0104
SW
492 };
493
494 pmc {
495 nvidia,invert-interrupt;
88950f3b
SW
496 };
497
2a5fdc9a
SW
498 usb@c5000000 {
499 status = "okay";
c04abb3a
SW
500 };
501
2a5fdc9a
SW
502 usb@c5004000 {
503 status = "okay";
504 nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
797acf70
SW
505 };
506
2a5fdc9a
SW
507 usb@c5008000 {
508 status = "okay";
c04abb3a
SW
509 };
510
c729429e
WN
511 sdhci@c8000000 {
512 status = "okay";
513 power-gpios = <&gpio 86 0>; /* gpio PK6 */
514 bus-width = <4>;
515 };
516
c04abb3a 517 sdhci@c8000400 {
2a5fdc9a 518 status = "okay";
c04abb3a
SW
519 cd-gpios = <&gpio 69 0>; /* gpio PI5 */
520 wp-gpios = <&gpio 57 0>; /* gpio PH1 */
521 power-gpios = <&gpio 70 0>; /* gpio PI6 */
deb88cc3 522 bus-width = <4>;
c04abb3a
SW
523 };
524
525 sdhci@c8000600 {
2a5fdc9a 526 status = "okay";
deb88cc3 527 bus-width = <8>;
c04abb3a
SW
528 };
529
017a0104
SW
530 regulators {
531 compatible = "simple-bus";
532 #address-cells = <1>;
533 #size-cells = <0>;
534
535 vdd_5v0_reg: regulator@0 {
536 compatible = "regulator-fixed";
537 reg = <0>;
538 regulator-name = "vdd_5v0";
539 regulator-min-microvolt = <5000000>;
540 regulator-max-microvolt = <5000000>;
541 regulator-always-on;
542 };
543
544 regulator@1 {
545 compatible = "regulator-fixed";
546 reg = <1>;
547 regulator-name = "vdd_1v5";
548 regulator-min-microvolt = <1500000>;
549 regulator-max-microvolt = <1500000>;
550 gpio = <&pmic 0 0>;
551 };
552
553 regulator@2 {
554 compatible = "regulator-fixed";
555 reg = <2>;
556 regulator-name = "vdd_1v2";
557 regulator-min-microvolt = <1200000>;
558 regulator-max-microvolt = <1200000>;
559 gpio = <&pmic 1 0>;
560 enable-active-high;
561 };
562
563 regulator@3 {
564 compatible = "regulator-fixed";
565 reg = <3>;
566 regulator-name = "vdd_pnl";
567 regulator-min-microvolt = <2800000>;
568 regulator-max-microvolt = <2800000>;
569 gpio = <&gpio 22 0>; /* gpio PC6 */
570 enable-active-high;
571 };
572
573 regulator@4 {
574 compatible = "regulator-fixed";
575 reg = <4>;
576 regulator-name = "vdd_bl";
577 regulator-min-microvolt = <2800000>;
578 regulator-max-microvolt = <2800000>;
579 gpio = <&gpio 176 0>; /* gpio PW0 */
580 enable-active-high;
581 };
582 };
583
797acf70
SW
584 sound {
585 compatible = "nvidia,tegra-audio-wm8903-ventana",
586 "nvidia,tegra-audio-wm8903";
587 nvidia,model = "NVIDIA Tegra Ventana";
588
589 nvidia,audio-routing =
590 "Headphone Jack", "HPOUTR",
591 "Headphone Jack", "HPOUTL",
592 "Int Spk", "ROP",
593 "Int Spk", "RON",
594 "Int Spk", "LOP",
595 "Int Spk", "LON",
596 "Mic Jack", "MICBIAS",
597 "IN1L", "Mic Jack";
598
599 nvidia,i2s-controller = <&tegra_i2s1>;
600 nvidia,audio-codec = <&wm8903>;
601
602 nvidia,spkr-en-gpios = <&wm8903 2 0>;
603 nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
c44e438a 604 nvidia,int-mic-en-gpios = <&gpio 184 0>; /* gpio PX0 */
797acf70
SW
605 nvidia,ext-mic-en-gpios = <&gpio 185 0>; /* gpio PX1 */
606 };
add29e61 607};
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