[deliverable/linux.git] / arch / arm / boot / dts / tegra20.dtsi

/include/ "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra20";
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &uarta;
		serial1 = &uartb;
		serial2 = &uartc;
		serial3 = &uartd;
		serial4 = &uarte;
	};

	host1x {
		compatible = "nvidia,tegra20-host1x", "simple-bus";
		reg = <0x50000000 0x00024000>;
		interrupts = <0 65 0x04   /* mpcore syncpt */
			      0 67 0x04>; /* mpcore general */
		clocks = <&tegra_car 28>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe {
			compatible = "nvidia,tegra20-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <0 68 0x04>;
			clocks = <&tegra_car 60>;
		};

		vi {
			compatible = "nvidia,tegra20-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <0 69 0x04>;
			clocks = <&tegra_car 100>;
		};

		epp {
			compatible = "nvidia,tegra20-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <0 70 0x04>;
			clocks = <&tegra_car 19>;
		};

		isp {
			compatible = "nvidia,tegra20-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <0 71 0x04>;
			clocks = <&tegra_car 23>;
		};

		gr2d {
			compatible = "nvidia,tegra20-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <0 72 0x04>;
			clocks = <&tegra_car 21>;
		};

		gr3d {
			compatible = "nvidia,tegra20-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car 24>;
		};

		dc@54200000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <0 73 0x04>;
			clocks = <&tegra_car 27>, <&tegra_car 121>;
			clock-names = "disp1", "parent";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <0 74 0x04>;
			clocks = <&tegra_car 26>, <&tegra_car 121>;
			clock-names = "disp2", "parent";

			rgb {
				status = "disabled";
			};
		};

		hdmi {
			compatible = "nvidia,tegra20-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <0 75 0x04>;
			clocks = <&tegra_car 51>, <&tegra_car 117>;
			clock-names = "hdmi", "parent";
			status = "disabled";
		};

		tvo {
			compatible = "nvidia,tegra20-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <0 76 0x04>;
			clocks = <&tegra_car 102>;
			status = "disabled";
		};

		dsi {
			compatible = "nvidia,tegra20-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car 48>;
			status = "disabled";
		};
	};

	timer@50004600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x50040600 0x20>;
		interrupts = <1 13 0x304>;
		clocks = <&tegra_car 132>;
	};

	intc: interrupt-controller {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0x50043000 0x1000>;
		arm,data-latency = <5 5 2>;
		arm,tag-latency = <4 4 2>;
		cache-unified;
		cache-level = <2>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra20-timer";
		reg = <0x60005000 0x60>;
		interrupts = <0 0 0x04
			      0 1 0x04
			      0 41 0x04
			      0 42 0x04>;
		clocks = <&tegra_car 5>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra20-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1200>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04>;
		clocks = <&tegra_car 34>;
	};

	ahb {
		compatible = "nvidia,tegra20-ahb";
		reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio {
		compatible = "nvidia,tegra20-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <0 32 0x04
			      0 33 0x04
			      0 34 0x04
			      0 35 0x04
			      0 55 0x04
			      0 87 0x04
			      0 89 0x04>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra20-pinmux";
		reg = <0x70000014 0x10   /* Tri-state registers */
		       0x70000080 0x20   /* Mux registers */
		       0x700000a0 0x14   /* Pull-up/down registers */
		       0x70000868 0xa8>; /* Pad control registers */
	};

	das {
		compatible = "nvidia,tegra20-das";
		reg = <0x70000c00 0x80>;
	};

	tegra_ac97: ac97 {
		compatible = "nvidia,tegra20-ac97";
		reg = <0x70002000 0x200>;
		interrupts = <0 81 0x04>;
		nvidia,dma-request-selector = <&apbdma 12>;
		clocks = <&tegra_car 3>;
		status = "disabled";
	};

	tegra_i2s1: i2s@70002800 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002800 0x200>;
		interrupts = <0 13 0x04>;
		nvidia,dma-request-selector = <&apbdma 2>;
		clocks = <&tegra_car 11>;
		status = "disabled";
	};

	tegra_i2s2: i2s@70002a00 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002a00 0x200>;
		interrupts = <0 3 0x04>;
		nvidia,dma-request-selector = <&apbdma 1>;
		clocks = <&tegra_car 18>;
		status = "disabled";
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
	 * driver, the comptible is "nvidia,tegra20-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <0 36 0x04>;
		nvidia,dma-request-selector = <&apbdma 8>;
		clocks = <&tegra_car 6>;
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <0 37 0x04>;
		nvidia,dma-request-selector = <&apbdma 9>;
		clocks = <&tegra_car 96>;
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <0 46 0x04>;
		nvidia,dma-request-selector = <&apbdma 10>;
		clocks = <&tegra_car 55>;
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <0 90 0x04>;
		nvidia,dma-request-selector = <&apbdma 19>;
		clocks = <&tegra_car 65>;
		status = "disabled";
	};

	uarte: serial@70006400 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <0 91 0x04>;
		nvidia,dma-request-selector = <&apbdma 20>;
		clocks = <&tegra_car 66>;
		status = "disabled";
	};

	pwm: pwm {
		compatible = "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car 17>;
		status = "disabled";
	};

	rtc {
		compatible = "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <0 2 0x04>;
		clocks = <&tegra_car 4>;
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <0 38 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000c380 {
		compatible = "nvidia,tegra20-sflash";
		reg = <0x7000c380 0x80>;
		interrupts = <0 39 0x04>;
		nvidia,dma-request-selector = <&apbdma 11>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 43>;
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <0 84 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <0 92 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra20-i2c-dvc";
		reg = <0x7000d000 0x200>;
		interrupts = <0 53 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d400 0x200>;
		interrupts = <0 59 0x04>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 41>;
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d600 0x200>;
		interrupts = <0 82 0x04>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 44>;
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d800 0x200>;
		interrupts = <0 83 0x04>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 46>;
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000da00 0x200>;
		interrupts = <0 93 0x04>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 68>;
		status = "disabled";
	};

	kbc {
		compatible = "nvidia,tegra20-kbc";
		reg = <0x7000e200 0x100>;
		interrupts = <0 85 0x04>;
		clocks = <&tegra_car 36>;
		status = "disabled";
	};

	pmc {
		compatible = "nvidia,tegra20-pmc";
		reg = <0x7000e400 0x400>;
		clocks = <&tegra_car 110>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
	};

	memory-controller@7000f000 {
		compatible = "nvidia,tegra20-mc";
		reg = <0x7000f000 0x024
		       0x7000f03c 0x3c4>;
		interrupts = <0 77 0x04>;
	};

	iommu {
		compatible = "nvidia,tegra20-gart";
		reg = <0x7000f024 0x00000018	/* controller registers */
		       0x58000000 0x02000000>;	/* GART aperture */
	};

	memory-controller@7000f400 {
		compatible = "nvidia,tegra20-emc";
		reg = <0x7000f400 0x200>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	usb@c5000000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5000000 0x4000>;
		interrupts = <0 20 0x04>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
		clocks = <&tegra_car 22>;
		nvidia,needs-double-reset;
		nvidia,phy = <&phy1>;
		status = "disabled";
	};

	phy1: usb-phy@c5000400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5000400 0x3c00>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
		clocks = <&tegra_car 22>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	usb@c5004000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5004000 0x4000>;
		interrupts = <0 21 0x04>;
		phy_type = "ulpi";
		clocks = <&tegra_car 58>;
		nvidia,phy = <&phy2>;
		status = "disabled";
	};

	phy2: usb-phy@c5004400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5004400 0x3c00>;
		phy_type = "ulpi";
		clocks = <&tegra_car 93>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	usb@c5008000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5008000 0x4000>;
		interrupts = <0 97 0x04>;
		phy_type = "utmi";
		clocks = <&tegra_car 59>;
		nvidia,phy = <&phy3>;
		status = "disabled";
	};

	phy3: usb-phy@c5008400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5008400 0x3c00>;
		phy_type = "utmi";
		clocks = <&tegra_car 22>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	sdhci@c8000000 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000000 0x200>;
		interrupts = <0 14 0x04>;
		clocks = <&tegra_car 14>;
		status = "disabled";
	};

	sdhci@c8000200 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000200 0x200>;
		interrupts = <0 15 0x04>;
		clocks = <&tegra_car 9>;
		status = "disabled";
	};

	sdhci@c8000400 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000400 0x200>;
		interrupts = <0 19 0x04>;
		clocks = <&tegra_car 69>;
		status = "disabled";
	};

	sdhci@c8000600 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000600 0x200>;
		interrupts = <0 31 0x04>;
		clocks = <&tegra_car 15>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 56 0x04
			      0 57 0x04>;
	};
};
Commit	Line	Data
8e267f3d GL	1	/include/ "skeleton.dtsi"
	2
	3	/ {
	4	compatible = "nvidia,tegra20";
	5	interrupt-parent = <&intc>;
	6
b6551bb9 LD	7	aliases {
	8	serial0 = &uarta;
	9	serial1 = &uartb;
	10	serial2 = &uartc;
	11	serial3 = &uartd;
	12	serial4 = &uarte;
	13	};
	14
ed821f07 TR	15	host1x {
	16	compatible = "nvidia,tegra20-host1x", "simple-bus";
	17	reg = <0x50000000 0x00024000>;
	18	interrupts = <0 65 0x04 /* mpcore syncpt */
	19	0 67 0x04>; /* mpcore general */
8d8b43da	20	clocks = <&tegra_car 28>;
ed821f07 TR	21
	22	#address-cells = <1>;
	23	#size-cells = <1>;
	24
	25	ranges = <0x54000000 0x54000000 0x04000000>;
	26
	27	mpe {
	28	compatible = "nvidia,tegra20-mpe";
	29	reg = <0x54040000 0x00040000>;
	30	interrupts = <0 68 0x04>;
8d8b43da	31	clocks = <&tegra_car 60>;
ed821f07 TR	32	};
	33
	34	vi {
	35	compatible = "nvidia,tegra20-vi";
	36	reg = <0x54080000 0x00040000>;
	37	interrupts = <0 69 0x04>;
8d8b43da	38	clocks = <&tegra_car 100>;
ed821f07 TR	39	};
	40
	41	epp {
	42	compatible = "nvidia,tegra20-epp";
	43	reg = <0x540c0000 0x00040000>;
	44	interrupts = <0 70 0x04>;
8d8b43da	45	clocks = <&tegra_car 19>;
ed821f07 TR	46	};
	47
	48	isp {
	49	compatible = "nvidia,tegra20-isp";
	50	reg = <0x54100000 0x00040000>;
	51	interrupts = <0 71 0x04>;
8d8b43da	52	clocks = <&tegra_car 23>;
ed821f07 TR	53	};
	54
	55	gr2d {
	56	compatible = "nvidia,tegra20-gr2d";
	57	reg = <0x54140000 0x00040000>;
	58	interrupts = <0 72 0x04>;
8d8b43da	59	clocks = <&tegra_car 21>;
ed821f07 TR	60	};
	61
	62	gr3d {
	63	compatible = "nvidia,tegra20-gr3d";
	64	reg = <0x54180000 0x00040000>;
8d8b43da	65	clocks = <&tegra_car 24>;
ed821f07 TR	66	};
	67
	68	dc@54200000 {
	69	compatible = "nvidia,tegra20-dc";
	70	reg = <0x54200000 0x00040000>;
	71	interrupts = <0 73 0x04>;
8d8b43da PG	72	clocks = <&tegra_car 27>, <&tegra_car 121>;
8d8b43da PG	73	clock-names = "disp1", "parent";
ed821f07 TR	74
	75	rgb {
	76	status = "disabled";
	77	};
	78	};
	79
	80	dc@54240000 {
	81	compatible = "nvidia,tegra20-dc";
	82	reg = <0x54240000 0x00040000>;
	83	interrupts = <0 74 0x04>;
8d8b43da PG	84	clocks = <&tegra_car 26>, <&tegra_car 121>;
8d8b43da PG	85	clock-names = "disp2", "parent";
ed821f07 TR	86
	87	rgb {
	88	status = "disabled";
	89	};
	90	};
	91
	92	hdmi {
	93	compatible = "nvidia,tegra20-hdmi";
	94	reg = <0x54280000 0x00040000>;
	95	interrupts = <0 75 0x04>;
8d8b43da PG	96	clocks = <&tegra_car 51>, <&tegra_car 117>;
8d8b43da PG	97	clock-names = "hdmi", "parent";
ed821f07 TR	98	status = "disabled";
	99	};
	100
	101	tvo {
	102	compatible = "nvidia,tegra20-tvo";
	103	reg = <0x542c0000 0x00040000>;
	104	interrupts = <0 76 0x04>;
8d8b43da	105	clocks = <&tegra_car 102>;
ed821f07 TR	106	status = "disabled";
	107	};
	108
	109	dsi {
	110	compatible = "nvidia,tegra20-dsi";
	111	reg = <0x54300000 0x00040000>;
8d8b43da	112	clocks = <&tegra_car 48>;
ed821f07 TR	113	status = "disabled";
	114	};
	115	};
	116
73368ba0 SW	117	timer@50004600 {
	118	compatible = "arm,cortex-a9-twd-timer";
	119	reg = <0x50040600 0x20>;
	120	interrupts = <1 13 0x304>;
ed3ced37	121	clocks = <&tegra_car 132>;
73368ba0 SW	122	};
73368ba0 SW	123
f9eb26a4	124	intc: interrupt-controller {
0d4f7479	125	compatible = "arm,cortex-a9-gic";
5ff48887 SW	126	reg = <0x50041000 0x1000
5ff48887 SW	127	0x50040100 0x0100>;
2eaab06e SW	128	interrupt-controller;
2eaab06e SW	129	#interrupt-cells = <3>;
8e267f3d GL	130	};
8e267f3d GL	131
bb2c1de9 SW	132	cache-controller {
	133	compatible = "arm,pl310-cache";
	134	reg = <0x50043000 0x1000>;
	135	arm,data-latency = <5 5 2>;
	136	arm,tag-latency = <4 4 2>;
	137	cache-unified;
	138	cache-level = <2>;
	139	};
	140
2f2b7fb2 SW	141	timer@60005000 {
	142	compatible = "nvidia,tegra20-timer";
	143	reg = <0x60005000 0x60>;
	144	interrupts = <0 0 0x04
	145	0 1 0x04
	146	0 41 0x04
	147	0 42 0x04>;
6f88fb8a	148	clocks = <&tegra_car 5>;
2f2b7fb2 SW	149	};
2f2b7fb2 SW	150
270f8ce3 SW	151	tegra_car: clock {
	152	compatible = "nvidia,tegra20-car";
	153	reg = <0x60006000 0x1000>;
	154	#clock-cells = <1>;
	155	};
	156
f9eb26a4	157	apbdma: dma {
8051b75a SW	158	compatible = "nvidia,tegra20-apbdma";
8051b75a SW	159	reg = <0x6000a000 0x1200>;
95decf84 SW	160	interrupts = <0 104 0x04
	161	0 105 0x04
	162	0 106 0x04
	163	0 107 0x04
	164	0 108 0x04
	165	0 109 0x04
	166	0 110 0x04
	167	0 111 0x04
	168	0 112 0x04
	169	0 113 0x04
	170	0 114 0x04
	171	0 115 0x04
	172	0 116 0x04
	173	0 117 0x04
	174	0 118 0x04
	175	0 119 0x04>;
8d8b43da	176	clocks = <&tegra_car 34>;
8051b75a SW	177	};
8051b75a SW	178
c04abb3a SW	179	ahb {
	180	compatible = "nvidia,tegra20-ahb";
	181	reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
8e267f3d GL	182	};
8e267f3d GL	183
f9eb26a4	184	gpio: gpio {
8e267f3d	185	compatible = "nvidia,tegra20-gpio";
95decf84 SW	186	reg = <0x6000d000 0x1000>;
	187	interrupts = <0 32 0x04
	188	0 33 0x04
	189	0 34 0x04
	190	0 35 0x04
	191	0 55 0x04
	192	0 87 0x04
	193	0 89 0x04>;
8e267f3d GL	194	#gpio-cells = <2>;
8e267f3d GL	195	gpio-controller;
6f74dc9b SW	196	#interrupt-cells = <2>;
6f74dc9b SW	197	interrupt-controller;
8e267f3d GL	198	};
8e267f3d GL	199
f9eb26a4	200	pinmux: pinmux {
f62f548c	201	compatible = "nvidia,tegra20-pinmux";
95decf84 SW	202	reg = <0x70000014 0x10 /* Tri-state registers */
	203	0x70000080 0x20 /* Mux registers */
	204	0x700000a0 0x14 /* Pull-up/down registers */
	205	0x70000868 0xa8>; /* Pad control registers */
f62f548c SW	206	};
f62f548c SW	207
c04abb3a SW	208	das {
	209	compatible = "nvidia,tegra20-das";
	210	reg = <0x70000c00 0x80>;
	211	};
fc5c306b	212
0698ed19 LS	213	tegra_ac97: ac97 {
	214	compatible = "nvidia,tegra20-ac97";
	215	reg = <0x70002000 0x200>;
	216	interrupts = <0 81 0x04>;
	217	nvidia,dma-request-selector = <&apbdma 12>;
	218	clocks = <&tegra_car 3>;
	219	status = "disabled";
	220	};
c04abb3a SW	221
	222	tegra_i2s1: i2s@70002800 {
	223	compatible = "nvidia,tegra20-i2s";
	224	reg = <0x70002800 0x200>;
	225	interrupts = <0 13 0x04>;
	226	nvidia,dma-request-selector = <&apbdma 2>;
8d8b43da	227	clocks = <&tegra_car 11>;
223ef78d	228	status = "disabled";
c04abb3a SW	229	};
	230
	231	tegra_i2s2: i2s@70002a00 {
	232	compatible = "nvidia,tegra20-i2s";
	233	reg = <0x70002a00 0x200>;
	234	interrupts = <0 3 0x04>;
	235	nvidia,dma-request-selector = <&apbdma 1>;
8d8b43da	236	clocks = <&tegra_car 18>;
223ef78d	237	status = "disabled";
c04abb3a SW	238	};
c04abb3a SW	239
b6551bb9 LD	240	/*
	241	* There are two serial driver i.e. 8250 based simple serial
	242	* driver and APB DMA based serial driver for higher baudrate
	243	* and performace. To enable the 8250 based driver, the compatible
	244	* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
	245	* driver, the comptible is "nvidia,tegra20-hsuart".
	246	*/
	247	uarta: serial@70006000 {
8e267f3d GL	248	compatible = "nvidia,tegra20-uart";
	249	reg = <0x70006000 0x40>;
	250	reg-shift = <2>;
95decf84	251	interrupts = <0 36 0x04>;
b6551bb9	252	nvidia,dma-request-selector = <&apbdma 8>;
8d8b43da	253	clocks = <&tegra_car 6>;
223ef78d	254	status = "disabled";
8e267f3d GL	255	};
8e267f3d GL	256
b6551bb9	257	uartb: serial@70006040 {
8e267f3d GL	258	compatible = "nvidia,tegra20-uart";
	259	reg = <0x70006040 0x40>;
	260	reg-shift = <2>;
95decf84	261	interrupts = <0 37 0x04>;
b6551bb9	262	nvidia,dma-request-selector = <&apbdma 9>;
8d8b43da	263	clocks = <&tegra_car 96>;
223ef78d	264	status = "disabled";
8e267f3d GL	265	};
8e267f3d GL	266
b6551bb9	267	uartc: serial@70006200 {
8e267f3d GL	268	compatible = "nvidia,tegra20-uart";
	269	reg = <0x70006200 0x100>;
	270	reg-shift = <2>;
95decf84	271	interrupts = <0 46 0x04>;
b6551bb9	272	nvidia,dma-request-selector = <&apbdma 10>;
8d8b43da	273	clocks = <&tegra_car 55>;
223ef78d	274	status = "disabled";
8e267f3d GL	275	};
8e267f3d GL	276
b6551bb9	277	uartd: serial@70006300 {
8e267f3d GL	278	compatible = "nvidia,tegra20-uart";
	279	reg = <0x70006300 0x100>;
	280	reg-shift = <2>;
95decf84	281	interrupts = <0 90 0x04>;
b6551bb9	282	nvidia,dma-request-selector = <&apbdma 19>;
8d8b43da	283	clocks = <&tegra_car 65>;
223ef78d	284	status = "disabled";
8e267f3d GL	285	};
8e267f3d GL	286
b6551bb9	287	uarte: serial@70006400 {
8e267f3d GL	288	compatible = "nvidia,tegra20-uart";
	289	reg = <0x70006400 0x100>;
	290	reg-shift = <2>;
95decf84	291	interrupts = <0 91 0x04>;
b6551bb9	292	nvidia,dma-request-selector = <&apbdma 20>;
8d8b43da	293	clocks = <&tegra_car 66>;
223ef78d	294	status = "disabled";
8e267f3d GL	295	};
8e267f3d GL	296
2b8b15da	297	pwm: pwm {
140fd977 TR	298	compatible = "nvidia,tegra20-pwm";
	299	reg = <0x7000a000 0x100>;
	300	#pwm-cells = <2>;
8d8b43da	301	clocks = <&tegra_car 17>;
b69cd984	302	status = "disabled";
140fd977 TR	303	};
140fd977 TR	304
380e04ac SW	305	rtc {
	306	compatible = "nvidia,tegra20-rtc";
	307	reg = <0x7000e000 0x100>;
	308	interrupts = <0 2 0x04>;
6f88fb8a	309	clocks = <&tegra_car 4>;
380e04ac SW	310	};
380e04ac SW	311
c04abb3a	312	i2c@7000c000 {
c04abb3a SW	313	compatible = "nvidia,tegra20-i2c";
	314	reg = <0x7000c000 0x100>;
	315	interrupts = <0 38 0x04>;
2eaab06e SW	316	#address-cells = <1>;
2eaab06e SW	317	#size-cells = <0>;
8d8b43da PG	318	clocks = <&tegra_car 12>, <&tegra_car 124>;
8d8b43da PG	319	clock-names = "div-clk", "fast-clk";
223ef78d	320	status = "disabled";
0c6700ab OJ	321	};
0c6700ab OJ	322
fa98a114 LD	323	spi@7000c380 {
	324	compatible = "nvidia,tegra20-sflash";
	325	reg = <0x7000c380 0x80>;
	326	interrupts = <0 39 0x04>;
	327	nvidia,dma-request-selector = <&apbdma 11>;
	328	#address-cells = <1>;
	329	#size-cells = <0>;
8d8b43da	330	clocks = <&tegra_car 43>;
fa98a114 LD	331	status = "disabled";
	332	};
	333
c04abb3a	334	i2c@7000c400 {
c04abb3a SW	335	compatible = "nvidia,tegra20-i2c";
	336	reg = <0x7000c400 0x100>;
	337	interrupts = <0 84 0x04>;
2eaab06e SW	338	#address-cells = <1>;
2eaab06e SW	339	#size-cells = <0>;
8d8b43da PG	340	clocks = <&tegra_car 54>, <&tegra_car 124>;
8d8b43da PG	341	clock-names = "div-clk", "fast-clk";
223ef78d	342	status = "disabled";
8e267f3d GL	343	};
8e267f3d GL	344
c04abb3a	345	i2c@7000c500 {
c04abb3a SW	346	compatible = "nvidia,tegra20-i2c";
	347	reg = <0x7000c500 0x100>;
	348	interrupts = <0 92 0x04>;
2eaab06e SW	349	#address-cells = <1>;
2eaab06e SW	350	#size-cells = <0>;
8d8b43da PG	351	clocks = <&tegra_car 67>, <&tegra_car 124>;
8d8b43da PG	352	clock-names = "div-clk", "fast-clk";
223ef78d	353	status = "disabled";
8e267f3d GL	354	};
8e267f3d GL	355
c04abb3a	356	i2c@7000d000 {
c04abb3a SW	357	compatible = "nvidia,tegra20-i2c-dvc";
	358	reg = <0x7000d000 0x200>;
	359	interrupts = <0 53 0x04>;
2eaab06e SW	360	#address-cells = <1>;
2eaab06e SW	361	#size-cells = <0>;
8d8b43da PG	362	clocks = <&tegra_car 47>, <&tegra_car 124>;
8d8b43da PG	363	clock-names = "div-clk", "fast-clk";
223ef78d	364	status = "disabled";
8e267f3d GL	365	};
8e267f3d GL	366
a86b0db3 LD	367	spi@7000d400 {
	368	compatible = "nvidia,tegra20-slink";
	369	reg = <0x7000d400 0x200>;
	370	interrupts = <0 59 0x04>;
	371	nvidia,dma-request-selector = <&apbdma 15>;
	372	#address-cells = <1>;
	373	#size-cells = <0>;
8d8b43da	374	clocks = <&tegra_car 41>;
a86b0db3 LD	375	status = "disabled";
	376	};
	377
	378	spi@7000d600 {
	379	compatible = "nvidia,tegra20-slink";
	380	reg = <0x7000d600 0x200>;
	381	interrupts = <0 82 0x04>;
	382	nvidia,dma-request-selector = <&apbdma 16>;
	383	#address-cells = <1>;
	384	#size-cells = <0>;
8d8b43da	385	clocks = <&tegra_car 44>;
a86b0db3 LD	386	status = "disabled";
	387	};
	388
	389	spi@7000d800 {
	390	compatible = "nvidia,tegra20-slink";
57471c8d	391	reg = <0x7000d800 0x200>;
a86b0db3 LD	392	interrupts = <0 83 0x04>;
	393	nvidia,dma-request-selector = <&apbdma 17>;
	394	#address-cells = <1>;
	395	#size-cells = <0>;
8d8b43da	396	clocks = <&tegra_car 46>;
a86b0db3 LD	397	status = "disabled";
	398	};
	399
	400	spi@7000da00 {
	401	compatible = "nvidia,tegra20-slink";
	402	reg = <0x7000da00 0x200>;
	403	interrupts = <0 93 0x04>;
	404	nvidia,dma-request-selector = <&apbdma 18>;
	405	#address-cells = <1>;
	406	#size-cells = <0>;
8d8b43da	407	clocks = <&tegra_car 68>;
a86b0db3 LD	408	status = "disabled";
	409	};
	410
699ed4b9 LD	411	kbc {
	412	compatible = "nvidia,tegra20-kbc";
	413	reg = <0x7000e200 0x100>;
	414	interrupts = <0 85 0x04>;
	415	clocks = <&tegra_car 36>;
	416	status = "disabled";
	417	};
	418
c04abb3a SW	419	pmc {
	420	compatible = "nvidia,tegra20-pmc";
	421	reg = <0x7000e400 0x400>;
7021d122 JL	422	clocks = <&tegra_car 110>, <&clk32k_in>;
7021d122 JL	423	clock-names = "pclk", "clk32k_in";
c04abb3a SW	424	};
c04abb3a SW	425
bbfc33bd	426	memory-controller@7000f000 {
c04abb3a SW	427	compatible = "nvidia,tegra20-mc";
	428	reg = <0x7000f000 0x024
	429	0x7000f03c 0x3c4>;
	430	interrupts = <0 77 0x04>;
	431	};
	432
109269e8	433	iommu {
c04abb3a SW	434	compatible = "nvidia,tegra20-gart";
	435	reg = <0x7000f024 0x00000018 /* controller registers */
	436	0x58000000 0x02000000>; /* GART aperture */
	437	};
	438
bbfc33bd	439	memory-controller@7000f400 {
c04abb3a SW	440	compatible = "nvidia,tegra20-emc";
c04abb3a SW	441	reg = <0x7000f400 0x200>;
2eaab06e SW	442	#address-cells = <1>;
2eaab06e SW	443	#size-cells = <0>;
8e267f3d	444	};
c27317c0 OJ	445
	446	usb@c5000000 {
	447	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	448	reg = <0xc5000000 0x4000>;
95decf84	449	interrupts = <0 20 0x04>;
c27317c0	450	phy_type = "utmi";
ba202f15	451	nvidia,has-legacy-mode;
8d8b43da	452	clocks = <&tegra_car 22>;
b4e07478	453	nvidia,needs-double-reset;
e374b65c	454	nvidia,phy = <&phy1>;
223ef78d	455	status = "disabled";
c27317c0 OJ	456	};
c27317c0 OJ	457
5d324410 SW	458	phy1: usb-phy@c5000400 {
	459	compatible = "nvidia,tegra20-usb-phy";
	460	reg = <0xc5000400 0x3c00>;
	461	phy_type = "utmi";
	462	nvidia,has-legacy-mode;
	463	clocks = <&tegra_car 22>, <&tegra_car 127>;
	464	clock-names = "phy", "pll_u";
	465	};
	466
c27317c0 OJ	467	usb@c5004000 {
	468	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	469	reg = <0xc5004000 0x4000>;
95decf84	470	interrupts = <0 21 0x04>;
c27317c0	471	phy_type = "ulpi";
8d8b43da	472	clocks = <&tegra_car 58>;
e374b65c	473	nvidia,phy = <&phy2>;
223ef78d	474	status = "disabled";
c27317c0 OJ	475	};
c27317c0 OJ	476
5d324410 SW	477	phy2: usb-phy@c5004400 {
	478	compatible = "nvidia,tegra20-usb-phy";
	479	reg = <0xc5004400 0x3c00>;
	480	phy_type = "ulpi";
1071b2df	481	clocks = <&tegra_car 93>, <&tegra_car 127>;
5d324410 SW	482	clock-names = "phy", "pll_u";
	483	};
	484
c27317c0 OJ	485	usb@c5008000 {
	486	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	487	reg = <0xc5008000 0x4000>;
95decf84	488	interrupts = <0 97 0x04>;
c27317c0	489	phy_type = "utmi";
8d8b43da	490	clocks = <&tegra_car 59>;
e374b65c	491	nvidia,phy = <&phy3>;
223ef78d	492	status = "disabled";
c27317c0	493	};
7868a9bc	494
5d324410 SW	495	phy3: usb-phy@c5008400 {
	496	compatible = "nvidia,tegra20-usb-phy";
	497	reg = <0xc5008400 0x3c00>;
	498	phy_type = "utmi";
	499	clocks = <&tegra_car 22>, <&tegra_car 127>;
	500	clock-names = "phy", "pll_u";
	501	};
	502
c04abb3a SW	503	sdhci@c8000000 {
	504	compatible = "nvidia,tegra20-sdhci";
	505	reg = <0xc8000000 0x200>;
	506	interrupts = <0 14 0x04>;
8d8b43da	507	clocks = <&tegra_car 14>;
223ef78d	508	status = "disabled";
7868a9bc	509	};
4a82f2b3	510
c04abb3a SW	511	sdhci@c8000200 {
	512	compatible = "nvidia,tegra20-sdhci";
	513	reg = <0xc8000200 0x200>;
	514	interrupts = <0 15 0x04>;
8d8b43da	515	clocks = <&tegra_car 9>;
223ef78d	516	status = "disabled";
4a82f2b3	517	};
6a943e0e	518
c04abb3a SW	519	sdhci@c8000400 {
	520	compatible = "nvidia,tegra20-sdhci";
	521	reg = <0xc8000400 0x200>;
	522	interrupts = <0 19 0x04>;
8d8b43da	523	clocks = <&tegra_car 69>;
223ef78d	524	status = "disabled";
c04abb3a SW	525	};
	526
	527	sdhci@c8000600 {
	528	compatible = "nvidia,tegra20-sdhci";
	529	reg = <0xc8000600 0x200>;
	530	interrupts = <0 31 0x04>;
8d8b43da	531	clocks = <&tegra_car 15>;
223ef78d	532	status = "disabled";
c04abb3a SW	533	};
c04abb3a SW	534
4dd2bd37 HD	535	cpus {
	536	#address-cells = <1>;
	537	#size-cells = <0>;
	538
	539	cpu@0 {
	540	device_type = "cpu";
	541	compatible = "arm,cortex-a9";
	542	reg = <0>;
	543	};
	544
	545	cpu@1 {
	546	device_type = "cpu";
	547	compatible = "arm,cortex-a9";
	548	reg = <1>;
	549	};
	550	};
	551
c04abb3a SW	552	pmu {
	553	compatible = "arm,cortex-a9-pmu";
	554	interrupts = <0 56 0x04
	555	0 57 0x04>;
6a943e0e	556	};
8e267f3d	557	};