[deliverable/linux.git] / arch / arm / boot / dts / tegra20.dtsi

#include <dt-bindings/clock/tegra20-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra20";
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &uarta;
		serial1 = &uartb;
		serial2 = &uartc;
		serial3 = &uartd;
		serial4 = &uarte;
	};

	host1x {
		compatible = "nvidia,tegra20-host1x", "simple-bus";
		reg = <0x50000000 0x00024000>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
		clocks = <&tegra_car TEGRA20_CLK_HOST1X>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe {
			compatible = "nvidia,tegra20-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA20_CLK_MPE>;
		};

		vi {
			compatible = "nvidia,tegra20-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA20_CLK_VI>;
		};

		epp {
			compatible = "nvidia,tegra20-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA20_CLK_EPP>;
		};

		isp {
			compatible = "nvidia,tegra20-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA20_CLK_ISP>;
		};

		gr2d {
			compatible = "nvidia,tegra20-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA20_CLK_GR2D>;
		};

		gr3d {
			compatible = "nvidia,tegra20-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car TEGRA20_CLK_GR3D>;
		};

		dc@54200000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA20_CLK_DISP1>,
				 <&tegra_car TEGRA20_CLK_PLL_P>;
			clock-names = "disp1", "parent";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA20_CLK_DISP2>,
				 <&tegra_car TEGRA20_CLK_PLL_P>;
			clock-names = "disp2", "parent";

			rgb {
				status = "disabled";
			};
		};

		hdmi {
			compatible = "nvidia,tegra20-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA20_CLK_HDMI>,
				 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
			clock-names = "hdmi", "parent";
			status = "disabled";
		};

		tvo {
			compatible = "nvidia,tegra20-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA20_CLK_TVO>;
			status = "disabled";
		};

		dsi {
			compatible = "nvidia,tegra20-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car TEGRA20_CLK_DSI>;
			status = "disabled";
		};
	};

	timer@50004600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x50040600 0x20>;
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
		clocks = <&tegra_car TEGRA20_CLK_TWD>;
	};

	intc: interrupt-controller {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0x50043000 0x1000>;
		arm,data-latency = <5 5 2>;
		arm,tag-latency = <4 4 2>;
		cache-unified;
		cache-level = <2>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra20-timer";
		reg = <0x60005000 0x60>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA20_CLK_TIMER>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra20-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1200>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
	};

	ahb {
		compatible = "nvidia,tegra20-ahb";
		reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio {
		compatible = "nvidia,tegra20-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra20-pinmux";
		reg = <0x70000014 0x10   /* Tri-state registers */
		       0x70000080 0x20   /* Mux registers */
		       0x700000a0 0x14   /* Pull-up/down registers */
		       0x70000868 0xa8>; /* Pad control registers */
	};

	das {
		compatible = "nvidia,tegra20-das";
		reg = <0x70000c00 0x80>;
	};

	tegra_ac97: ac97 {
		compatible = "nvidia,tegra20-ac97";
		reg = <0x70002000 0x200>;
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 12>;
		clocks = <&tegra_car TEGRA20_CLK_AC97>;
		status = "disabled";
	};

	tegra_i2s1: i2s@70002800 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002800 0x200>;
		interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 2>;
		clocks = <&tegra_car TEGRA20_CLK_I2S1>;
		status = "disabled";
	};

	tegra_i2s2: i2s@70002a00 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002a00 0x200>;
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 1>;
		clocks = <&tegra_car TEGRA20_CLK_I2S2>;
		status = "disabled";
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
	 * driver, the comptible is "nvidia,tegra20-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 8>;
		clocks = <&tegra_car TEGRA20_CLK_UARTA>;
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 9>;
		clocks = <&tegra_car TEGRA20_CLK_UARTB>;
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 10>;
		clocks = <&tegra_car TEGRA20_CLK_UARTC>;
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 19>;
		clocks = <&tegra_car TEGRA20_CLK_UARTD>;
		status = "disabled";
	};

	uarte: serial@70006400 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 20>;
		clocks = <&tegra_car TEGRA20_CLK_UARTE>;
		status = "disabled";
	};

	pwm: pwm {
		compatible = "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car TEGRA20_CLK_PWM>;
		status = "disabled";
	};

	rtc {
		compatible = "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA20_CLK_RTC>;
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA20_CLK_I2C1>,
			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000c380 {
		compatible = "nvidia,tegra20-sflash";
		reg = <0x7000c380 0x80>;
		interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 11>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA20_CLK_SPI>;
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA20_CLK_I2C2>,
			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra20-i2c-dvc";
		reg = <0x7000d000 0x200>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA20_CLK_DVC>,
			 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d400 0x200>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA20_CLK_SBC1>;
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d600 0x200>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA20_CLK_SBC2>;
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d800 0x200>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA20_CLK_SBC3>;
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000da00 0x200>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA20_CLK_SBC4>;
		status = "disabled";
	};

	kbc {
		compatible = "nvidia,tegra20-kbc";
		reg = <0x7000e200 0x100>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA20_CLK_KBC>;
		status = "disabled";
	};

	pmc {
		compatible = "nvidia,tegra20-pmc";
		reg = <0x7000e400 0x400>;
		clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
	};

	memory-controller@7000f000 {
		compatible = "nvidia,tegra20-mc";
		reg = <0x7000f000 0x024
		       0x7000f03c 0x3c4>;
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu {
		compatible = "nvidia,tegra20-gart";
		reg = <0x7000f024 0x00000018	/* controller registers */
		       0x58000000 0x02000000>;	/* GART aperture */
	};

	memory-controller@7000f400 {
		compatible = "nvidia,tegra20-emc";
		reg = <0x7000f400 0x200>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	usb@c5000000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5000000 0x4000>;
		interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
		clocks = <&tegra_car TEGRA20_CLK_USBD>;
		nvidia,needs-double-reset;
		nvidia,phy = <&phy1>;
		status = "disabled";
	};

	phy1: usb-phy@c5000000 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA20_CLK_USBD>,
			 <&tegra_car TEGRA20_CLK_PLL_U>,
			 <&tegra_car TEGRA20_CLK_CLK_M>,
			 <&tegra_car TEGRA20_CLK_USBD>;
		clock-names = "reg", "pll_u", "timer", "utmi-pads";
		nvidia,has-legacy-mode;
		hssync_start_delay = <9>;
		idle_wait_delay = <17>;
		elastic_limit = <16>;
		term_range_adj = <6>;
		xcvr_setup = <9>;
		xcvr_lsfslew = <1>;
		xcvr_lsrslew = <1>;
		status = "disabled";
	};

	usb@c5004000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5004000 0x4000>;
		interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "ulpi";
		clocks = <&tegra_car TEGRA20_CLK_USB2>;
		nvidia,phy = <&phy2>;
		status = "disabled";
	};

	phy2: usb-phy@c5004000 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5004000 0x4000>;
		phy_type = "ulpi";
		clocks = <&tegra_car TEGRA20_CLK_USB2>,
			 <&tegra_car TEGRA20_CLK_PLL_U>,
			 <&tegra_car TEGRA20_CLK_CDEV2>;
		clock-names = "reg", "pll_u", "ulpi-link";
		status = "disabled";
	};

	usb@c5008000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5008000 0x4000>;
		interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA20_CLK_USB3>;
		nvidia,phy = <&phy3>;
		status = "disabled";
	};

	phy3: usb-phy@c5008000 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
		phy_type = "utmi";
		clocks = <&tegra_car TEGRA20_CLK_USB3>,
			 <&tegra_car TEGRA20_CLK_PLL_U>,
			 <&tegra_car TEGRA20_CLK_CLK_M>,
			 <&tegra_car TEGRA20_CLK_USBD>;
		clock-names = "reg", "pll_u", "timer", "utmi-pads";
		hssync_start_delay = <9>;
		idle_wait_delay = <17>;
		elastic_limit = <16>;
		term_range_adj = <6>;
		xcvr_setup = <9>;
		xcvr_lsfslew = <2>;
		xcvr_lsrslew = <2>;
		status = "disabled";
	};

	sdhci@c8000000 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000000 0x200>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
		status = "disabled";
	};

	sdhci@c8000200 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000200 0x200>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
		status = "disabled";
	};

	sdhci@c8000400 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000400 0x200>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
		status = "disabled";
	};

	sdhci@c8000600 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000600 0x200>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
	};
};
Commit	Line	Data
885a8cfa	1	#include <dt-bindings/clock/tegra20-car.h>
3325f1bc	2	#include <dt-bindings/gpio/tegra-gpio.h>
6cecf916	3	#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc	4
1bd0bd49	5	#include "skeleton.dtsi"
8e267f3d GL	6
	7	/ {
	8	compatible = "nvidia,tegra20";
	9	interrupt-parent = <&intc>;
	10
b6551bb9 LD	11	aliases {
	12	serial0 = &uarta;
	13	serial1 = &uartb;
	14	serial2 = &uartc;
	15	serial3 = &uartd;
	16	serial4 = &uarte;
	17	};
	18
ed821f07 TR	19	host1x {
	20	compatible = "nvidia,tegra20-host1x", "simple-bus";
	21	reg = <0x50000000 0x00024000>;
6cecf916 SW	22	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
6cecf916 SW	23	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
885a8cfa	24	clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
ed821f07 TR	25
	26	#address-cells = <1>;
	27	#size-cells = <1>;
	28
	29	ranges = <0x54000000 0x54000000 0x04000000>;
	30
	31	mpe {
	32	compatible = "nvidia,tegra20-mpe";
	33	reg = <0x54040000 0x00040000>;
6cecf916	34	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	35	clocks = <&tegra_car TEGRA20_CLK_MPE>;
ed821f07 TR	36	};
	37
	38	vi {
	39	compatible = "nvidia,tegra20-vi";
	40	reg = <0x54080000 0x00040000>;
6cecf916	41	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	42	clocks = <&tegra_car TEGRA20_CLK_VI>;
ed821f07 TR	43	};
	44
	45	epp {
	46	compatible = "nvidia,tegra20-epp";
	47	reg = <0x540c0000 0x00040000>;
6cecf916	48	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	49	clocks = <&tegra_car TEGRA20_CLK_EPP>;
ed821f07 TR	50	};
	51
	52	isp {
	53	compatible = "nvidia,tegra20-isp";
	54	reg = <0x54100000 0x00040000>;
6cecf916	55	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	56	clocks = <&tegra_car TEGRA20_CLK_ISP>;
ed821f07 TR	57	};
	58
	59	gr2d {
	60	compatible = "nvidia,tegra20-gr2d";
	61	reg = <0x54140000 0x00040000>;
6cecf916	62	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	63	clocks = <&tegra_car TEGRA20_CLK_GR2D>;
ed821f07 TR	64	};
	65
	66	gr3d {
	67	compatible = "nvidia,tegra20-gr3d";
	68	reg = <0x54180000 0x00040000>;
885a8cfa	69	clocks = <&tegra_car TEGRA20_CLK_GR3D>;
ed821f07 TR	70	};
	71
	72	dc@54200000 {
	73	compatible = "nvidia,tegra20-dc";
	74	reg = <0x54200000 0x00040000>;
6cecf916	75	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa HD	76	clocks = <&tegra_car TEGRA20_CLK_DISP1>,
885a8cfa HD	77	<&tegra_car TEGRA20_CLK_PLL_P>;
8d8b43da	78	clock-names = "disp1", "parent";
ed821f07 TR	79
	80	rgb {
	81	status = "disabled";
	82	};
	83	};
	84
	85	dc@54240000 {
	86	compatible = "nvidia,tegra20-dc";
	87	reg = <0x54240000 0x00040000>;
6cecf916	88	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa HD	89	clocks = <&tegra_car TEGRA20_CLK_DISP2>,
885a8cfa HD	90	<&tegra_car TEGRA20_CLK_PLL_P>;
8d8b43da	91	clock-names = "disp2", "parent";
ed821f07 TR	92
	93	rgb {
	94	status = "disabled";
	95	};
	96	};
	97
	98	hdmi {
	99	compatible = "nvidia,tegra20-hdmi";
	100	reg = <0x54280000 0x00040000>;
6cecf916	101	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa HD	102	clocks = <&tegra_car TEGRA20_CLK_HDMI>,
885a8cfa HD	103	<&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
8d8b43da	104	clock-names = "hdmi", "parent";
ed821f07 TR	105	status = "disabled";
	106	};
	107
	108	tvo {
	109	compatible = "nvidia,tegra20-tvo";
	110	reg = <0x542c0000 0x00040000>;
6cecf916	111	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	112	clocks = <&tegra_car TEGRA20_CLK_TVO>;
ed821f07 TR	113	status = "disabled";
	114	};
	115
	116	dsi {
	117	compatible = "nvidia,tegra20-dsi";
	118	reg = <0x54300000 0x00040000>;
885a8cfa	119	clocks = <&tegra_car TEGRA20_CLK_DSI>;
ed821f07 TR	120	status = "disabled";
	121	};
	122	};
	123
73368ba0 SW	124	timer@50004600 {
	125	compatible = "arm,cortex-a9-twd-timer";
	126	reg = <0x50040600 0x20>;
6cecf916 SW	127	interrupts = <GIC_PPI 13
6cecf916 SW	128	(GIC_CPU_MASK_SIMPLE(2) \| IRQ_TYPE_LEVEL_HIGH)>;
885a8cfa	129	clocks = <&tegra_car TEGRA20_CLK_TWD>;
73368ba0 SW	130	};
73368ba0 SW	131
f9eb26a4	132	intc: interrupt-controller {
0d4f7479	133	compatible = "arm,cortex-a9-gic";
5ff48887 SW	134	reg = <0x50041000 0x1000
5ff48887 SW	135	0x50040100 0x0100>;
2eaab06e SW	136	interrupt-controller;
2eaab06e SW	137	#interrupt-cells = <3>;
8e267f3d GL	138	};
8e267f3d GL	139
bb2c1de9 SW	140	cache-controller {
	141	compatible = "arm,pl310-cache";
	142	reg = <0x50043000 0x1000>;
	143	arm,data-latency = <5 5 2>;
	144	arm,tag-latency = <4 4 2>;
	145	cache-unified;
	146	cache-level = <2>;
	147	};
	148
2f2b7fb2 SW	149	timer@60005000 {
	150	compatible = "nvidia,tegra20-timer";
	151	reg = <0x60005000 0x60>;
6cecf916 SW	152	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	153	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	154	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	155	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	156	clocks = <&tegra_car TEGRA20_CLK_TIMER>;
2f2b7fb2 SW	157	};
2f2b7fb2 SW	158
270f8ce3 SW	159	tegra_car: clock {
	160	compatible = "nvidia,tegra20-car";
	161	reg = <0x60006000 0x1000>;
	162	#clock-cells = <1>;
	163	};
	164
f9eb26a4	165	apbdma: dma {
8051b75a SW	166	compatible = "nvidia,tegra20-apbdma";
8051b75a SW	167	reg = <0x6000a000 0x1200>;
6cecf916 SW	168	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	169	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	170	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	171	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	172	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	173	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	174	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	175	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	176	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	177	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	178	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	179	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	180	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	181	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	182	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	183	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	184	clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
8051b75a SW	185	};
8051b75a SW	186
c04abb3a SW	187	ahb {
	188	compatible = "nvidia,tegra20-ahb";
	189	reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
8e267f3d GL	190	};
8e267f3d GL	191
f9eb26a4	192	gpio: gpio {
8e267f3d	193	compatible = "nvidia,tegra20-gpio";
95decf84	194	reg = <0x6000d000 0x1000>;
6cecf916 SW	195	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	196	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	197	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	198	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	199	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	200	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	201	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
8e267f3d GL	202	#gpio-cells = <2>;
8e267f3d GL	203	gpio-controller;
6f74dc9b SW	204	#interrupt-cells = <2>;
6f74dc9b SW	205	interrupt-controller;
8e267f3d GL	206	};
8e267f3d GL	207
f9eb26a4	208	pinmux: pinmux {
f62f548c	209	compatible = "nvidia,tegra20-pinmux";
95decf84 SW	210	reg = <0x70000014 0x10 /* Tri-state registers */
	211	0x70000080 0x20 /* Mux registers */
	212	0x700000a0 0x14 /* Pull-up/down registers */
	213	0x70000868 0xa8>; /* Pad control registers */
f62f548c SW	214	};
f62f548c SW	215
c04abb3a SW	216	das {
	217	compatible = "nvidia,tegra20-das";
	218	reg = <0x70000c00 0x80>;
	219	};
fc5c306b	220
0698ed19 LS	221	tegra_ac97: ac97 {
	222	compatible = "nvidia,tegra20-ac97";
	223	reg = <0x70002000 0x200>;
6cecf916	224	interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
0698ed19	225	nvidia,dma-request-selector = <&apbdma 12>;
885a8cfa	226	clocks = <&tegra_car TEGRA20_CLK_AC97>;
0698ed19 LS	227	status = "disabled";
0698ed19 LS	228	};
c04abb3a SW	229
	230	tegra_i2s1: i2s@70002800 {
	231	compatible = "nvidia,tegra20-i2s";
	232	reg = <0x70002800 0x200>;
6cecf916	233	interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a	234	nvidia,dma-request-selector = <&apbdma 2>;
885a8cfa	235	clocks = <&tegra_car TEGRA20_CLK_I2S1>;
223ef78d	236	status = "disabled";
c04abb3a SW	237	};
	238
	239	tegra_i2s2: i2s@70002a00 {
	240	compatible = "nvidia,tegra20-i2s";
	241	reg = <0x70002a00 0x200>;
6cecf916	242	interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a	243	nvidia,dma-request-selector = <&apbdma 1>;
885a8cfa	244	clocks = <&tegra_car TEGRA20_CLK_I2S2>;
223ef78d	245	status = "disabled";
c04abb3a SW	246	};
c04abb3a SW	247
b6551bb9 LD	248	/*
	249	* There are two serial driver i.e. 8250 based simple serial
	250	* driver and APB DMA based serial driver for higher baudrate
	251	* and performace. To enable the 8250 based driver, the compatible
	252	* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
	253	* driver, the comptible is "nvidia,tegra20-hsuart".
	254	*/
	255	uarta: serial@70006000 {
8e267f3d GL	256	compatible = "nvidia,tegra20-uart";
	257	reg = <0x70006000 0x40>;
	258	reg-shift = <2>;
6cecf916	259	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	260	nvidia,dma-request-selector = <&apbdma 8>;
885a8cfa	261	clocks = <&tegra_car TEGRA20_CLK_UARTA>;
223ef78d	262	status = "disabled";
8e267f3d GL	263	};
8e267f3d GL	264
b6551bb9	265	uartb: serial@70006040 {
8e267f3d GL	266	compatible = "nvidia,tegra20-uart";
	267	reg = <0x70006040 0x40>;
	268	reg-shift = <2>;
6cecf916	269	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	270	nvidia,dma-request-selector = <&apbdma 9>;
885a8cfa	271	clocks = <&tegra_car TEGRA20_CLK_UARTB>;
223ef78d	272	status = "disabled";
8e267f3d GL	273	};
8e267f3d GL	274
b6551bb9	275	uartc: serial@70006200 {
8e267f3d GL	276	compatible = "nvidia,tegra20-uart";
	277	reg = <0x70006200 0x100>;
	278	reg-shift = <2>;
6cecf916	279	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	280	nvidia,dma-request-selector = <&apbdma 10>;
885a8cfa	281	clocks = <&tegra_car TEGRA20_CLK_UARTC>;
223ef78d	282	status = "disabled";
8e267f3d GL	283	};
8e267f3d GL	284
b6551bb9	285	uartd: serial@70006300 {
8e267f3d GL	286	compatible = "nvidia,tegra20-uart";
	287	reg = <0x70006300 0x100>;
	288	reg-shift = <2>;
6cecf916	289	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	290	nvidia,dma-request-selector = <&apbdma 19>;
885a8cfa	291	clocks = <&tegra_car TEGRA20_CLK_UARTD>;
223ef78d	292	status = "disabled";
8e267f3d GL	293	};
8e267f3d GL	294
b6551bb9	295	uarte: serial@70006400 {
8e267f3d GL	296	compatible = "nvidia,tegra20-uart";
	297	reg = <0x70006400 0x100>;
	298	reg-shift = <2>;
6cecf916	299	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	300	nvidia,dma-request-selector = <&apbdma 20>;
885a8cfa	301	clocks = <&tegra_car TEGRA20_CLK_UARTE>;
223ef78d	302	status = "disabled";
8e267f3d GL	303	};
8e267f3d GL	304
2b8b15da	305	pwm: pwm {
140fd977 TR	306	compatible = "nvidia,tegra20-pwm";
	307	reg = <0x7000a000 0x100>;
	308	#pwm-cells = <2>;
885a8cfa	309	clocks = <&tegra_car TEGRA20_CLK_PWM>;
b69cd984	310	status = "disabled";
140fd977 TR	311	};
140fd977 TR	312
380e04ac SW	313	rtc {
	314	compatible = "nvidia,tegra20-rtc";
	315	reg = <0x7000e000 0x100>;
6cecf916	316	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	317	clocks = <&tegra_car TEGRA20_CLK_RTC>;
380e04ac SW	318	};
380e04ac SW	319
c04abb3a	320	i2c@7000c000 {
c04abb3a SW	321	compatible = "nvidia,tegra20-i2c";
c04abb3a SW	322	reg = <0x7000c000 0x100>;
6cecf916	323	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	324	#address-cells = <1>;
2eaab06e SW	325	#size-cells = <0>;
885a8cfa HD	326	clocks = <&tegra_car TEGRA20_CLK_I2C1>,
885a8cfa HD	327	<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da	328	clock-names = "div-clk", "fast-clk";
223ef78d	329	status = "disabled";
0c6700ab OJ	330	};
0c6700ab OJ	331
fa98a114 LD	332	spi@7000c380 {
	333	compatible = "nvidia,tegra20-sflash";
	334	reg = <0x7000c380 0x80>;
6cecf916	335	interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
fa98a114 LD	336	nvidia,dma-request-selector = <&apbdma 11>;
	337	#address-cells = <1>;
	338	#size-cells = <0>;
885a8cfa	339	clocks = <&tegra_car TEGRA20_CLK_SPI>;
fa98a114 LD	340	status = "disabled";
	341	};
	342
c04abb3a	343	i2c@7000c400 {
c04abb3a SW	344	compatible = "nvidia,tegra20-i2c";
c04abb3a SW	345	reg = <0x7000c400 0x100>;
6cecf916	346	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	347	#address-cells = <1>;
2eaab06e SW	348	#size-cells = <0>;
885a8cfa HD	349	clocks = <&tegra_car TEGRA20_CLK_I2C2>,
885a8cfa HD	350	<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da	351	clock-names = "div-clk", "fast-clk";
223ef78d	352	status = "disabled";
8e267f3d GL	353	};
8e267f3d GL	354
c04abb3a	355	i2c@7000c500 {
c04abb3a SW	356	compatible = "nvidia,tegra20-i2c";
c04abb3a SW	357	reg = <0x7000c500 0x100>;
6cecf916	358	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	359	#address-cells = <1>;
2eaab06e SW	360	#size-cells = <0>;
885a8cfa HD	361	clocks = <&tegra_car TEGRA20_CLK_I2C3>,
885a8cfa HD	362	<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da	363	clock-names = "div-clk", "fast-clk";
223ef78d	364	status = "disabled";
8e267f3d GL	365	};
8e267f3d GL	366
c04abb3a	367	i2c@7000d000 {
c04abb3a SW	368	compatible = "nvidia,tegra20-i2c-dvc";
c04abb3a SW	369	reg = <0x7000d000 0x200>;
6cecf916	370	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	371	#address-cells = <1>;
2eaab06e SW	372	#size-cells = <0>;
885a8cfa HD	373	clocks = <&tegra_car TEGRA20_CLK_DVC>,
885a8cfa HD	374	<&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da	375	clock-names = "div-clk", "fast-clk";
223ef78d	376	status = "disabled";
8e267f3d GL	377	};
8e267f3d GL	378
a86b0db3 LD	379	spi@7000d400 {
	380	compatible = "nvidia,tegra20-slink";
	381	reg = <0x7000d400 0x200>;
6cecf916	382	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	383	nvidia,dma-request-selector = <&apbdma 15>;
	384	#address-cells = <1>;
	385	#size-cells = <0>;
885a8cfa	386	clocks = <&tegra_car TEGRA20_CLK_SBC1>;
a86b0db3 LD	387	status = "disabled";
	388	};
	389
	390	spi@7000d600 {
	391	compatible = "nvidia,tegra20-slink";
	392	reg = <0x7000d600 0x200>;
6cecf916	393	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	394	nvidia,dma-request-selector = <&apbdma 16>;
	395	#address-cells = <1>;
	396	#size-cells = <0>;
885a8cfa	397	clocks = <&tegra_car TEGRA20_CLK_SBC2>;
a86b0db3 LD	398	status = "disabled";
	399	};
	400
	401	spi@7000d800 {
	402	compatible = "nvidia,tegra20-slink";
57471c8d	403	reg = <0x7000d800 0x200>;
6cecf916	404	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	405	nvidia,dma-request-selector = <&apbdma 17>;
	406	#address-cells = <1>;
	407	#size-cells = <0>;
885a8cfa	408	clocks = <&tegra_car TEGRA20_CLK_SBC3>;
a86b0db3 LD	409	status = "disabled";
	410	};
	411
	412	spi@7000da00 {
	413	compatible = "nvidia,tegra20-slink";
	414	reg = <0x7000da00 0x200>;
6cecf916	415	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	416	nvidia,dma-request-selector = <&apbdma 18>;
	417	#address-cells = <1>;
	418	#size-cells = <0>;
885a8cfa	419	clocks = <&tegra_car TEGRA20_CLK_SBC4>;
a86b0db3 LD	420	status = "disabled";
	421	};
	422
699ed4b9 LD	423	kbc {
	424	compatible = "nvidia,tegra20-kbc";
	425	reg = <0x7000e200 0x100>;
6cecf916	426	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	427	clocks = <&tegra_car TEGRA20_CLK_KBC>;
699ed4b9 LD	428	status = "disabled";
	429	};
	430
c04abb3a SW	431	pmc {
	432	compatible = "nvidia,tegra20-pmc";
	433	reg = <0x7000e400 0x400>;
885a8cfa	434	clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
7021d122	435	clock-names = "pclk", "clk32k_in";
c04abb3a SW	436	};
c04abb3a SW	437
bbfc33bd	438	memory-controller@7000f000 {
c04abb3a SW	439	compatible = "nvidia,tegra20-mc";
	440	reg = <0x7000f000 0x024
	441	0x7000f03c 0x3c4>;
6cecf916	442	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a SW	443	};
c04abb3a SW	444
109269e8	445	iommu {
c04abb3a SW	446	compatible = "nvidia,tegra20-gart";
	447	reg = <0x7000f024 0x00000018 /* controller registers */
	448	0x58000000 0x02000000>; /* GART aperture */
	449	};
	450
bbfc33bd	451	memory-controller@7000f400 {
c04abb3a SW	452	compatible = "nvidia,tegra20-emc";
c04abb3a SW	453	reg = <0x7000f400 0x200>;
2eaab06e SW	454	#address-cells = <1>;
2eaab06e SW	455	#size-cells = <0>;
8e267f3d	456	};
c27317c0 OJ	457
	458	usb@c5000000 {
	459	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	460	reg = <0xc5000000 0x4000>;
6cecf916	461	interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
c27317c0	462	phy_type = "utmi";
ba202f15	463	nvidia,has-legacy-mode;
885a8cfa	464	clocks = <&tegra_car TEGRA20_CLK_USBD>;
b4e07478	465	nvidia,needs-double-reset;
e374b65c	466	nvidia,phy = <&phy1>;
223ef78d	467	status = "disabled";
c27317c0 OJ	468	};
c27317c0 OJ	469
4c94c8b5	470	phy1: usb-phy@c5000000 {
5d324410	471	compatible = "nvidia,tegra20-usb-phy";
4c94c8b5	472	reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
5d324410	473	phy_type = "utmi";
885a8cfa HD	474	clocks = <&tegra_car TEGRA20_CLK_USBD>,
	475	<&tegra_car TEGRA20_CLK_PLL_U>,
	476	<&tegra_car TEGRA20_CLK_CLK_M>,
	477	<&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5	478	clock-names = "reg", "pll_u", "timer", "utmi-pads";
5d324410	479	nvidia,has-legacy-mode;
4c94c8b5 VB	480	hssync_start_delay = <9>;
	481	idle_wait_delay = <17>;
	482	elastic_limit = <16>;
	483	term_range_adj = <6>;
	484	xcvr_setup = <9>;
	485	xcvr_lsfslew = <1>;
	486	xcvr_lsrslew = <1>;
	487	status = "disabled";
5d324410 SW	488	};
5d324410 SW	489
c27317c0 OJ	490	usb@c5004000 {
	491	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	492	reg = <0xc5004000 0x4000>;
6cecf916	493	interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
c27317c0	494	phy_type = "ulpi";
885a8cfa	495	clocks = <&tegra_car TEGRA20_CLK_USB2>;
e374b65c	496	nvidia,phy = <&phy2>;
223ef78d	497	status = "disabled";
c27317c0 OJ	498	};
c27317c0 OJ	499
4c94c8b5	500	phy2: usb-phy@c5004000 {
5d324410	501	compatible = "nvidia,tegra20-usb-phy";
4c94c8b5	502	reg = <0xc5004000 0x4000>;
5d324410	503	phy_type = "ulpi";
885a8cfa HD	504	clocks = <&tegra_car TEGRA20_CLK_USB2>,
	505	<&tegra_car TEGRA20_CLK_PLL_U>,
	506	<&tegra_car TEGRA20_CLK_CDEV2>;
4c94c8b5 VB	507	clock-names = "reg", "pll_u", "ulpi-link";
4c94c8b5 VB	508	status = "disabled";
5d324410 SW	509	};
5d324410 SW	510
c27317c0 OJ	511	usb@c5008000 {
	512	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	513	reg = <0xc5008000 0x4000>;
6cecf916	514	interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
c27317c0	515	phy_type = "utmi";
885a8cfa	516	clocks = <&tegra_car TEGRA20_CLK_USB3>;
e374b65c	517	nvidia,phy = <&phy3>;
223ef78d	518	status = "disabled";
c27317c0	519	};
7868a9bc	520
4c94c8b5	521	phy3: usb-phy@c5008000 {
5d324410	522	compatible = "nvidia,tegra20-usb-phy";
4c94c8b5	523	reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
5d324410	524	phy_type = "utmi";
885a8cfa HD	525	clocks = <&tegra_car TEGRA20_CLK_USB3>,
	526	<&tegra_car TEGRA20_CLK_PLL_U>,
	527	<&tegra_car TEGRA20_CLK_CLK_M>,
	528	<&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 VB	529	clock-names = "reg", "pll_u", "timer", "utmi-pads";
	530	hssync_start_delay = <9>;
	531	idle_wait_delay = <17>;
	532	elastic_limit = <16>;
	533	term_range_adj = <6>;
	534	xcvr_setup = <9>;
	535	xcvr_lsfslew = <2>;
	536	xcvr_lsrslew = <2>;
	537	status = "disabled";
5d324410 SW	538	};
5d324410 SW	539
c04abb3a SW	540	sdhci@c8000000 {
	541	compatible = "nvidia,tegra20-sdhci";
	542	reg = <0xc8000000 0x200>;
6cecf916	543	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	544	clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
223ef78d	545	status = "disabled";
7868a9bc	546	};
4a82f2b3	547
c04abb3a SW	548	sdhci@c8000200 {
	549	compatible = "nvidia,tegra20-sdhci";
	550	reg = <0xc8000200 0x200>;
6cecf916	551	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	552	clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
223ef78d	553	status = "disabled";
4a82f2b3	554	};
6a943e0e	555
c04abb3a SW	556	sdhci@c8000400 {
	557	compatible = "nvidia,tegra20-sdhci";
	558	reg = <0xc8000400 0x200>;
6cecf916	559	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	560	clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
223ef78d	561	status = "disabled";
c04abb3a SW	562	};
	563
	564	sdhci@c8000600 {
	565	compatible = "nvidia,tegra20-sdhci";
	566	reg = <0xc8000600 0x200>;
6cecf916	567	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa	568	clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
223ef78d	569	status = "disabled";
c04abb3a SW	570	};
c04abb3a SW	571
4dd2bd37 HD	572	cpus {
	573	#address-cells = <1>;
	574	#size-cells = <0>;
	575
	576	cpu@0 {
	577	device_type = "cpu";
	578	compatible = "arm,cortex-a9";
	579	reg = <0>;
	580	};
	581
	582	cpu@1 {
	583	device_type = "cpu";
	584	compatible = "arm,cortex-a9";
	585	reg = <1>;
	586	};
	587	};
	588
c04abb3a SW	589	pmu {
c04abb3a SW	590	compatible = "arm,cortex-a9-pmu";
6cecf916 SW	591	interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
6cecf916 SW	592	<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6a943e0e	593	};
8e267f3d	594	};