[deliverable/linux.git] / arch / arm / boot / dts / tegra20.dtsi

/include/ "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra20";
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &uarta;
		serial1 = &uartb;
		serial2 = &uartc;
		serial3 = &uartd;
		serial4 = &uarte;
	};

	host1x {
		compatible = "nvidia,tegra20-host1x", "simple-bus";
		reg = <0x50000000 0x00024000>;
		interrupts = <0 65 0x04   /* mpcore syncpt */
			      0 67 0x04>; /* mpcore general */
		clocks = <&tegra_car 28>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe {
			compatible = "nvidia,tegra20-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <0 68 0x04>;
			clocks = <&tegra_car 60>;
		};

		vi {
			compatible = "nvidia,tegra20-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <0 69 0x04>;
			clocks = <&tegra_car 100>;
		};

		epp {
			compatible = "nvidia,tegra20-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <0 70 0x04>;
			clocks = <&tegra_car 19>;
		};

		isp {
			compatible = "nvidia,tegra20-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <0 71 0x04>;
			clocks = <&tegra_car 23>;
		};

		gr2d {
			compatible = "nvidia,tegra20-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <0 72 0x04>;
			clocks = <&tegra_car 21>;
		};

		gr3d {
			compatible = "nvidia,tegra20-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car 24>;
		};

		dc@54200000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <0 73 0x04>;
			clocks = <&tegra_car 27>, <&tegra_car 121>;
			clock-names = "disp1", "parent";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra20-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <0 74 0x04>;
			clocks = <&tegra_car 26>, <&tegra_car 121>;
			clock-names = "disp2", "parent";

			rgb {
				status = "disabled";
			};
		};

		hdmi {
			compatible = "nvidia,tegra20-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <0 75 0x04>;
			clocks = <&tegra_car 51>, <&tegra_car 117>;
			clock-names = "hdmi", "parent";
			status = "disabled";
		};

		tvo {
			compatible = "nvidia,tegra20-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <0 76 0x04>;
			clocks = <&tegra_car 102>;
			status = "disabled";
		};

		dsi {
			compatible = "nvidia,tegra20-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car 48>;
			status = "disabled";
		};
	};

	timer@50004600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x50040600 0x20>;
		interrupts = <1 13 0x304>;
	};

	cache-controller@50043000 {
		compatible = "arm,pl310-cache";
		reg = <0x50043000 0x1000>;
		arm,data-latency = <5 5 2>;
		arm,tag-latency = <4 4 2>;
		cache-unified;
		cache-level = <2>;
	};

	intc: interrupt-controller {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra20-timer";
		reg = <0x60005000 0x60>;
		interrupts = <0 0 0x04
			      0 1 0x04
			      0 41 0x04
			      0 42 0x04>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra20-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1200>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04>;
		clocks = <&tegra_car 34>;
	};

	ahb {
		compatible = "nvidia,tegra20-ahb";
		reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio {
		compatible = "nvidia,tegra20-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <0 32 0x04
			      0 33 0x04
			      0 34 0x04
			      0 35 0x04
			      0 55 0x04
			      0 87 0x04
			      0 89 0x04>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra20-pinmux";
		reg = <0x70000014 0x10   /* Tri-state registers */
		       0x70000080 0x20   /* Mux registers */
		       0x700000a0 0x14   /* Pull-up/down registers */
		       0x70000868 0xa8>; /* Pad control registers */
	};

	das {
		compatible = "nvidia,tegra20-das";
		reg = <0x70000c00 0x80>;
	};
	
	tegra_ac97: ac97 {
		compatible = "nvidia,tegra20-ac97";
		reg = <0x70002000 0x200>;
		interrupts = <0 81 0x04>;
		nvidia,dma-request-selector = <&apbdma 12>;
		clocks = <&tegra_car 3>;
		status = "disabled";
	};

	tegra_i2s1: i2s@70002800 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002800 0x200>;
		interrupts = <0 13 0x04>;
		nvidia,dma-request-selector = <&apbdma 2>;
		clocks = <&tegra_car 11>;
		status = "disabled";
	};

	tegra_i2s2: i2s@70002a00 {
		compatible = "nvidia,tegra20-i2s";
		reg = <0x70002a00 0x200>;
		interrupts = <0 3 0x04>;
		nvidia,dma-request-selector = <&apbdma 1>;
		clocks = <&tegra_car 18>;
		status = "disabled";
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
	 * driver, the comptible is "nvidia,tegra20-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <0 36 0x04>;
		nvidia,dma-request-selector = <&apbdma 8>;
		clocks = <&tegra_car 6>;
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <0 37 0x04>;
		nvidia,dma-request-selector = <&apbdma 9>;
		clocks = <&tegra_car 96>;
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <0 46 0x04>;
		nvidia,dma-request-selector = <&apbdma 10>;
		clocks = <&tegra_car 55>;
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <0 90 0x04>;
		nvidia,dma-request-selector = <&apbdma 19>;
		clocks = <&tegra_car 65>;
		status = "disabled";
	};

	uarte: serial@70006400 {
		compatible = "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <0 91 0x04>;
		nvidia,dma-request-selector = <&apbdma 20>;
		clocks = <&tegra_car 66>;
		status = "disabled";
	};

	pwm: pwm {
		compatible = "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car 17>;
	};

	rtc {
		compatible = "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <0 2 0x04>;
	};

	i2c@7000c000 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <0 38 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000c380 {
		compatible = "nvidia,tegra20-sflash";
		reg = <0x7000c380 0x80>;
		interrupts = <0 39 0x04>;
		nvidia,dma-request-selector = <&apbdma 11>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 43>;
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <0 84 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <0 92 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra20-i2c-dvc";
		reg = <0x7000d000 0x200>;
		interrupts = <0 53 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>, <&tegra_car 124>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d400 0x200>;
		interrupts = <0 59 0x04>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 41>;
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d600 0x200>;
		interrupts = <0 82 0x04>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 44>;
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000d480 0x200>;
		interrupts = <0 83 0x04>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 46>;
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra20-slink";
		reg = <0x7000da00 0x200>;
		interrupts = <0 93 0x04>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 68>;
		status = "disabled";
	};

	pmc {
		compatible = "nvidia,tegra20-pmc";
		reg = <0x7000e400 0x400>;
	};

	memory-controller@7000f000 {
		compatible = "nvidia,tegra20-mc";
		reg = <0x7000f000 0x024
		       0x7000f03c 0x3c4>;
		interrupts = <0 77 0x04>;
	};

	gart {
		compatible = "nvidia,tegra20-gart";
		reg = <0x7000f024 0x00000018	/* controller registers */
		       0x58000000 0x02000000>;	/* GART aperture */
	};

	memory-controller@7000f400 {
		compatible = "nvidia,tegra20-emc";
		reg = <0x7000f400 0x200>;
		#address-cells = <1>;
		#size-cells = <0>;
	};

	phy1: usb-phy@c5000400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5000400 0x3c00>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
		clocks = <&tegra_car 22>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	phy2: usb-phy@c5004400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5004400 0x3c00>;
		phy_type = "ulpi";
		clocks = <&tegra_car 94>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	phy3: usb-phy@c5008400 {
		compatible = "nvidia,tegra20-usb-phy";
		reg = <0xc5008400 0x3C00>;
		phy_type = "utmi";
		clocks = <&tegra_car 22>, <&tegra_car 127>;
		clock-names = "phy", "pll_u";
	};

	usb@c5000000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5000000 0x4000>;
		interrupts = <0 20 0x04>;
		phy_type = "utmi";
		nvidia,has-legacy-mode;
		clocks = <&tegra_car 22>;
		nvidia,needs-double-reset;
		nvidia,phy = <&phy1>;
		status = "disabled";
	};

	usb@c5004000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5004000 0x4000>;
		interrupts = <0 21 0x04>;
		phy_type = "ulpi";
		clocks = <&tegra_car 58>;
		nvidia,phy = <&phy2>;
		status = "disabled";
	};

	usb@c5008000 {
		compatible = "nvidia,tegra20-ehci", "usb-ehci";
		reg = <0xc5008000 0x4000>;
		interrupts = <0 97 0x04>;
		phy_type = "utmi";
		clocks = <&tegra_car 59>;
		nvidia,phy = <&phy3>;
		status = "disabled";
	};

	sdhci@c8000000 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000000 0x200>;
		interrupts = <0 14 0x04>;
		clocks = <&tegra_car 14>;
		status = "disabled";
	};

	sdhci@c8000200 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000200 0x200>;
		interrupts = <0 15 0x04>;
		clocks = <&tegra_car 9>;
		status = "disabled";
	};

	sdhci@c8000400 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000400 0x200>;
		interrupts = <0 19 0x04>;
		clocks = <&tegra_car 69>;
		status = "disabled";
	};

	sdhci@c8000600 {
		compatible = "nvidia,tegra20-sdhci";
		reg = <0xc8000600 0x200>;
		interrupts = <0 31 0x04>;
		clocks = <&tegra_car 15>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 56 0x04
			      0 57 0x04>;
	};
};
Commit	Line	Data
8e267f3d GL	1	/include/ "skeleton.dtsi"
	2
	3	/ {
	4	compatible = "nvidia,tegra20";
	5	interrupt-parent = <&intc>;
	6
b6551bb9 LD	7	aliases {
	8	serial0 = &uarta;
	9	serial1 = &uartb;
	10	serial2 = &uartc;
	11	serial3 = &uartd;
	12	serial4 = &uarte;
	13	};
	14
ed821f07 TR	15	host1x {
	16	compatible = "nvidia,tegra20-host1x", "simple-bus";
	17	reg = <0x50000000 0x00024000>;
	18	interrupts = <0 65 0x04 /* mpcore syncpt */
	19	0 67 0x04>; /* mpcore general */
8d8b43da	20	clocks = <&tegra_car 28>;
ed821f07 TR	21
	22	#address-cells = <1>;
	23	#size-cells = <1>;
	24
	25	ranges = <0x54000000 0x54000000 0x04000000>;
	26
	27	mpe {
	28	compatible = "nvidia,tegra20-mpe";
	29	reg = <0x54040000 0x00040000>;
	30	interrupts = <0 68 0x04>;
8d8b43da	31	clocks = <&tegra_car 60>;
ed821f07 TR	32	};
	33
	34	vi {
	35	compatible = "nvidia,tegra20-vi";
	36	reg = <0x54080000 0x00040000>;
	37	interrupts = <0 69 0x04>;
8d8b43da	38	clocks = <&tegra_car 100>;
ed821f07 TR	39	};
	40
	41	epp {
	42	compatible = "nvidia,tegra20-epp";
	43	reg = <0x540c0000 0x00040000>;
	44	interrupts = <0 70 0x04>;
8d8b43da	45	clocks = <&tegra_car 19>;
ed821f07 TR	46	};
	47
	48	isp {
	49	compatible = "nvidia,tegra20-isp";
	50	reg = <0x54100000 0x00040000>;
	51	interrupts = <0 71 0x04>;
8d8b43da	52	clocks = <&tegra_car 23>;
ed821f07 TR	53	};
	54
	55	gr2d {
	56	compatible = "nvidia,tegra20-gr2d";
	57	reg = <0x54140000 0x00040000>;
	58	interrupts = <0 72 0x04>;
8d8b43da	59	clocks = <&tegra_car 21>;
ed821f07 TR	60	};
	61
	62	gr3d {
	63	compatible = "nvidia,tegra20-gr3d";
	64	reg = <0x54180000 0x00040000>;
8d8b43da	65	clocks = <&tegra_car 24>;
ed821f07 TR	66	};
	67
	68	dc@54200000 {
	69	compatible = "nvidia,tegra20-dc";
	70	reg = <0x54200000 0x00040000>;
	71	interrupts = <0 73 0x04>;
8d8b43da PG	72	clocks = <&tegra_car 27>, <&tegra_car 121>;
8d8b43da PG	73	clock-names = "disp1", "parent";
ed821f07 TR	74
	75	rgb {
	76	status = "disabled";
	77	};
	78	};
	79
	80	dc@54240000 {
	81	compatible = "nvidia,tegra20-dc";
	82	reg = <0x54240000 0x00040000>;
	83	interrupts = <0 74 0x04>;
8d8b43da PG	84	clocks = <&tegra_car 26>, <&tegra_car 121>;
8d8b43da PG	85	clock-names = "disp2", "parent";
ed821f07 TR	86
	87	rgb {
	88	status = "disabled";
	89	};
	90	};
	91
	92	hdmi {
	93	compatible = "nvidia,tegra20-hdmi";
	94	reg = <0x54280000 0x00040000>;
	95	interrupts = <0 75 0x04>;
8d8b43da PG	96	clocks = <&tegra_car 51>, <&tegra_car 117>;
8d8b43da PG	97	clock-names = "hdmi", "parent";
ed821f07 TR	98	status = "disabled";
	99	};
	100
	101	tvo {
	102	compatible = "nvidia,tegra20-tvo";
	103	reg = <0x542c0000 0x00040000>;
	104	interrupts = <0 76 0x04>;
8d8b43da	105	clocks = <&tegra_car 102>;
ed821f07 TR	106	status = "disabled";
	107	};
	108
	109	dsi {
	110	compatible = "nvidia,tegra20-dsi";
	111	reg = <0x54300000 0x00040000>;
8d8b43da	112	clocks = <&tegra_car 48>;
ed821f07 TR	113	status = "disabled";
	114	};
	115	};
	116
73368ba0 SW	117	timer@50004600 {
	118	compatible = "arm,cortex-a9-twd-timer";
	119	reg = <0x50040600 0x20>;
	120	interrupts = <1 13 0x304>;
	121	};
	122
5ab134ad JL	123	cache-controller@50043000 {
	124	compatible = "arm,pl310-cache";
	125	reg = <0x50043000 0x1000>;
	126	arm,data-latency = <5 5 2>;
	127	arm,tag-latency = <4 4 2>;
	128	cache-unified;
	129	cache-level = <2>;
	130	};
	131
f9eb26a4	132	intc: interrupt-controller {
0d4f7479	133	compatible = "arm,cortex-a9-gic";
5ff48887 SW	134	reg = <0x50041000 0x1000
5ff48887 SW	135	0x50040100 0x0100>;
2eaab06e SW	136	interrupt-controller;
2eaab06e SW	137	#interrupt-cells = <3>;
8e267f3d GL	138	};
8e267f3d GL	139
2f2b7fb2 SW	140	timer@60005000 {
	141	compatible = "nvidia,tegra20-timer";
	142	reg = <0x60005000 0x60>;
	143	interrupts = <0 0 0x04
	144	0 1 0x04
	145	0 41 0x04
	146	0 42 0x04>;
	147	};
	148
270f8ce3 SW	149	tegra_car: clock {
	150	compatible = "nvidia,tegra20-car";
	151	reg = <0x60006000 0x1000>;
	152	#clock-cells = <1>;
	153	};
	154
f9eb26a4	155	apbdma: dma {
8051b75a SW	156	compatible = "nvidia,tegra20-apbdma";
8051b75a SW	157	reg = <0x6000a000 0x1200>;
95decf84 SW	158	interrupts = <0 104 0x04
	159	0 105 0x04
	160	0 106 0x04
	161	0 107 0x04
	162	0 108 0x04
	163	0 109 0x04
	164	0 110 0x04
	165	0 111 0x04
	166	0 112 0x04
	167	0 113 0x04
	168	0 114 0x04
	169	0 115 0x04
	170	0 116 0x04
	171	0 117 0x04
	172	0 118 0x04
	173	0 119 0x04>;
8d8b43da	174	clocks = <&tegra_car 34>;
8051b75a SW	175	};
8051b75a SW	176
c04abb3a SW	177	ahb {
	178	compatible = "nvidia,tegra20-ahb";
	179	reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
8e267f3d GL	180	};
8e267f3d GL	181
f9eb26a4	182	gpio: gpio {
8e267f3d	183	compatible = "nvidia,tegra20-gpio";
95decf84 SW	184	reg = <0x6000d000 0x1000>;
	185	interrupts = <0 32 0x04
	186	0 33 0x04
	187	0 34 0x04
	188	0 35 0x04
	189	0 55 0x04
	190	0 87 0x04
	191	0 89 0x04>;
8e267f3d GL	192	#gpio-cells = <2>;
8e267f3d GL	193	gpio-controller;
6f74dc9b SW	194	#interrupt-cells = <2>;
6f74dc9b SW	195	interrupt-controller;
8e267f3d GL	196	};
8e267f3d GL	197
f9eb26a4	198	pinmux: pinmux {
f62f548c	199	compatible = "nvidia,tegra20-pinmux";
95decf84 SW	200	reg = <0x70000014 0x10 /* Tri-state registers */
	201	0x70000080 0x20 /* Mux registers */
	202	0x700000a0 0x14 /* Pull-up/down registers */
	203	0x70000868 0xa8>; /* Pad control registers */
f62f548c SW	204	};
f62f548c SW	205
c04abb3a SW	206	das {
	207	compatible = "nvidia,tegra20-das";
	208	reg = <0x70000c00 0x80>;
	209	};
0698ed19 LS	210
	211	tegra_ac97: ac97 {
	212	compatible = "nvidia,tegra20-ac97";
	213	reg = <0x70002000 0x200>;
	214	interrupts = <0 81 0x04>;
	215	nvidia,dma-request-selector = <&apbdma 12>;
	216	clocks = <&tegra_car 3>;
	217	status = "disabled";
	218	};
c04abb3a SW	219
	220	tegra_i2s1: i2s@70002800 {
	221	compatible = "nvidia,tegra20-i2s";
	222	reg = <0x70002800 0x200>;
	223	interrupts = <0 13 0x04>;
	224	nvidia,dma-request-selector = <&apbdma 2>;
8d8b43da	225	clocks = <&tegra_car 11>;
223ef78d	226	status = "disabled";
c04abb3a SW	227	};
	228
	229	tegra_i2s2: i2s@70002a00 {
	230	compatible = "nvidia,tegra20-i2s";
	231	reg = <0x70002a00 0x200>;
	232	interrupts = <0 3 0x04>;
	233	nvidia,dma-request-selector = <&apbdma 1>;
8d8b43da	234	clocks = <&tegra_car 18>;
223ef78d	235	status = "disabled";
c04abb3a SW	236	};
c04abb3a SW	237
b6551bb9 LD	238	/*
	239	* There are two serial driver i.e. 8250 based simple serial
	240	* driver and APB DMA based serial driver for higher baudrate
	241	* and performace. To enable the 8250 based driver, the compatible
	242	* is "nvidia,tegra20-uart" and to enable the APB DMA based serial
	243	* driver, the comptible is "nvidia,tegra20-hsuart".
	244	*/
	245	uarta: serial@70006000 {
8e267f3d GL	246	compatible = "nvidia,tegra20-uart";
	247	reg = <0x70006000 0x40>;
	248	reg-shift = <2>;
95decf84	249	interrupts = <0 36 0x04>;
b6551bb9	250	nvidia,dma-request-selector = <&apbdma 8>;
8d8b43da	251	clocks = <&tegra_car 6>;
223ef78d	252	status = "disabled";
8e267f3d GL	253	};
8e267f3d GL	254
b6551bb9	255	uartb: serial@70006040 {
8e267f3d GL	256	compatible = "nvidia,tegra20-uart";
	257	reg = <0x70006040 0x40>;
	258	reg-shift = <2>;
95decf84	259	interrupts = <0 37 0x04>;
b6551bb9	260	nvidia,dma-request-selector = <&apbdma 9>;
8d8b43da	261	clocks = <&tegra_car 96>;
223ef78d	262	status = "disabled";
8e267f3d GL	263	};
8e267f3d GL	264
b6551bb9	265	uartc: serial@70006200 {
8e267f3d GL	266	compatible = "nvidia,tegra20-uart";
	267	reg = <0x70006200 0x100>;
	268	reg-shift = <2>;
95decf84	269	interrupts = <0 46 0x04>;
b6551bb9	270	nvidia,dma-request-selector = <&apbdma 10>;
8d8b43da	271	clocks = <&tegra_car 55>;
223ef78d	272	status = "disabled";
8e267f3d GL	273	};
8e267f3d GL	274
b6551bb9	275	uartd: serial@70006300 {
8e267f3d GL	276	compatible = "nvidia,tegra20-uart";
	277	reg = <0x70006300 0x100>;
	278	reg-shift = <2>;
95decf84	279	interrupts = <0 90 0x04>;
b6551bb9	280	nvidia,dma-request-selector = <&apbdma 19>;
8d8b43da	281	clocks = <&tegra_car 65>;
223ef78d	282	status = "disabled";
8e267f3d GL	283	};
8e267f3d GL	284
b6551bb9	285	uarte: serial@70006400 {
8e267f3d GL	286	compatible = "nvidia,tegra20-uart";
	287	reg = <0x70006400 0x100>;
	288	reg-shift = <2>;
95decf84	289	interrupts = <0 91 0x04>;
b6551bb9	290	nvidia,dma-request-selector = <&apbdma 20>;
8d8b43da	291	clocks = <&tegra_car 66>;
223ef78d	292	status = "disabled";
8e267f3d GL	293	};
8e267f3d GL	294
2b8b15da	295	pwm: pwm {
140fd977 TR	296	compatible = "nvidia,tegra20-pwm";
	297	reg = <0x7000a000 0x100>;
	298	#pwm-cells = <2>;
8d8b43da	299	clocks = <&tegra_car 17>;
140fd977 TR	300	};
140fd977 TR	301
380e04ac SW	302	rtc {
	303	compatible = "nvidia,tegra20-rtc";
	304	reg = <0x7000e000 0x100>;
	305	interrupts = <0 2 0x04>;
	306	};
	307
c04abb3a	308	i2c@7000c000 {
c04abb3a SW	309	compatible = "nvidia,tegra20-i2c";
	310	reg = <0x7000c000 0x100>;
	311	interrupts = <0 38 0x04>;
2eaab06e SW	312	#address-cells = <1>;
2eaab06e SW	313	#size-cells = <0>;
8d8b43da PG	314	clocks = <&tegra_car 12>, <&tegra_car 124>;
8d8b43da PG	315	clock-names = "div-clk", "fast-clk";
223ef78d	316	status = "disabled";
0c6700ab OJ	317	};
0c6700ab OJ	318
fa98a114 LD	319	spi@7000c380 {
	320	compatible = "nvidia,tegra20-sflash";
	321	reg = <0x7000c380 0x80>;
	322	interrupts = <0 39 0x04>;
	323	nvidia,dma-request-selector = <&apbdma 11>;
	324	#address-cells = <1>;
	325	#size-cells = <0>;
8d8b43da	326	clocks = <&tegra_car 43>;
fa98a114 LD	327	status = "disabled";
	328	};
	329
c04abb3a	330	i2c@7000c400 {
c04abb3a SW	331	compatible = "nvidia,tegra20-i2c";
	332	reg = <0x7000c400 0x100>;
	333	interrupts = <0 84 0x04>;
2eaab06e SW	334	#address-cells = <1>;
2eaab06e SW	335	#size-cells = <0>;
8d8b43da PG	336	clocks = <&tegra_car 54>, <&tegra_car 124>;
8d8b43da PG	337	clock-names = "div-clk", "fast-clk";
223ef78d	338	status = "disabled";
8e267f3d GL	339	};
8e267f3d GL	340
c04abb3a	341	i2c@7000c500 {
c04abb3a SW	342	compatible = "nvidia,tegra20-i2c";
	343	reg = <0x7000c500 0x100>;
	344	interrupts = <0 92 0x04>;
2eaab06e SW	345	#address-cells = <1>;
2eaab06e SW	346	#size-cells = <0>;
8d8b43da PG	347	clocks = <&tegra_car 67>, <&tegra_car 124>;
8d8b43da PG	348	clock-names = "div-clk", "fast-clk";
223ef78d	349	status = "disabled";
8e267f3d GL	350	};
8e267f3d GL	351
c04abb3a	352	i2c@7000d000 {
c04abb3a SW	353	compatible = "nvidia,tegra20-i2c-dvc";
	354	reg = <0x7000d000 0x200>;
	355	interrupts = <0 53 0x04>;
2eaab06e SW	356	#address-cells = <1>;
2eaab06e SW	357	#size-cells = <0>;
8d8b43da PG	358	clocks = <&tegra_car 47>, <&tegra_car 124>;
8d8b43da PG	359	clock-names = "div-clk", "fast-clk";
223ef78d	360	status = "disabled";
8e267f3d GL	361	};
8e267f3d GL	362
a86b0db3 LD	363	spi@7000d400 {
	364	compatible = "nvidia,tegra20-slink";
	365	reg = <0x7000d400 0x200>;
	366	interrupts = <0 59 0x04>;
	367	nvidia,dma-request-selector = <&apbdma 15>;
	368	#address-cells = <1>;
	369	#size-cells = <0>;
8d8b43da	370	clocks = <&tegra_car 41>;
a86b0db3 LD	371	status = "disabled";
	372	};
	373
	374	spi@7000d600 {
	375	compatible = "nvidia,tegra20-slink";
	376	reg = <0x7000d600 0x200>;
	377	interrupts = <0 82 0x04>;
	378	nvidia,dma-request-selector = <&apbdma 16>;
	379	#address-cells = <1>;
	380	#size-cells = <0>;
8d8b43da	381	clocks = <&tegra_car 44>;
a86b0db3 LD	382	status = "disabled";
	383	};
	384
	385	spi@7000d800 {
	386	compatible = "nvidia,tegra20-slink";
	387	reg = <0x7000d480 0x200>;
	388	interrupts = <0 83 0x04>;
	389	nvidia,dma-request-selector = <&apbdma 17>;
	390	#address-cells = <1>;
	391	#size-cells = <0>;
8d8b43da	392	clocks = <&tegra_car 46>;
a86b0db3 LD	393	status = "disabled";
	394	};
	395
	396	spi@7000da00 {
	397	compatible = "nvidia,tegra20-slink";
	398	reg = <0x7000da00 0x200>;
	399	interrupts = <0 93 0x04>;
	400	nvidia,dma-request-selector = <&apbdma 18>;
	401	#address-cells = <1>;
	402	#size-cells = <0>;
8d8b43da	403	clocks = <&tegra_car 68>;
a86b0db3 LD	404	status = "disabled";
	405	};
	406
c04abb3a SW	407	pmc {
	408	compatible = "nvidia,tegra20-pmc";
	409	reg = <0x7000e400 0x400>;
	410	};
	411
bbfc33bd	412	memory-controller@7000f000 {
c04abb3a SW	413	compatible = "nvidia,tegra20-mc";
	414	reg = <0x7000f000 0x024
	415	0x7000f03c 0x3c4>;
	416	interrupts = <0 77 0x04>;
	417	};
	418
	419	gart {
	420	compatible = "nvidia,tegra20-gart";
	421	reg = <0x7000f024 0x00000018 /* controller registers */
	422	0x58000000 0x02000000>; /* GART aperture */
	423	};
	424
bbfc33bd	425	memory-controller@7000f400 {
c04abb3a SW	426	compatible = "nvidia,tegra20-emc";
c04abb3a SW	427	reg = <0x7000f400 0x200>;
2eaab06e SW	428	#address-cells = <1>;
2eaab06e SW	429	#size-cells = <0>;
8e267f3d	430	};
c27317c0	431
e374b65c VB	432	phy1: usb-phy@c5000400 {
	433	compatible = "nvidia,tegra20-usb-phy";
	434	reg = <0xc5000400 0x3c00>;
	435	phy_type = "utmi";
	436	nvidia,has-legacy-mode;
540fc9d9 SW	437	clocks = <&tegra_car 22>, <&tegra_car 127>;
540fc9d9 SW	438	clock-names = "phy", "pll_u";
e374b65c VB	439	};
	440
	441	phy2: usb-phy@c5004400 {
	442	compatible = "nvidia,tegra20-usb-phy";
	443	reg = <0xc5004400 0x3c00>;
	444	phy_type = "ulpi";
540fc9d9 SW	445	clocks = <&tegra_car 94>, <&tegra_car 127>;
540fc9d9 SW	446	clock-names = "phy", "pll_u";
e374b65c VB	447	};
	448
	449	phy3: usb-phy@c5008400 {
	450	compatible = "nvidia,tegra20-usb-phy";
	451	reg = <0xc5008400 0x3C00>;
	452	phy_type = "utmi";
540fc9d9 SW	453	clocks = <&tegra_car 22>, <&tegra_car 127>;
540fc9d9 SW	454	clock-names = "phy", "pll_u";
e374b65c VB	455	};
e374b65c VB	456
c27317c0 OJ	457	usb@c5000000 {
	458	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	459	reg = <0xc5000000 0x4000>;
95decf84	460	interrupts = <0 20 0x04>;
c27317c0	461	phy_type = "utmi";
ba202f15	462	nvidia,has-legacy-mode;
8d8b43da	463	clocks = <&tegra_car 22>;
b4e07478	464	nvidia,needs-double-reset;
e374b65c	465	nvidia,phy = <&phy1>;
223ef78d	466	status = "disabled";
c27317c0 OJ	467	};
	468
	469	usb@c5004000 {
	470	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	471	reg = <0xc5004000 0x4000>;
95decf84	472	interrupts = <0 21 0x04>;
c27317c0	473	phy_type = "ulpi";
8d8b43da	474	clocks = <&tegra_car 58>;
e374b65c	475	nvidia,phy = <&phy2>;
223ef78d	476	status = "disabled";
c27317c0 OJ	477	};
	478
	479	usb@c5008000 {
	480	compatible = "nvidia,tegra20-ehci", "usb-ehci";
	481	reg = <0xc5008000 0x4000>;
95decf84	482	interrupts = <0 97 0x04>;
c27317c0	483	phy_type = "utmi";
8d8b43da	484	clocks = <&tegra_car 59>;
e374b65c	485	nvidia,phy = <&phy3>;
223ef78d	486	status = "disabled";
c27317c0	487	};
7868a9bc	488
c04abb3a SW	489	sdhci@c8000000 {
	490	compatible = "nvidia,tegra20-sdhci";
	491	reg = <0xc8000000 0x200>;
	492	interrupts = <0 14 0x04>;
8d8b43da	493	clocks = <&tegra_car 14>;
223ef78d	494	status = "disabled";
7868a9bc	495	};
4a82f2b3	496
c04abb3a SW	497	sdhci@c8000200 {
	498	compatible = "nvidia,tegra20-sdhci";
	499	reg = <0xc8000200 0x200>;
	500	interrupts = <0 15 0x04>;
8d8b43da	501	clocks = <&tegra_car 9>;
223ef78d	502	status = "disabled";
4a82f2b3	503	};
6a943e0e	504
c04abb3a SW	505	sdhci@c8000400 {
	506	compatible = "nvidia,tegra20-sdhci";
	507	reg = <0xc8000400 0x200>;
	508	interrupts = <0 19 0x04>;
8d8b43da	509	clocks = <&tegra_car 69>;
223ef78d	510	status = "disabled";
c04abb3a SW	511	};
	512
	513	sdhci@c8000600 {
	514	compatible = "nvidia,tegra20-sdhci";
	515	reg = <0xc8000600 0x200>;
	516	interrupts = <0 31 0x04>;
8d8b43da	517	clocks = <&tegra_car 15>;
223ef78d	518	status = "disabled";
c04abb3a SW	519	};
c04abb3a SW	520
4dd2bd37 HD	521	cpus {
	522	#address-cells = <1>;
	523	#size-cells = <0>;
	524
	525	cpu@0 {
	526	device_type = "cpu";
	527	compatible = "arm,cortex-a9";
	528	reg = <0>;
	529	};
	530
	531	cpu@1 {
	532	device_type = "cpu";
	533	compatible = "arm,cortex-a9";
	534	reg = <1>;
	535	};
	536	};
	537
c04abb3a SW	538	pmu {
	539	compatible = "arm,cortex-a9-pmu";
	540	interrupts = <0 56 0x04
	541	0 57 0x04>;
6a943e0e	542	};
8e267f3d	543	};