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ARM: tegra: add port FF to GPIO IDs
[deliverable/linux.git] / arch / arm / boot / dts / tegra20.dtsi
CommitLineData
885a8cfa 1#include <dt-bindings/clock/tegra20-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
6cecf916 3#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 4
1bd0bd49 5#include "skeleton.dtsi"
8e267f3d
GL		 6
7/ {
8 compatible = "nvidia,tegra20";
9 interrupt-parent = <&intc>;
10
b6551bb9
LD		 11 aliases {
12 serial0 = &uarta;
13 serial1 = &uartb;
14 serial2 = &uartc;
15 serial3 = &uartd;
16 serial4 = &uarte;
17 };
18
ed821f07
TR		 19 host1x {
20 compatible = "nvidia,tegra20-host1x", "simple-bus";
21 reg = <0x50000000 0x00024000>;
6cecf916
SW		 22 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
23 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
885a8cfa 24 clocks = <&tegra_car TEGRA20_CLK_HOST1X>;
3393d422
SW		 25 resets = <&tegra_car 28>;
26 reset-names = "host1x";
ed821f07
TR		 27
28 #address-cells = <1>;
29 #size-cells = <1>;
30
31 ranges = <0x54000000 0x54000000 0x04000000>;
32
33 mpe {
34 compatible = "nvidia,tegra20-mpe";
35 reg = <0x54040000 0x00040000>;
6cecf916 36 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 37 clocks = <&tegra_car TEGRA20_CLK_MPE>;
3393d422
SW		 38 resets = <&tegra_car 60>;
39 reset-names = "mpe";
ed821f07
TR		 40 };
41
42 vi {
43 compatible = "nvidia,tegra20-vi";
44 reg = <0x54080000 0x00040000>;
6cecf916 45 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 46 clocks = <&tegra_car TEGRA20_CLK_VI>;
3393d422
SW		 47 resets = <&tegra_car 20>;
48 reset-names = "vi";
ed821f07
TR		 49 };
50
51 epp {
52 compatible = "nvidia,tegra20-epp";
53 reg = <0x540c0000 0x00040000>;
6cecf916 54 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 55 clocks = <&tegra_car TEGRA20_CLK_EPP>;
3393d422
SW		 56 resets = <&tegra_car 19>;
57 reset-names = "epp";
ed821f07
TR		 58 };
59
60 isp {
61 compatible = "nvidia,tegra20-isp";
62 reg = <0x54100000 0x00040000>;
6cecf916 63 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 64 clocks = <&tegra_car TEGRA20_CLK_ISP>;
3393d422
SW		 65 resets = <&tegra_car 23>;
66 reset-names = "isp";
ed821f07
TR		 67 };
68
69 gr2d {
70 compatible = "nvidia,tegra20-gr2d";
71 reg = <0x54140000 0x00040000>;
6cecf916 72 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 73 clocks = <&tegra_car TEGRA20_CLK_GR2D>;
3393d422
SW		 74 resets = <&tegra_car 21>;
75 reset-names = "2d";
ed821f07
TR		 76 };
77
78 gr3d {
79 compatible = "nvidia,tegra20-gr3d";
80 reg = <0x54180000 0x00040000>;
885a8cfa 81 clocks = <&tegra_car TEGRA20_CLK_GR3D>;
3393d422
SW		 82 resets = <&tegra_car 24>;
83 reset-names = "3d";
ed821f07
TR		 84 };
85
86 dc@54200000 {
87 compatible = "nvidia,tegra20-dc";
88 reg = <0x54200000 0x00040000>;
6cecf916 89 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 90 clocks = <&tegra_car TEGRA20_CLK_DISP1>,
91 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 92 clock-names = "dc", "parent";
3393d422
SW		 93 resets = <&tegra_car 27>;
94 reset-names = "dc";
ed821f07
TR		 95
96 rgb {
97 status = "disabled";
98 };
99 };
100
101 dc@54240000 {
102 compatible = "nvidia,tegra20-dc";
103 reg = <0x54240000 0x00040000>;
6cecf916 104 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 105 clocks = <&tegra_car TEGRA20_CLK_DISP2>,
106 <&tegra_car TEGRA20_CLK_PLL_P>;
d8f64797 107 clock-names = "dc", "parent";
3393d422
SW		 108 resets = <&tegra_car 26>;
109 reset-names = "dc";
ed821f07
TR		 110
111 rgb {
112 status = "disabled";
113 };
114 };
115
116 hdmi {
117 compatible = "nvidia,tegra20-hdmi";
118 reg = <0x54280000 0x00040000>;
6cecf916 119 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa
HD		 120 clocks = <&tegra_car TEGRA20_CLK_HDMI>,
121 <&tegra_car TEGRA20_CLK_PLL_D_OUT0>;
8d8b43da 122 clock-names = "hdmi", "parent";
3393d422
SW		 123 resets = <&tegra_car 51>;
124 reset-names = "hdmi";
ed821f07
TR		 125 status = "disabled";
126 };
127
128 tvo {
129 compatible = "nvidia,tegra20-tvo";
130 reg = <0x542c0000 0x00040000>;
6cecf916 131 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 132 clocks = <&tegra_car TEGRA20_CLK_TVO>;
ed821f07
TR		 133 status = "disabled";
134 };
135
136 dsi {
137 compatible = "nvidia,tegra20-dsi";
138 reg = <0x54300000 0x00040000>;
885a8cfa 139 clocks = <&tegra_car TEGRA20_CLK_DSI>;
3393d422
SW		 140 resets = <&tegra_car 48>;
141 reset-names = "dsi";
ed821f07
TR		 142 status = "disabled";
143 };
144 };
145
73368ba0
SW		 146 timer@50004600 {
147 compatible = "arm,cortex-a9-twd-timer";
148 reg = <0x50040600 0x20>;
6cecf916
SW		 149 interrupts = <GIC_PPI 13
150 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
885a8cfa 151 clocks = <&tegra_car TEGRA20_CLK_TWD>;
73368ba0
SW		 152 };
153
f9eb26a4 154 intc: interrupt-controller {
0d4f7479 155 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 156 reg = <0x50041000 0x1000
157 0x50040100 0x0100>;
2eaab06e
SW		 158 interrupt-controller;
159 #interrupt-cells = <3>;
8e267f3d
GL		 160 };
161
bb2c1de9
SW		 162 cache-controller {
163 compatible = "arm,pl310-cache";
164 reg = <0x50043000 0x1000>;
165 arm,data-latency = <5 5 2>;
166 arm,tag-latency = <4 4 2>;
167 cache-unified;
168 cache-level = <2>;
169 };
170
2f2b7fb2
SW		 171 timer@60005000 {
172 compatible = "nvidia,tegra20-timer";
173 reg = <0x60005000 0x60>;
6cecf916
SW		 174 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
175 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
176 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
177 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 178 clocks = <&tegra_car TEGRA20_CLK_TIMER>;
2f2b7fb2
SW		 179 };
180
270f8ce3
SW		 181 tegra_car: clock {
182 compatible = "nvidia,tegra20-car";
183 reg = <0x60006000 0x1000>;
184 #clock-cells = <1>;
3393d422 185 #reset-cells = <1>;
270f8ce3
SW		 186 };
187
f9eb26a4 188 apbdma: dma {
8051b75a
SW		 189 compatible = "nvidia,tegra20-apbdma";
190 reg = <0x6000a000 0x1200>;
6cecf916
SW		 191 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
192 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
193 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
194 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
195 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
196 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
197 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
198 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
199 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
200 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
201 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
202 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
203 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
204 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 207 clocks = <&tegra_car TEGRA20_CLK_APBDMA>;
3393d422
SW		 208 resets = <&tegra_car 34>;
209 reset-names = "dma";
034d023f 210 #dma-cells = <1>;
8051b75a
SW		 211 };
212
c04abb3a
SW		 213 ahb {
214 compatible = "nvidia,tegra20-ahb";
215 reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */
8e267f3d
GL		 216 };
217
f9eb26a4 218 gpio: gpio {
8e267f3d 219 compatible = "nvidia,tegra20-gpio";
95decf84 220 reg = <0x6000d000 0x1000>;
6cecf916
SW		 221 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
222 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
223 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
224 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
225 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
226 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
227 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
8e267f3d
GL		 228 #gpio-cells = <2>;
229 gpio-controller;
6f74dc9b
SW		 230 #interrupt-cells = <2>;
231 interrupt-controller;
8e267f3d
GL		 232 };
233
f9eb26a4 234 pinmux: pinmux {
f62f548c 235 compatible = "nvidia,tegra20-pinmux";
95decf84
SW		 236 reg = <0x70000014 0x10 /* Tri-state registers */
237 0x70000080 0x20 /* Mux registers */
238 0x700000a0 0x14 /* Pull-up/down registers */
239 0x70000868 0xa8>; /* Pad control registers */
f62f548c
SW		 240 };
241
c04abb3a
SW		 242 das {
243 compatible = "nvidia,tegra20-das";
244 reg = <0x70000c00 0x80>;
245 };
fc5c306b 246
0698ed19
LS		 247 tegra_ac97: ac97 {
248 compatible = "nvidia,tegra20-ac97";
249 reg = <0x70002000 0x200>;
6cecf916 250 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 251 clocks = <&tegra_car TEGRA20_CLK_AC97>;
3393d422
SW		 252 resets = <&tegra_car 3>;
253 reset-names = "ac97";
034d023f
SW		 254 dmas = <&apbdma 12>, <&apbdma 12>;
255 dma-names = "rx", "tx";
0698ed19
LS		 256 status = "disabled";
257 };
c04abb3a
SW		 258
259 tegra_i2s1: i2s@70002800 {
260 compatible = "nvidia,tegra20-i2s";
261 reg = <0x70002800 0x200>;
6cecf916 262 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 263 clocks = <&tegra_car TEGRA20_CLK_I2S1>;
3393d422
SW		 264 resets = <&tegra_car 11>;
265 reset-names = "i2s";
034d023f
SW		 266 dmas = <&apbdma 2>, <&apbdma 2>;
267 dma-names = "rx", "tx";
223ef78d 268 status = "disabled";
c04abb3a
SW		 269 };
270
271 tegra_i2s2: i2s@70002a00 {
272 compatible = "nvidia,tegra20-i2s";
273 reg = <0x70002a00 0x200>;
6cecf916 274 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 275 clocks = <&tegra_car TEGRA20_CLK_I2S2>;
3393d422
SW		 276 resets = <&tegra_car 18>;
277 reset-names = "i2s";
034d023f
SW		 278 dmas = <&apbdma 1>, <&apbdma 1>;
279 dma-names = "rx", "tx";
223ef78d 280 status = "disabled";
c04abb3a
SW		 281 };
282
b6551bb9
LD		 283 /*
284 * There are two serial driver i.e. 8250 based simple serial
285 * driver and APB DMA based serial driver for higher baudrate
286 * and performace. To enable the 8250 based driver, the compatible
287 * is "nvidia,tegra20-uart" and to enable the APB DMA based serial
288 * driver, the comptible is "nvidia,tegra20-hsuart".
289 */
290 uarta: serial@70006000 {
8e267f3d
GL		 291 compatible = "nvidia,tegra20-uart";
292 reg = <0x70006000 0x40>;
293 reg-shift = <2>;
6cecf916 294 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 295 clocks = <&tegra_car TEGRA20_CLK_UARTA>;
3393d422
SW		 296 resets = <&tegra_car 6>;
297 reset-names = "serial";
034d023f
SW		 298 dmas = <&apbdma 8>, <&apbdma 8>;
299 dma-names = "rx", "tx";
223ef78d 300 status = "disabled";
8e267f3d
GL		 301 };
302
b6551bb9 303 uartb: serial@70006040 {
8e267f3d
GL		 304 compatible = "nvidia,tegra20-uart";
305 reg = <0x70006040 0x40>;
306 reg-shift = <2>;
6cecf916 307 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 308 clocks = <&tegra_car TEGRA20_CLK_UARTB>;
3393d422
SW		 309 resets = <&tegra_car 7>;
310 reset-names = "serial";
034d023f
SW		 311 dmas = <&apbdma 9>, <&apbdma 9>;
312 dma-names = "rx", "tx";
223ef78d 313 status = "disabled";
8e267f3d
GL		 314 };
315
b6551bb9 316 uartc: serial@70006200 {
8e267f3d
GL		 317 compatible = "nvidia,tegra20-uart";
318 reg = <0x70006200 0x100>;
319 reg-shift = <2>;
6cecf916 320 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 321 clocks = <&tegra_car TEGRA20_CLK_UARTC>;
3393d422
SW		 322 resets = <&tegra_car 55>;
323 reset-names = "serial";
034d023f
SW		 324 dmas = <&apbdma 10>, <&apbdma 10>;
325 dma-names = "rx", "tx";
223ef78d 326 status = "disabled";
8e267f3d
GL		 327 };
328
b6551bb9 329 uartd: serial@70006300 {
8e267f3d
GL		 330 compatible = "nvidia,tegra20-uart";
331 reg = <0x70006300 0x100>;
332 reg-shift = <2>;
6cecf916 333 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 334 clocks = <&tegra_car TEGRA20_CLK_UARTD>;
3393d422
SW		 335 resets = <&tegra_car 65>;
336 reset-names = "serial";
034d023f
SW		 337 dmas = <&apbdma 19>, <&apbdma 19>;
338 dma-names = "rx", "tx";
223ef78d 339 status = "disabled";
8e267f3d
GL		 340 };
341
b6551bb9 342 uarte: serial@70006400 {
8e267f3d
GL		 343 compatible = "nvidia,tegra20-uart";
344 reg = <0x70006400 0x100>;
345 reg-shift = <2>;
6cecf916 346 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 347 clocks = <&tegra_car TEGRA20_CLK_UARTE>;
3393d422
SW		 348 resets = <&tegra_car 66>;
349 reset-names = "serial";
034d023f
SW		 350 dmas = <&apbdma 20>, <&apbdma 20>;
351 dma-names = "rx", "tx";
223ef78d 352 status = "disabled";
8e267f3d
GL		 353 };
354
2b8b15da 355 pwm: pwm {
140fd977
TR		 356 compatible = "nvidia,tegra20-pwm";
357 reg = <0x7000a000 0x100>;
358 #pwm-cells = <2>;
885a8cfa 359 clocks = <&tegra_car TEGRA20_CLK_PWM>;
3393d422
SW		 360 resets = <&tegra_car 17>;
361 reset-names = "pwm";
b69cd984 362 status = "disabled";
140fd977
TR		 363 };
364
380e04ac
SW		 365 rtc {
366 compatible = "nvidia,tegra20-rtc";
367 reg = <0x7000e000 0x100>;
6cecf916 368 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 369 clocks = <&tegra_car TEGRA20_CLK_RTC>;
380e04ac
SW		 370 };
371
c04abb3a 372 i2c@7000c000 {
c04abb3a
SW		 373 compatible = "nvidia,tegra20-i2c";
374 reg = <0x7000c000 0x100>;
6cecf916 375 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 376 #address-cells = <1>;
377 #size-cells = <0>;
885a8cfa
HD		 378 clocks = <&tegra_car TEGRA20_CLK_I2C1>,
379 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 380 clock-names = "div-clk", "fast-clk";
3393d422
SW		 381 resets = <&tegra_car 12>;
382 reset-names = "i2c";
034d023f
SW		 383 dmas = <&apbdma 21>, <&apbdma 21>;
384 dma-names = "rx", "tx";
223ef78d 385 status = "disabled";
0c6700ab
OJ		 386 };
387
fa98a114
LD		 388 spi@7000c380 {
389 compatible = "nvidia,tegra20-sflash";
390 reg = <0x7000c380 0x80>;
6cecf916 391 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
fa98a114
LD		 392 #address-cells = <1>;
393 #size-cells = <0>;
885a8cfa 394 clocks = <&tegra_car TEGRA20_CLK_SPI>;
3393d422
SW		 395 resets = <&tegra_car 43>;
396 reset-names = "spi";
034d023f
SW		 397 dmas = <&apbdma 11>, <&apbdma 11>;
398 dma-names = "rx", "tx";
fa98a114
LD		 399 status = "disabled";
400 };
401
c04abb3a 402 i2c@7000c400 {
c04abb3a
SW		 403 compatible = "nvidia,tegra20-i2c";
404 reg = <0x7000c400 0x100>;
6cecf916 405 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 406 #address-cells = <1>;
407 #size-cells = <0>;
885a8cfa
HD		 408 clocks = <&tegra_car TEGRA20_CLK_I2C2>,
409 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 410 clock-names = "div-clk", "fast-clk";
3393d422
SW		 411 resets = <&tegra_car 54>;
412 reset-names = "i2c";
034d023f
SW		 413 dmas = <&apbdma 22>, <&apbdma 22>;
414 dma-names = "rx", "tx";
223ef78d 415 status = "disabled";
8e267f3d
GL		 416 };
417
c04abb3a 418 i2c@7000c500 {
c04abb3a
SW		 419 compatible = "nvidia,tegra20-i2c";
420 reg = <0x7000c500 0x100>;
6cecf916 421 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 422 #address-cells = <1>;
423 #size-cells = <0>;
885a8cfa
HD		 424 clocks = <&tegra_car TEGRA20_CLK_I2C3>,
425 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 426 clock-names = "div-clk", "fast-clk";
3393d422
SW		 427 resets = <&tegra_car 67>;
428 reset-names = "i2c";
034d023f
SW		 429 dmas = <&apbdma 23>, <&apbdma 23>;
430 dma-names = "rx", "tx";
223ef78d 431 status = "disabled";
8e267f3d
GL		 432 };
433
c04abb3a 434 i2c@7000d000 {
c04abb3a
SW		 435 compatible = "nvidia,tegra20-i2c-dvc";
436 reg = <0x7000d000 0x200>;
6cecf916 437 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 438 #address-cells = <1>;
439 #size-cells = <0>;
885a8cfa
HD		 440 clocks = <&tegra_car TEGRA20_CLK_DVC>,
441 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
8d8b43da 442 clock-names = "div-clk", "fast-clk";
3393d422
SW		 443 resets = <&tegra_car 47>;
444 reset-names = "i2c";
034d023f
SW		 445 dmas = <&apbdma 24>, <&apbdma 24>;
446 dma-names = "rx", "tx";
223ef78d 447 status = "disabled";
8e267f3d
GL		 448 };
449
a86b0db3
LD		 450 spi@7000d400 {
451 compatible = "nvidia,tegra20-slink";
452 reg = <0x7000d400 0x200>;
6cecf916 453 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 454 #address-cells = <1>;
455 #size-cells = <0>;
885a8cfa 456 clocks = <&tegra_car TEGRA20_CLK_SBC1>;
3393d422
SW		 457 resets = <&tegra_car 41>;
458 reset-names = "spi";
034d023f
SW		 459 dmas = <&apbdma 15>, <&apbdma 15>;
460 dma-names = "rx", "tx";
a86b0db3
LD		 461 status = "disabled";
462 };
463
464 spi@7000d600 {
465 compatible = "nvidia,tegra20-slink";
466 reg = <0x7000d600 0x200>;
6cecf916 467 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 468 #address-cells = <1>;
469 #size-cells = <0>;
885a8cfa 470 clocks = <&tegra_car TEGRA20_CLK_SBC2>;
3393d422
SW		 471 resets = <&tegra_car 44>;
472 reset-names = "spi";
034d023f
SW		 473 dmas = <&apbdma 16>, <&apbdma 16>;
474 dma-names = "rx", "tx";
a86b0db3
LD		 475 status = "disabled";
476 };
477
478 spi@7000d800 {
479 compatible = "nvidia,tegra20-slink";
57471c8d 480 reg = <0x7000d800 0x200>;
6cecf916 481 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 482 #address-cells = <1>;
483 #size-cells = <0>;
885a8cfa 484 clocks = <&tegra_car TEGRA20_CLK_SBC3>;
3393d422
SW		 485 resets = <&tegra_car 46>;
486 reset-names = "spi";
034d023f
SW		 487 dmas = <&apbdma 17>, <&apbdma 17>;
488 dma-names = "rx", "tx";
a86b0db3
LD		 489 status = "disabled";
490 };
491
492 spi@7000da00 {
493 compatible = "nvidia,tegra20-slink";
494 reg = <0x7000da00 0x200>;
6cecf916 495 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 496 #address-cells = <1>;
497 #size-cells = <0>;
885a8cfa 498 clocks = <&tegra_car TEGRA20_CLK_SBC4>;
3393d422
SW		 499 resets = <&tegra_car 68>;
500 reset-names = "spi";
034d023f
SW		 501 dmas = <&apbdma 18>, <&apbdma 18>;
502 dma-names = "rx", "tx";
a86b0db3
LD		 503 status = "disabled";
504 };
505
699ed4b9
LD		 506 kbc {
507 compatible = "nvidia,tegra20-kbc";
508 reg = <0x7000e200 0x100>;
6cecf916 509 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 510 clocks = <&tegra_car TEGRA20_CLK_KBC>;
3393d422
SW		 511 resets = <&tegra_car 36>;
512 reset-names = "kbc";
699ed4b9
LD		 513 status = "disabled";
514 };
515
c04abb3a
SW		 516 pmc {
517 compatible = "nvidia,tegra20-pmc";
518 reg = <0x7000e400 0x400>;
885a8cfa 519 clocks = <&tegra_car TEGRA20_CLK_PCLK>, <&clk32k_in>;
7021d122 520 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 521 };
522
bbfc33bd 523 memory-controller@7000f000 {
c04abb3a
SW		 524 compatible = "nvidia,tegra20-mc";
525 reg = <0x7000f000 0x024
526 0x7000f03c 0x3c4>;
6cecf916 527 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a
SW		 528 };
529
109269e8 530 iommu {
c04abb3a
SW		 531 compatible = "nvidia,tegra20-gart";
532 reg = <0x7000f024 0x00000018 /* controller registers */
533 0x58000000 0x02000000>; /* GART aperture */
534 };
535
bbfc33bd 536 memory-controller@7000f400 {
c04abb3a
SW		 537 compatible = "nvidia,tegra20-emc";
538 reg = <0x7000f400 0x200>;
2eaab06e
SW		 539 #address-cells = <1>;
540 #size-cells = <0>;
8e267f3d 541 };
c27317c0 542
1b62b611
TR		 543 pcie-controller {
544 compatible = "nvidia,tegra20-pcie";
545 device_type = "pci";
546 reg = <0x80003000 0x00000800 /* PADS registers */
547 0x80003800 0x00000200 /* AFI registers */
548 0x90000000 0x10000000>; /* configuration space */
549 reg-names = "pads", "afi", "cs";
550 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
551 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
552 interrupt-names = "intr", "msi";
553
554 bus-range = <0x00 0xff>;
555 #address-cells = <3>;
556 #size-cells = <2>;
557
558 ranges = <0x82000000 0 0x80000000 0x80000000 0 0x00001000 /* port 0 registers */
559 0x82000000 0 0x80001000 0x80001000 0 0x00001000 /* port 1 registers */
560 0x81000000 0 0 0x82000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 561 0x82000000 0 0xa0000000 0xa0000000 0 0x08000000 /* non-prefetchable memory */
562 0xc2000000 0 0xa8000000 0xa8000000 0 0x18000000>; /* prefetchable memory */
1b62b611
TR		 563
564 clocks = <&tegra_car TEGRA20_CLK_PEX>,
565 <&tegra_car TEGRA20_CLK_AFI>,
1b62b611 566 <&tegra_car TEGRA20_CLK_PLL_E>;
2bd541ff 567 clock-names = "pex", "afi", "pll_e";
3393d422
SW		 568 resets = <&tegra_car 70>,
569 <&tegra_car 72>,
570 <&tegra_car 74>;
571 reset-names = "pex", "afi", "pcie_x";
1b62b611
TR		 572 status = "disabled";
573
574 pci@1,0 {
575 device_type = "pci";
576 assigned-addresses = <0x82000800 0 0x80000000 0 0x1000>;
577 reg = <0x000800 0 0 0 0>;
578 status = "disabled";
579
580 #address-cells = <3>;
581 #size-cells = <2>;
582 ranges;
583
584 nvidia,num-lanes = <2>;
585 };
586
587 pci@2,0 {
588 device_type = "pci";
589 assigned-addresses = <0x82001000 0 0x80001000 0 0x1000>;
590 reg = <0x001000 0 0 0 0>;
591 status = "disabled";
592
593 #address-cells = <3>;
594 #size-cells = <2>;
595 ranges;
596
597 nvidia,num-lanes = <2>;
598 };
599 };
600
c27317c0
OJ		 601 usb@c5000000 {
602 compatible = "nvidia,tegra20-ehci", "usb-ehci";
603 reg = <0xc5000000 0x4000>;
6cecf916 604 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 605 phy_type = "utmi";
ba202f15 606 nvidia,has-legacy-mode;
885a8cfa 607 clocks = <&tegra_car TEGRA20_CLK_USBD>;
3393d422
SW		 608 resets = <&tegra_car 22>;
609 reset-names = "usb";
b4e07478 610 nvidia,needs-double-reset;
e374b65c 611 nvidia,phy = <&phy1>;
223ef78d 612 status = "disabled";
c27317c0
OJ		 613 };
614
4c94c8b5 615 phy1: usb-phy@c5000000 {
5d324410 616 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 617 reg = <0xc5000000 0x4000 0xc5000000 0x4000>;
5d324410 618 phy_type = "utmi";
885a8cfa
HD		 619 clocks = <&tegra_car TEGRA20_CLK_USBD>,
620 <&tegra_car TEGRA20_CLK_PLL_U>,
621 <&tegra_car TEGRA20_CLK_CLK_M>,
622 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 623 clock-names = "reg", "pll_u", "timer", "utmi-pads";
5d324410 624 nvidia,has-legacy-mode;
c49667e5
MP		 625 nvidia,hssync-start-delay = <9>;
626 nvidia,idle-wait-delay = <17>;
627 nvidia,elastic-limit = <16>;
628 nvidia,term-range-adj = <6>;
629 nvidia,xcvr-setup = <9>;
630 nvidia,xcvr-lsfslew = <1>;
631 nvidia,xcvr-lsrslew = <1>;
4c94c8b5 632 status = "disabled";
5d324410
SW		 633 };
634
c27317c0
OJ		 635 usb@c5004000 {
636 compatible = "nvidia,tegra20-ehci", "usb-ehci";
637 reg = <0xc5004000 0x4000>;
6cecf916 638 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 639 phy_type = "ulpi";
885a8cfa 640 clocks = <&tegra_car TEGRA20_CLK_USB2>;
3393d422
SW		 641 resets = <&tegra_car 58>;
642 reset-names = "usb";
e374b65c 643 nvidia,phy = <&phy2>;
223ef78d 644 status = "disabled";
c27317c0
OJ		 645 };
646
4c94c8b5 647 phy2: usb-phy@c5004000 {
5d324410 648 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 649 reg = <0xc5004000 0x4000>;
5d324410 650 phy_type = "ulpi";
885a8cfa
HD		 651 clocks = <&tegra_car TEGRA20_CLK_USB2>,
652 <&tegra_car TEGRA20_CLK_PLL_U>,
653 <&tegra_car TEGRA20_CLK_CDEV2>;
4c94c8b5
VB		 654 clock-names = "reg", "pll_u", "ulpi-link";
655 status = "disabled";
5d324410
SW		 656 };
657
c27317c0
OJ		 658 usb@c5008000 {
659 compatible = "nvidia,tegra20-ehci", "usb-ehci";
660 reg = <0xc5008000 0x4000>;
6cecf916 661 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
c27317c0 662 phy_type = "utmi";
885a8cfa 663 clocks = <&tegra_car TEGRA20_CLK_USB3>;
3393d422
SW		 664 resets = <&tegra_car 59>;
665 reset-names = "usb";
e374b65c 666 nvidia,phy = <&phy3>;
223ef78d 667 status = "disabled";
c27317c0 668 };
7868a9bc 669
4c94c8b5 670 phy3: usb-phy@c5008000 {
5d324410 671 compatible = "nvidia,tegra20-usb-phy";
4c94c8b5 672 reg = <0xc5008000 0x4000 0xc5000000 0x4000>;
5d324410 673 phy_type = "utmi";
885a8cfa
HD		 674 clocks = <&tegra_car TEGRA20_CLK_USB3>,
675 <&tegra_car TEGRA20_CLK_PLL_U>,
676 <&tegra_car TEGRA20_CLK_CLK_M>,
677 <&tegra_car TEGRA20_CLK_USBD>;
4c94c8b5 678 clock-names = "reg", "pll_u", "timer", "utmi-pads";
c49667e5
MP		 679 nvidia,hssync-start-delay = <9>;
680 nvidia,idle-wait-delay = <17>;
681 nvidia,elastic-limit = <16>;
682 nvidia,term-range-adj = <6>;
683 nvidia,xcvr-setup = <9>;
684 nvidia,xcvr-lsfslew = <2>;
685 nvidia,xcvr-lsrslew = <2>;
4c94c8b5 686 status = "disabled";
5d324410
SW		 687 };
688
c04abb3a
SW		 689 sdhci@c8000000 {
690 compatible = "nvidia,tegra20-sdhci";
691 reg = <0xc8000000 0x200>;
6cecf916 692 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 693 clocks = <&tegra_car TEGRA20_CLK_SDMMC1>;
3393d422
SW		 694 resets = <&tegra_car 14>;
695 reset-names = "sdhci";
223ef78d 696 status = "disabled";
7868a9bc 697 };
4a82f2b3 698
c04abb3a
SW		 699 sdhci@c8000200 {
700 compatible = "nvidia,tegra20-sdhci";
701 reg = <0xc8000200 0x200>;
6cecf916 702 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 703 clocks = <&tegra_car TEGRA20_CLK_SDMMC2>;
3393d422
SW		 704 resets = <&tegra_car 9>;
705 reset-names = "sdhci";
223ef78d 706 status = "disabled";
4a82f2b3 707 };
6a943e0e 708
c04abb3a
SW		 709 sdhci@c8000400 {
710 compatible = "nvidia,tegra20-sdhci";
711 reg = <0xc8000400 0x200>;
6cecf916 712 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 713 clocks = <&tegra_car TEGRA20_CLK_SDMMC3>;
3393d422
SW		 714 resets = <&tegra_car 69>;
715 reset-names = "sdhci";
223ef78d 716 status = "disabled";
c04abb3a
SW		 717 };
718
719 sdhci@c8000600 {
720 compatible = "nvidia,tegra20-sdhci";
721 reg = <0xc8000600 0x200>;
6cecf916 722 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
885a8cfa 723 clocks = <&tegra_car TEGRA20_CLK_SDMMC4>;
3393d422
SW		 724 resets = <&tegra_car 15>;
725 reset-names = "sdhci";
223ef78d 726 status = "disabled";
c04abb3a
SW		 727 };
728
4dd2bd37
HD		 729 cpus {
730 #address-cells = <1>;
731 #size-cells = <0>;
732
733 cpu@0 {
734 device_type = "cpu";
735 compatible = "arm,cortex-a9";
736 reg = <0>;
737 };
738
739 cpu@1 {
740 device_type = "cpu";
741 compatible = "arm,cortex-a9";
742 reg = <1>;
743 };
744 };
745
c04abb3a
SW		 746 pmu {
747 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 748 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
749 <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
6a943e0e 750 };
8e267f3d 751};
Linux kernel - Deliverables
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