projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 8e267f3d GL |
1 | /include/ "skeleton.dtsi" |
| 2 | ||
| 3 | / { | |
| 4 | compatible = "nvidia,tegra20"; | |
| 5 | interrupt-parent = <&intc>; | |
| 6 | ||
| b6551bb9 LD |
7 | aliases { |
| 8 | serial0 = &uarta; | |
| 9 | serial1 = &uartb; | |
| 10 | serial2 = &uartc; | |
| 11 | serial3 = &uartd; | |
| 12 | serial4 = &uarte; | |
| 13 | }; | |
| 14 | ||
| ed821f07 TR |
15 | host1x { |
| 16 | compatible = "nvidia,tegra20-host1x", "simple-bus"; | |
| 17 | reg = <0x50000000 0x00024000>; | |
| 18 | interrupts = <0 65 0x04 /* mpcore syncpt */ | |
| 19 | 0 67 0x04>; /* mpcore general */ | |
| 8d8b43da | 20 | clocks = <&tegra_car 28>; |
| ed821f07 TR |
21 | |
| 22 | #address-cells = <1>; | |
| 23 | #size-cells = <1>; | |
| 24 | ||
| 25 | ranges = <0x54000000 0x54000000 0x04000000>; | |
| 26 | ||
| 27 | mpe { | |
| 28 | compatible = "nvidia,tegra20-mpe"; | |
| 29 | reg = <0x54040000 0x00040000>; | |
| 30 | interrupts = <0 68 0x04>; | |
| 8d8b43da | 31 | clocks = <&tegra_car 60>; |
| ed821f07 TR |
32 | }; |
| 33 | ||
| 34 | vi { | |
| 35 | compatible = "nvidia,tegra20-vi"; | |
| 36 | reg = <0x54080000 0x00040000>; | |
| 37 | interrupts = <0 69 0x04>; | |
| 8d8b43da | 38 | clocks = <&tegra_car 100>; |
| ed821f07 TR |
39 | }; |
| 40 | ||
| 41 | epp { | |
| 42 | compatible = "nvidia,tegra20-epp"; | |
| 43 | reg = <0x540c0000 0x00040000>; | |
| 44 | interrupts = <0 70 0x04>; | |
| 8d8b43da | 45 | clocks = <&tegra_car 19>; |
| ed821f07 TR |
46 | }; |
| 47 | ||
| 48 | isp { | |
| 49 | compatible = "nvidia,tegra20-isp"; | |
| 50 | reg = <0x54100000 0x00040000>; | |
| 51 | interrupts = <0 71 0x04>; | |
| 8d8b43da | 52 | clocks = <&tegra_car 23>; |
| ed821f07 TR |
53 | }; |
| 54 | ||
| 55 | gr2d { | |
| 56 | compatible = "nvidia,tegra20-gr2d"; | |
| 57 | reg = <0x54140000 0x00040000>; | |
| 58 | interrupts = <0 72 0x04>; | |
| 8d8b43da | 59 | clocks = <&tegra_car 21>; |
| ed821f07 TR |
60 | }; |
| 61 | ||
| 62 | gr3d { | |
| 63 | compatible = "nvidia,tegra20-gr3d"; | |
| 64 | reg = <0x54180000 0x00040000>; | |
| 8d8b43da | 65 | clocks = <&tegra_car 24>; |
| ed821f07 TR |
66 | }; |
| 67 | ||
| 68 | dc@54200000 { | |
| 69 | compatible = "nvidia,tegra20-dc"; | |
| 70 | reg = <0x54200000 0x00040000>; | |
| 71 | interrupts = <0 73 0x04>; | |
| 8d8b43da PG |
72 | clocks = <&tegra_car 27>, <&tegra_car 121>; |
| 73 | clock-names = "disp1", "parent"; | |
| ed821f07 TR |
74 | |
| 75 | rgb { | |
| 76 | status = "disabled"; | |
| 77 | }; | |
| 78 | }; | |
| 79 | ||
| 80 | dc@54240000 { | |
| 81 | compatible = "nvidia,tegra20-dc"; | |
| 82 | reg = <0x54240000 0x00040000>; | |
| 83 | interrupts = <0 74 0x04>; | |
| 8d8b43da PG |
84 | clocks = <&tegra_car 26>, <&tegra_car 121>; |
| 85 | clock-names = "disp2", "parent"; | |
| ed821f07 TR |
86 | |
| 87 | rgb { | |
| 88 | status = "disabled"; | |
| 89 | }; | |
| 90 | }; | |
| 91 | ||
| 92 | hdmi { | |
| 93 | compatible = "nvidia,tegra20-hdmi"; | |
| 94 | reg = <0x54280000 0x00040000>; | |
| 95 | interrupts = <0 75 0x04>; | |
| 8d8b43da PG |
96 | clocks = <&tegra_car 51>, <&tegra_car 117>; |
| 97 | clock-names = "hdmi", "parent"; | |
| ed821f07 TR |
98 | status = "disabled"; |
| 99 | }; | |
| 100 | ||
| 101 | tvo { | |
| 102 | compatible = "nvidia,tegra20-tvo"; | |
| 103 | reg = <0x542c0000 0x00040000>; | |
| 104 | interrupts = <0 76 0x04>; | |
| 8d8b43da | 105 | clocks = <&tegra_car 102>; |
| ed821f07 TR |
106 | status = "disabled"; |
| 107 | }; | |
| 108 | ||
| 109 | dsi { | |
| 110 | compatible = "nvidia,tegra20-dsi"; | |
| 111 | reg = <0x54300000 0x00040000>; | |
| 8d8b43da | 112 | clocks = <&tegra_car 48>; |
| ed821f07 TR |
113 | status = "disabled"; |
| 114 | }; | |
| 115 | }; | |
| 116 | ||
| 73368ba0 SW |
117 | timer@50004600 { |
| 118 | compatible = "arm,cortex-a9-twd-timer"; | |
| 119 | reg = <0x50040600 0x20>; | |
| 120 | interrupts = <1 13 0x304>; | |
| 121 | }; | |
| 122 | ||
| f9eb26a4 | 123 | intc: interrupt-controller { |
| 0d4f7479 | 124 | compatible = "arm,cortex-a9-gic"; |
| 5ff48887 SW |
125 | reg = <0x50041000 0x1000 |
| 126 | 0x50040100 0x0100>; | |
| 2eaab06e SW |
127 | interrupt-controller; |
| 128 | #interrupt-cells = <3>; | |
| 8e267f3d GL |
129 | }; |
| 130 | ||
| bb2c1de9 SW |
131 | cache-controller { |
| 132 | compatible = "arm,pl310-cache"; | |
| 133 | reg = <0x50043000 0x1000>; | |
| 134 | arm,data-latency = <5 5 2>; | |
| 135 | arm,tag-latency = <4 4 2>; | |
| 136 | cache-unified; | |
| 137 | cache-level = <2>; | |
| 138 | }; | |
| 139 | ||
| 2f2b7fb2 SW |
140 | timer@60005000 { |
| 141 | compatible = "nvidia,tegra20-timer"; | |
| 142 | reg = <0x60005000 0x60>; | |
| 143 | interrupts = <0 0 0x04 | |
| 144 | 0 1 0x04 | |
| 145 | 0 41 0x04 | |
| 146 | 0 42 0x04>; | |
| 147 | }; | |
| 148 | ||
| 270f8ce3 SW |
149 | tegra_car: clock { |
| 150 | compatible = "nvidia,tegra20-car"; | |
| 151 | reg = <0x60006000 0x1000>; | |
| 152 | #clock-cells = <1>; | |
| 153 | }; | |
| 154 | ||
| f9eb26a4 | 155 | apbdma: dma { |
| 8051b75a SW |
156 | compatible = "nvidia,tegra20-apbdma"; |
| 157 | reg = <0x6000a000 0x1200>; | |
| 95decf84 SW |
158 | interrupts = <0 104 0x04 |
| 159 | 0 105 0x04 | |
| 160 | 0 106 0x04 | |
| 161 | 0 107 0x04 | |
| 162 | 0 108 0x04 | |
| 163 | 0 109 0x04 | |
| 164 | 0 110 0x04 | |
| 165 | 0 111 0x04 | |
| 166 | 0 112 0x04 | |
| 167 | 0 113 0x04 | |
| 168 | 0 114 0x04 | |
| 169 | 0 115 0x04 | |
| 170 | 0 116 0x04 | |
| 171 | 0 117 0x04 | |
| 172 | 0 118 0x04 | |
| 173 | 0 119 0x04>; | |
| 8d8b43da | 174 | clocks = <&tegra_car 34>; |
| 8051b75a SW |
175 | }; |
| 176 | ||
| c04abb3a SW |
177 | ahb { |
| 178 | compatible = "nvidia,tegra20-ahb"; | |
| 179 | reg = <0x6000c004 0x10c>; /* AHB Arbitration + Gizmo Controller */ | |
| 8e267f3d GL |
180 | }; |
| 181 | ||
| f9eb26a4 | 182 | gpio: gpio { |
| 8e267f3d | 183 | compatible = "nvidia,tegra20-gpio"; |
| 95decf84 SW |
184 | reg = <0x6000d000 0x1000>; |
| 185 | interrupts = <0 32 0x04 | |
| 186 | 0 33 0x04 | |
| 187 | 0 34 0x04 | |
| 188 | 0 35 0x04 | |
| 189 | 0 55 0x04 | |
| 190 | 0 87 0x04 | |
| 191 | 0 89 0x04>; | |
| 8e267f3d GL |
192 | #gpio-cells = <2>; |
| 193 | gpio-controller; | |
| 6f74dc9b SW |
194 | #interrupt-cells = <2>; |
| 195 | interrupt-controller; | |
| 8e267f3d GL |
196 | }; |
| 197 | ||
| f9eb26a4 | 198 | pinmux: pinmux { |
| f62f548c | 199 | compatible = "nvidia,tegra20-pinmux"; |
| 95decf84 SW |
200 | reg = <0x70000014 0x10 /* Tri-state registers */ |
| 201 | 0x70000080 0x20 /* Mux registers */ | |
| 202 | 0x700000a0 0x14 /* Pull-up/down registers */ | |
| 203 | 0x70000868 0xa8>; /* Pad control registers */ | |
| f62f548c SW |
204 | }; |
| 205 | ||
| c04abb3a SW |
206 | das { |
| 207 | compatible = "nvidia,tegra20-das"; | |
| 208 | reg = <0x70000c00 0x80>; | |
| 209 | }; | |
| 0698ed19 LS |
210 | |
| 211 | tegra_ac97: ac97 { | |
| 212 | compatible = "nvidia,tegra20-ac97"; | |
| 213 | reg = <0x70002000 0x200>; | |
| 214 | interrupts = <0 81 0x04>; | |
| 215 | nvidia,dma-request-selector = <&apbdma 12>; | |
| 216 | clocks = <&tegra_car 3>; | |
| 217 | status = "disabled"; | |
| 218 | }; | |
| c04abb3a SW |
219 | |
| 220 | tegra_i2s1: i2s@70002800 { | |
| 221 | compatible = "nvidia,tegra20-i2s"; | |
| 222 | reg = <0x70002800 0x200>; | |
| 223 | interrupts = <0 13 0x04>; | |
| 224 | nvidia,dma-request-selector = <&apbdma 2>; | |
| 8d8b43da | 225 | clocks = <&tegra_car 11>; |
| 223ef78d | 226 | status = "disabled"; |
| c04abb3a SW |
227 | }; |
| 228 | ||
| 229 | tegra_i2s2: i2s@70002a00 { | |
| 230 | compatible = "nvidia,tegra20-i2s"; | |
| 231 | reg = <0x70002a00 0x200>; | |
| 232 | interrupts = <0 3 0x04>; | |
| 233 | nvidia,dma-request-selector = <&apbdma 1>; | |
| 8d8b43da | 234 | clocks = <&tegra_car 18>; |
| 223ef78d | 235 | status = "disabled"; |
| c04abb3a SW |
236 | }; |
| 237 | ||
| b6551bb9 LD |
238 | /* |
| 239 | * There are two serial driver i.e. 8250 based simple serial | |
| 240 | * driver and APB DMA based serial driver for higher baudrate | |
| 241 | * and performace. To enable the 8250 based driver, the compatible | |
| 242 | * is "nvidia,tegra20-uart" and to enable the APB DMA based serial | |
| 243 | * driver, the comptible is "nvidia,tegra20-hsuart". | |
| 244 | */ | |
| 245 | uarta: serial@70006000 { | |
| 8e267f3d GL |
246 | compatible = "nvidia,tegra20-uart"; |
| 247 | reg = <0x70006000 0x40>; | |
| 248 | reg-shift = <2>; | |
| 95decf84 | 249 | interrupts = <0 36 0x04>; |
| ab343e91 | 250 | clock-frequency = <216000000>; |
| b6551bb9 | 251 | nvidia,dma-request-selector = <&apbdma 8>; |
| 8d8b43da | 252 | clocks = <&tegra_car 6>; |
| 223ef78d | 253 | status = "disabled"; |
| 8e267f3d GL |
254 | }; |
| 255 | ||
| b6551bb9 | 256 | uartb: serial@70006040 { |
| 8e267f3d GL |
257 | compatible = "nvidia,tegra20-uart"; |
| 258 | reg = <0x70006040 0x40>; | |
| 259 | reg-shift = <2>; | |
| 95decf84 | 260 | interrupts = <0 37 0x04>; |
| ab343e91 | 261 | clock-frequency = <216000000>; |
| b6551bb9 | 262 | nvidia,dma-request-selector = <&apbdma 9>; |
| 8d8b43da | 263 | clocks = <&tegra_car 96>; |
| 223ef78d | 264 | status = "disabled"; |
| 8e267f3d GL |
265 | }; |
| 266 | ||
| b6551bb9 | 267 | uartc: serial@70006200 { |
| 8e267f3d GL |
268 | compatible = "nvidia,tegra20-uart"; |
| 269 | reg = <0x70006200 0x100>; | |
| 270 | reg-shift = <2>; | |
| 95decf84 | 271 | interrupts = <0 46 0x04>; |
| ab343e91 | 272 | clock-frequency = <216000000>; |
| b6551bb9 | 273 | nvidia,dma-request-selector = <&apbdma 10>; |
| 8d8b43da | 274 | clocks = <&tegra_car 55>; |
| 223ef78d | 275 | status = "disabled"; |
| 8e267f3d GL |
276 | }; |
| 277 | ||
| b6551bb9 | 278 | uartd: serial@70006300 { |
| 8e267f3d GL |
279 | compatible = "nvidia,tegra20-uart"; |
| 280 | reg = <0x70006300 0x100>; | |
| 281 | reg-shift = <2>; | |
| 95decf84 | 282 | interrupts = <0 90 0x04>; |
| ab343e91 | 283 | clock-frequency = <216000000>; |
| b6551bb9 | 284 | nvidia,dma-request-selector = <&apbdma 19>; |
| 8d8b43da | 285 | clocks = <&tegra_car 65>; |
| 223ef78d | 286 | status = "disabled"; |
| 8e267f3d GL |
287 | }; |
| 288 | ||
| b6551bb9 | 289 | uarte: serial@70006400 { |
| 8e267f3d GL |
290 | compatible = "nvidia,tegra20-uart"; |
| 291 | reg = <0x70006400 0x100>; | |
| 292 | reg-shift = <2>; | |
| 95decf84 | 293 | interrupts = <0 91 0x04>; |
| ab343e91 | 294 | clock-frequency = <216000000>; |
| b6551bb9 | 295 | nvidia,dma-request-selector = <&apbdma 20>; |
| 8d8b43da | 296 | clocks = <&tegra_car 66>; |
| 223ef78d | 297 | status = "disabled"; |
| 8e267f3d GL |
298 | }; |
| 299 | ||
| 2b8b15da | 300 | pwm: pwm { |
| 140fd977 TR |
301 | compatible = "nvidia,tegra20-pwm"; |
| 302 | reg = <0x7000a000 0x100>; | |
| 303 | #pwm-cells = <2>; | |
| 8d8b43da | 304 | clocks = <&tegra_car 17>; |
| 140fd977 TR |
305 | }; |
| 306 | ||
| 380e04ac SW |
307 | rtc { |
| 308 | compatible = "nvidia,tegra20-rtc"; | |
| 309 | reg = <0x7000e000 0x100>; | |
| 310 | interrupts = <0 2 0x04>; | |
| 311 | }; | |
| 312 | ||
| c04abb3a | 313 | i2c@7000c000 { |
| c04abb3a SW |
314 | compatible = "nvidia,tegra20-i2c"; |
| 315 | reg = <0x7000c000 0x100>; | |
| 316 | interrupts = <0 38 0x04>; | |
| 2eaab06e SW |
317 | #address-cells = <1>; |
| 318 | #size-cells = <0>; | |
| 8d8b43da PG |
319 | clocks = <&tegra_car 12>, <&tegra_car 124>; |
| 320 | clock-names = "div-clk", "fast-clk"; | |
| 223ef78d | 321 | status = "disabled"; |
| 0c6700ab OJ |
322 | }; |
| 323 | ||
| fa98a114 LD |
324 | spi@7000c380 { |
| 325 | compatible = "nvidia,tegra20-sflash"; | |
| 326 | reg = <0x7000c380 0x80>; | |
| 327 | interrupts = <0 39 0x04>; | |
| 328 | nvidia,dma-request-selector = <&apbdma 11>; | |
| 329 | #address-cells = <1>; | |
| 330 | #size-cells = <0>; | |
| 8d8b43da | 331 | clocks = <&tegra_car 43>; |
| fa98a114 LD |
332 | status = "disabled"; |
| 333 | }; | |
| 334 | ||
| c04abb3a | 335 | i2c@7000c400 { |
| c04abb3a SW |
336 | compatible = "nvidia,tegra20-i2c"; |
| 337 | reg = <0x7000c400 0x100>; | |
| 338 | interrupts = <0 84 0x04>; | |
| 2eaab06e SW |
339 | #address-cells = <1>; |
| 340 | #size-cells = <0>; | |
| 8d8b43da PG |
341 | clocks = <&tegra_car 54>, <&tegra_car 124>; |
| 342 | clock-names = "div-clk", "fast-clk"; | |
| 223ef78d | 343 | status = "disabled"; |
| 8e267f3d GL |
344 | }; |
| 345 | ||
| c04abb3a | 346 | i2c@7000c500 { |
| c04abb3a SW |
347 | compatible = "nvidia,tegra20-i2c"; |
| 348 | reg = <0x7000c500 0x100>; | |
| 349 | interrupts = <0 92 0x04>; | |
| 2eaab06e SW |
350 | #address-cells = <1>; |
| 351 | #size-cells = <0>; | |
| 8d8b43da PG |
352 | clocks = <&tegra_car 67>, <&tegra_car 124>; |
| 353 | clock-names = "div-clk", "fast-clk"; | |
| 223ef78d | 354 | status = "disabled"; |
| 8e267f3d GL |
355 | }; |
| 356 | ||
| c04abb3a | 357 | i2c@7000d000 { |
| c04abb3a SW |
358 | compatible = "nvidia,tegra20-i2c-dvc"; |
| 359 | reg = <0x7000d000 0x200>; | |
| 360 | interrupts = <0 53 0x04>; | |
| 2eaab06e SW |
361 | #address-cells = <1>; |
| 362 | #size-cells = <0>; | |
| 8d8b43da PG |
363 | clocks = <&tegra_car 47>, <&tegra_car 124>; |
| 364 | clock-names = "div-clk", "fast-clk"; | |
| 223ef78d | 365 | status = "disabled"; |
| 8e267f3d GL |
366 | }; |
| 367 | ||
| a86b0db3 LD |
368 | spi@7000d400 { |
| 369 | compatible = "nvidia,tegra20-slink"; | |
| 370 | reg = <0x7000d400 0x200>; | |
| 371 | interrupts = <0 59 0x04>; | |
| 372 | nvidia,dma-request-selector = <&apbdma 15>; | |
| 373 | #address-cells = <1>; | |
| 374 | #size-cells = <0>; | |
| 8d8b43da | 375 | clocks = <&tegra_car 41>; |
| a86b0db3 LD |
376 | status = "disabled"; |
| 377 | }; | |
| 378 | ||
| 379 | spi@7000d600 { | |
| 380 | compatible = "nvidia,tegra20-slink"; | |
| 381 | reg = <0x7000d600 0x200>; | |
| 382 | interrupts = <0 82 0x04>; | |
| 383 | nvidia,dma-request-selector = <&apbdma 16>; | |
| 384 | #address-cells = <1>; | |
| 385 | #size-cells = <0>; | |
| 8d8b43da | 386 | clocks = <&tegra_car 44>; |
| a86b0db3 LD |
387 | status = "disabled"; |
| 388 | }; | |
| 389 | ||
| 390 | spi@7000d800 { | |
| 391 | compatible = "nvidia,tegra20-slink"; | |
| 392 | reg = <0x7000d480 0x200>; | |
| 393 | interrupts = <0 83 0x04>; | |
| 394 | nvidia,dma-request-selector = <&apbdma 17>; | |
| 395 | #address-cells = <1>; | |
| 396 | #size-cells = <0>; | |
| 8d8b43da | 397 | clocks = <&tegra_car 46>; |
| a86b0db3 LD |
398 | status = "disabled"; |
| 399 | }; | |
| 400 | ||
| 401 | spi@7000da00 { | |
| 402 | compatible = "nvidia,tegra20-slink"; | |
| 403 | reg = <0x7000da00 0x200>; | |
| 404 | interrupts = <0 93 0x04>; | |
| 405 | nvidia,dma-request-selector = <&apbdma 18>; | |
| 406 | #address-cells = <1>; | |
| 407 | #size-cells = <0>; | |
| 8d8b43da | 408 | clocks = <&tegra_car 68>; |
| a86b0db3 LD |
409 | status = "disabled"; |
| 410 | }; | |
| 411 | ||
| 699ed4b9 LD |
412 | kbc { |
| 413 | compatible = "nvidia,tegra20-kbc"; | |
| 414 | reg = <0x7000e200 0x100>; | |
| 415 | interrupts = <0 85 0x04>; | |
| 416 | clocks = <&tegra_car 36>; | |
| 417 | status = "disabled"; | |
| 418 | }; | |
| 419 | ||
| c04abb3a SW |
420 | pmc { |
| 421 | compatible = "nvidia,tegra20-pmc"; | |
| 422 | reg = <0x7000e400 0x400>; | |
| 423 | }; | |
| 424 | ||
| bbfc33bd | 425 | memory-controller@7000f000 { |
| c04abb3a SW |
426 | compatible = "nvidia,tegra20-mc"; |
| 427 | reg = <0x7000f000 0x024 | |
| 428 | 0x7000f03c 0x3c4>; | |
| 429 | interrupts = <0 77 0x04>; | |
| 430 | }; | |
| 431 | ||
| 432 | gart { | |
| 433 | compatible = "nvidia,tegra20-gart"; | |
| 434 | reg = <0x7000f024 0x00000018 /* controller registers */ | |
| 435 | 0x58000000 0x02000000>; /* GART aperture */ | |
| 436 | }; | |
| 437 | ||
| bbfc33bd | 438 | memory-controller@7000f400 { |
| c04abb3a SW |
439 | compatible = "nvidia,tegra20-emc"; |
| 440 | reg = <0x7000f400 0x200>; | |
| 2eaab06e SW |
441 | #address-cells = <1>; |
| 442 | #size-cells = <0>; | |
| 8e267f3d | 443 | }; |
| c27317c0 | 444 | |
| e374b65c VB |
445 | phy1: usb-phy@c5000400 { |
| 446 | compatible = "nvidia,tegra20-usb-phy"; | |
| 447 | reg = <0xc5000400 0x3c00>; | |
| 448 | phy_type = "utmi"; | |
| 449 | nvidia,has-legacy-mode; | |
| 540fc9d9 SW |
450 | clocks = <&tegra_car 22>, <&tegra_car 127>; |
| 451 | clock-names = "phy", "pll_u"; | |
| e374b65c VB |
452 | }; |
| 453 | ||
| 454 | phy2: usb-phy@c5004400 { | |
| 455 | compatible = "nvidia,tegra20-usb-phy"; | |
| 456 | reg = <0xc5004400 0x3c00>; | |
| 457 | phy_type = "ulpi"; | |
| 540fc9d9 SW |
458 | clocks = <&tegra_car 94>, <&tegra_car 127>; |
| 459 | clock-names = "phy", "pll_u"; | |
| e374b65c VB |
460 | }; |
| 461 | ||
| 462 | phy3: usb-phy@c5008400 { | |
| 463 | compatible = "nvidia,tegra20-usb-phy"; | |
| 464 | reg = <0xc5008400 0x3C00>; | |
| 465 | phy_type = "utmi"; | |
| 540fc9d9 SW |
466 | clocks = <&tegra_car 22>, <&tegra_car 127>; |
| 467 | clock-names = "phy", "pll_u"; | |
| e374b65c VB |
468 | }; |
| 469 | ||
| c27317c0 OJ |
470 | usb@c5000000 { |
| 471 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
| 472 | reg = <0xc5000000 0x4000>; | |
| 95decf84 | 473 | interrupts = <0 20 0x04>; |
| c27317c0 | 474 | phy_type = "utmi"; |
| ba202f15 | 475 | nvidia,has-legacy-mode; |
| 8d8b43da | 476 | clocks = <&tegra_car 22>; |
| b4e07478 | 477 | nvidia,needs-double-reset; |
| e374b65c | 478 | nvidia,phy = <&phy1>; |
| 223ef78d | 479 | status = "disabled"; |
| c27317c0 OJ |
480 | }; |
| 481 | ||
| 482 | usb@c5004000 { | |
| 483 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
| 484 | reg = <0xc5004000 0x4000>; | |
| 95decf84 | 485 | interrupts = <0 21 0x04>; |
| c27317c0 | 486 | phy_type = "ulpi"; |
| 8d8b43da | 487 | clocks = <&tegra_car 58>; |
| e374b65c | 488 | nvidia,phy = <&phy2>; |
| 223ef78d | 489 | status = "disabled"; |
| c27317c0 OJ |
490 | }; |
| 491 | ||
| 492 | usb@c5008000 { | |
| 493 | compatible = "nvidia,tegra20-ehci", "usb-ehci"; | |
| 494 | reg = <0xc5008000 0x4000>; | |
| 95decf84 | 495 | interrupts = <0 97 0x04>; |
| c27317c0 | 496 | phy_type = "utmi"; |
| 8d8b43da | 497 | clocks = <&tegra_car 59>; |
| e374b65c | 498 | nvidia,phy = <&phy3>; |
| 223ef78d | 499 | status = "disabled"; |
| c27317c0 | 500 | }; |
| 7868a9bc | 501 | |
| c04abb3a SW |
502 | sdhci@c8000000 { |
| 503 | compatible = "nvidia,tegra20-sdhci"; | |
| 504 | reg = <0xc8000000 0x200>; | |
| 505 | interrupts = <0 14 0x04>; | |
| 8d8b43da | 506 | clocks = <&tegra_car 14>; |
| 223ef78d | 507 | status = "disabled"; |
| 7868a9bc | 508 | }; |
| 4a82f2b3 | 509 | |
| c04abb3a SW |
510 | sdhci@c8000200 { |
| 511 | compatible = "nvidia,tegra20-sdhci"; | |
| 512 | reg = <0xc8000200 0x200>; | |
| 513 | interrupts = <0 15 0x04>; | |
| 8d8b43da | 514 | clocks = <&tegra_car 9>; |
| 223ef78d | 515 | status = "disabled"; |
| 4a82f2b3 | 516 | }; |
| 6a943e0e | 517 | |
| c04abb3a SW |
518 | sdhci@c8000400 { |
| 519 | compatible = "nvidia,tegra20-sdhci"; | |
| 520 | reg = <0xc8000400 0x200>; | |
| 521 | interrupts = <0 19 0x04>; | |
| 8d8b43da | 522 | clocks = <&tegra_car 69>; |
| 223ef78d | 523 | status = "disabled"; |
| c04abb3a SW |
524 | }; |
| 525 | ||
| 526 | sdhci@c8000600 { | |
| 527 | compatible = "nvidia,tegra20-sdhci"; | |
| 528 | reg = <0xc8000600 0x200>; | |
| 529 | interrupts = <0 31 0x04>; | |
| 8d8b43da | 530 | clocks = <&tegra_car 15>; |
| 223ef78d | 531 | status = "disabled"; |
| c04abb3a SW |
532 | }; |
| 533 | ||
| 4dd2bd37 HD |
534 | cpus { |
| 535 | #address-cells = <1>; | |
| 536 | #size-cells = <0>; | |
| 537 | ||
| 538 | cpu@0 { | |
| 539 | device_type = "cpu"; | |
| 540 | compatible = "arm,cortex-a9"; | |
| 541 | reg = <0>; | |
| 542 | }; | |
| 543 | ||
| 544 | cpu@1 { | |
| 545 | device_type = "cpu"; | |
| 546 | compatible = "arm,cortex-a9"; | |
| 547 | reg = <1>; | |
| 548 | }; | |
| 549 | }; | |
| 550 | ||
| c04abb3a SW |
551 | pmu { |
| 552 | compatible = "arm,cortex-a9-pmu"; | |
| 553 | interrupts = <0 56 0x04 | |
| 554 | 0 57 0x04>; | |
| 6a943e0e | 555 | }; |
| 8e267f3d | 556 | }; |