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Merge tag 'nfs-for-4.8-1' of git://git.linux-nfs.org/projects/trondmy/linux-nfs
[deliverable/linux.git] / arch / arm / boot / dts / tegra30-cardhu.dtsi
CommitLineData
5780c206 1#include <dt-bindings/input/input.h>
1bd0bd49 2#include "tegra30.dtsi"
64c4e9f8 3
640a7af5
LD		 4/**
5 * This file contains common DT entry for all fab version of Cardhu.
6 * There is multiple fab version of Cardhu starting from A01 to A07.
7 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
8 * A02 will have different sets of GPIOs for fixed regulator compare to
9 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
10 * compatible with fab version A04. Based on Cardhu fab version, the
11 * related dts file need to be chosen like for Cardhu fab version A02,
12 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
13 * tegra30-cardhu-a04.dts.
14 * The identification of board is done in two ways, by looking the sticker
15 * on PCB and by reading board id eeprom.
db374069 16 * The sticker will have number like 600-81291-1000-002 C.3. In this 4th
640a7af5
LD		 17 * number is the fab version like here it is 002 and hence fab version A02.
18 * The (downstream internal) U-Boot of Cardhu display the board-id as
19 * follows:
20 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
21 * In this Fab version is 02 i.e. A02.
22 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
23 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
24 * wide.
25 */
26
64c4e9f8
PDS		 27/ {
28 model = "NVIDIA Tegra30 Cardhu evaluation board";
29 compatible = "nvidia,cardhu", "nvidia,tegra30";
30
553c0a20 31 aliases {
763fbff2 32 rtc0 = "/i2c@7000d000/tps65911@2d";
553c0a20 33 rtc1 = "/rtc@7000e000";
c4574aa0
OJ		 34 serial0 = &uarta;
35 serial1 = &uartc;
553c0a20
SW		 36 };
37
f5bbb327
JH		 38 chosen {
39 stdout-path = "serial0:115200n8";
40 };
41
64c4e9f8 42 memory {
95decf84 43 reg = <0x80000000 0x40000000>;
64c4e9f8
PDS		 44 };
45
58ecb23f 46 pcie-controller@00003000 {
89e7ada4 47 status = "okay";
cca8614d
TR		 48
49 /* AVDD_PEXA and VDD_PEXA inputs are grounded on Cardhu. */
50 avdd-pexb-supply = <&ldo1_reg>;
51 vdd-pexb-supply = <&ldo1_reg>;
52 avdd-pex-pll-supply = <&ldo1_reg>;
53 hvdd-pex-supply = <&pex_hvdd_3v3_reg>;
54 vddio-pex-ctl-supply = <&sys_3v3_reg>;
55 avdd-plle-supply = <&ldo2_reg>;
56
89e7ada4
JA		 57 pci@1,0 {
58 nvidia,num-lanes = <4>;
59 };
60
61 pci@2,0 {
62 nvidia,num-lanes = <1>;
63 };
64
65 pci@3,0 {
66 status = "okay";
67 nvidia,num-lanes = <1>;
68 };
69 };
70
02b1fea2
TR		 71 host1x@50000000 {
72 dc@54200000 {
73 rgb {
74 status = "okay";
75
76 nvidia,panel = <&panel>;
77 };
78 };
79 };
80
58ecb23f 81 pinmux@70000868 {
e5cbeef0
SW		 82 pinctrl-names = "default";
83 pinctrl-0 = <&state_default>;
84
85 state_default: pinmux {
86 sdmmc1_clk_pz0 {
87 nvidia,pins = "sdmmc1_clk_pz0";
88 nvidia,function = "sdmmc1";
a47c662a
LD		 89 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
90 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0
SW		 91 };
92 sdmmc1_cmd_pz1 {
93 nvidia,pins = "sdmmc1_cmd_pz1",
94 "sdmmc1_dat0_py7",
95 "sdmmc1_dat1_py6",
96 "sdmmc1_dat2_py5",
97 "sdmmc1_dat3_py4";
98 nvidia,function = "sdmmc1";
a47c662a
LD		 99 nvidia,pull = <TEGRA_PIN_PULL_UP>;
100 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0 101 };
6fb11131
WN		 102 sdmmc3_clk_pa6 {
103 nvidia,pins = "sdmmc3_clk_pa6";
104 nvidia,function = "sdmmc3";
a47c662a
LD		 105 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
106 nvidia,tristate = <TEGRA_PIN_DISABLE>;
6fb11131
WN		 107 };
108 sdmmc3_cmd_pa7 {
109 nvidia,pins = "sdmmc3_cmd_pa7",
110 "sdmmc3_dat0_pb7",
111 "sdmmc3_dat1_pb6",
112 "sdmmc3_dat2_pb5",
113 "sdmmc3_dat3_pb4";
114 nvidia,function = "sdmmc3";
a47c662a
LD		 115 nvidia,pull = <TEGRA_PIN_PULL_UP>;
116 nvidia,tristate = <TEGRA_PIN_DISABLE>;
6fb11131 117 };
e5cbeef0
SW		 118 sdmmc4_clk_pcc4 {
119 nvidia,pins = "sdmmc4_clk_pcc4",
120 "sdmmc4_rst_n_pcc3";
121 nvidia,function = "sdmmc4";
a47c662a
LD		 122 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
123 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0
SW		 124 };
125 sdmmc4_dat0_paa0 {
126 nvidia,pins = "sdmmc4_dat0_paa0",
127 "sdmmc4_dat1_paa1",
128 "sdmmc4_dat2_paa2",
129 "sdmmc4_dat3_paa3",
130 "sdmmc4_dat4_paa4",
131 "sdmmc4_dat5_paa5",
132 "sdmmc4_dat6_paa6",
133 "sdmmc4_dat7_paa7";
134 nvidia,function = "sdmmc4";
a47c662a
LD		 135 nvidia,pull = <TEGRA_PIN_PULL_UP>;
136 nvidia,tristate = <TEGRA_PIN_DISABLE>;
e5cbeef0 137 };
8c6a3852
SW		 138 dap2_fs_pa2 {
139 nvidia,pins = "dap2_fs_pa2",
140 "dap2_sclk_pa3",
141 "dap2_din_pa4",
142 "dap2_dout_pa5";
143 nvidia,function = "i2s1";
a47c662a
LD		 144 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
145 nvidia,tristate = <TEGRA_PIN_DISABLE>;
8c6a3852 146 };
6fb11131
WN		 147 sdio3 {
148 nvidia,pins = "drive_sdio3";
a47c662a
LD		 149 nvidia,high-speed-mode = <TEGRA_PIN_DISABLE>;
150 nvidia,schmitt = <TEGRA_PIN_DISABLE>;
6fb11131
WN		 151 nvidia,pull-down-strength = <46>;
152 nvidia,pull-up-strength = <42>;
a47c662a
LD		 153 nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FAST>;
154 nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FAST>;
6fb11131 155 };
ecfd6c7f
LD		 156 uart3_txd_pw6 {
157 nvidia,pins = "uart3_txd_pw6",
158 "uart3_cts_n_pa1",
159 "uart3_rts_n_pc0",
160 "uart3_rxd_pw7";
161 nvidia,function = "uartc";
a47c662a
LD		 162 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
163 nvidia,tristate = <TEGRA_PIN_DISABLE>;
ecfd6c7f 164 };
e5cbeef0
SW		 165 };
166 };
167
64c4e9f8 168 serial@70006000 {
2a5fdc9a 169 status = "okay";
64c4e9f8
PDS		 170 };
171
ecfd6c7f
LD		 172 serial@70006200 {
173 compatible = "nvidia,tegra30-hsuart";
174 status = "okay";
ecfd6c7f
LD		 175 };
176
02b1fea2
TR		 177 pwm@7000a000 {
178 status = "okay";
179 };
180
181 panelddc: i2c@7000c000 {
2a5fdc9a 182 status = "okay";
64c4e9f8
PDS		 183 clock-frequency = <100000>;
184 };
185
186 i2c@7000c400 {
2a5fdc9a 187 status = "okay";
64c4e9f8
PDS		 188 clock-frequency = <100000>;
189 };
190
191 i2c@7000c500 {
2a5fdc9a 192 status = "okay";
64c4e9f8 193 clock-frequency = <100000>;
b46b0b54
LD		 194
195 /* ALS and Proximity sensor */
196 isl29028@44 {
62981239 197 compatible = "isil,isl29028";
b46b0b54
LD		 198 reg = <0x44>;
199 interrupt-parent = <&gpio>;
6cecf916 200 interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
b46b0b54 201 };
40431d16
BW		 202
203 i2cmux@70 {
204 compatible = "nxp,pca9546";
205 #address-cells = <1>;
206 #size-cells = <0>;
207 reg = <0x70>;
208 };
64c4e9f8
PDS		 209 };
210
211 i2c@7000c700 {
2a5fdc9a 212 status = "okay";
64c4e9f8
PDS		 213 clock-frequency = <100000>;
214 };
215
216 i2c@7000d000 {
2a5fdc9a 217 status = "okay";
64c4e9f8 218 clock-frequency = <100000>;
8c6a3852
SW		 219
220 wm8903: wm8903@1a {
221 compatible = "wlf,wm8903";
222 reg = <0x1a>;
223 interrupt-parent = <&gpio>;
6cecf916 224 interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
8c6a3852
SW		 225
226 gpio-controller;
227 #gpio-cells = <2>;
228
229 micdet-cfg = <0>;
230 micdet-delay = <100>;
231 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
232 };
331da58c 233
167e6279
LD		 234 pmic: tps65911@2d {
235 compatible = "ti,tps65911";
236 reg = <0x2d>;
237
6cecf916 238 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
167e6279
LD		 239 #interrupt-cells = <2>;
240 interrupt-controller;
241
44b12ef7
SW		 242 ti,system-power-controller;
243
167e6279
LD		 244 #gpio-cells = <2>;
245 gpio-controller;
246
247 vcc1-supply = <&vdd_ac_bat_reg>;
248 vcc2-supply = <&vdd_ac_bat_reg>;
249 vcc3-supply = <&vio_reg>;
fa4a9252 250 vcc4-supply = <&vdd_5v0_reg>;
167e6279
LD		 251 vcc5-supply = <&vdd_ac_bat_reg>;
252 vcc6-supply = <&vdd2_reg>;
253 vcc7-supply = <&vdd_ac_bat_reg>;
254 vccio-supply = <&vdd_ac_bat_reg>;
255
256 regulators {
b9c665d7 257 vdd1_reg: vdd1 {
167e6279
LD		 258 regulator-name = "vddio_ddr_1v2";
259 regulator-min-microvolt = <1200000>;
260 regulator-max-microvolt = <1200000>;
261 regulator-always-on;
262 };
263
b9c665d7 264 vdd2_reg: vdd2 {
167e6279
LD		 265 regulator-name = "vdd_1v5_gen";
266 regulator-min-microvolt = <1500000>;
267 regulator-max-microvolt = <1500000>;
268 regulator-always-on;
269 };
270
b9c665d7 271 vddctrl_reg: vddctrl {
167e6279
LD		 272 regulator-name = "vdd_cpu,vdd_sys";
273 regulator-min-microvolt = <1000000>;
274 regulator-max-microvolt = <1000000>;
275 regulator-always-on;
276 };
277
b9c665d7 278 vio_reg: vio {
167e6279
LD		 279 regulator-name = "vdd_1v8_gen";
280 regulator-min-microvolt = <1800000>;
281 regulator-max-microvolt = <1800000>;
282 regulator-always-on;
283 };
284
b9c665d7 285 ldo1_reg: ldo1 {
167e6279
LD		 286 regulator-name = "vdd_pexa,vdd_pexb";
287 regulator-min-microvolt = <1050000>;
288 regulator-max-microvolt = <1050000>;
289 };
290
b9c665d7 291 ldo2_reg: ldo2 {
167e6279
LD		 292 regulator-name = "vdd_sata,avdd_plle";
293 regulator-min-microvolt = <1050000>;
294 regulator-max-microvolt = <1050000>;
295 };
296
297 /* LDO3 is not connected to anything */
298
b9c665d7 299 ldo4_reg: ldo4 {
167e6279
LD		 300 regulator-name = "vdd_rtc";
301 regulator-min-microvolt = <1200000>;
302 regulator-max-microvolt = <1200000>;
303 regulator-always-on;
304 };
305
b9c665d7 306 ldo5_reg: ldo5 {
fa4a9252
LD		 307 regulator-name = "vddio_sdmmc,avdd_vdac";
308 regulator-min-microvolt = <3300000>;
309 regulator-max-microvolt = <3300000>;
310 regulator-always-on;
311 };
312
b9c665d7 313 ldo6_reg: ldo6 {
167e6279
LD		 314 regulator-name = "avdd_dsi_csi,pwrdet_mipi";
315 regulator-min-microvolt = <1200000>;
316 regulator-max-microvolt = <1200000>;
317 };
318
b9c665d7 319 ldo7_reg: ldo7 {
167e6279
LD		 320 regulator-name = "vdd_pllm,x,u,a_p_c_s";
321 regulator-min-microvolt = <1200000>;
322 regulator-max-microvolt = <1200000>;
323 regulator-always-on;
324 };
325
b9c665d7 326 ldo8_reg: ldo8 {
167e6279
LD		 327 regulator-name = "vdd_ddr_hs";
328 regulator-min-microvolt = <1000000>;
329 regulator-max-microvolt = <1000000>;
330 regulator-always-on;
331 };
332 };
333 };
74ecab27 334
7c7de6b0 335 temperature-sensor@4c {
74ecab27
WN		 336 compatible = "onnn,nct1008";
337 reg = <0x4c>;
7c7de6b0 338 vcc-supply = <&sys_3v3_reg>;
74ecab27
WN		 339 interrupt-parent = <&gpio>;
340 interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
341 };
2b8584d5 342
58ecb23f 343 tps62361@60 {
2b8584d5
SW		 344 compatible = "ti,tps62361";
345 reg = <0x60>;
346
347 regulator-name = "tps62361-vout";
348 regulator-min-microvolt = <500000>;
349 regulator-max-microvolt = <1500000>;
350 regulator-boot-on;
351 regulator-always-on;
352 ti,vsel0-state-high;
353 ti,vsel1-state-high;
354 };
64c4e9f8 355 };
850c4c8f 356
c42cb1c3
LD		 357 spi@7000da00 {
358 status = "okay";
359 spi-max-frequency = <25000000>;
360 spi-flash@1 {
361 compatible = "winbond,w25q32";
362 reg = <1>;
363 spi-max-frequency = <20000000>;
364 };
365 };
366
58ecb23f 367 pmc@7000e400 {
167e6279
LD		 368 status = "okay";
369 nvidia,invert-interrupt;
47d2d63b 370 nvidia,suspend-mode = <1>;
a44a019d
JL		 371 nvidia,cpu-pwr-good-time = <2000>;
372 nvidia,cpu-pwr-off-time = <200>;
373 nvidia,core-pwr-good-time = <3845 3845>;
374 nvidia,core-pwr-off-time = <0>;
375 nvidia,core-power-req-active-high;
376 nvidia,sys-clock-req-active-high;
167e6279
LD		 377 };
378
57899053
SW		 379 ahub@70080000 {
380 i2s@70080400 {
381 status = "okay";
382 };
383 };
384
c04abb3a 385 sdhci@78000000 {
2a5fdc9a 386 status = "okay";
3325f1bc
SW		 387 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
388 wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
389 power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
7f217794 390 bus-width = <4>;
c04abb3a
SW		 391 };
392
c04abb3a 393 sdhci@78000600 {
2a5fdc9a 394 status = "okay";
7f217794 395 bus-width = <8>;
7a2617a6 396 non-removable;
c04abb3a
SW		 397 };
398
cc34c9f7
TT		 399 usb@7d008000 {
400 status = "okay";
401 };
402
403 usb-phy@7d008000 {
404 vbus-supply = <&usb3_vbus_reg>;
405 status = "okay";
406 };
407
02b1fea2
TR		 408 backlight: backlight {
409 compatible = "pwm-backlight";
410
411 enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>;
412 power-supply = <&vdd_bl_reg>;
413 pwms = <&pwm 0 5000000>;
414
415 brightness-levels = <0 4 8 16 32 64 128 255>;
416 default-brightness-level = <6>;
417 };
418
7021d122
JL		 419 clocks {
420 compatible = "simple-bus";
421 #address-cells = <1>;
422 #size-cells = <0>;
423
58ecb23f 424 clk32k_in: clock@0 {
7021d122
JL		 425 compatible = "fixed-clock";
426 reg=<0>;
427 #clock-cells = <0>;
428 clock-frequency = <32768>;
429 };
430 };
431
02b1fea2
TR		 432 panel: panel {
433 compatible = "chunghwa,claa101wb01", "simple-panel";
434 ddc-i2c-bus = <&panelddc>;
435
436 power-supply = <&vdd_pnl1_reg>;
437 enable-gpios = <&gpio TEGRA_GPIO(L, 2) GPIO_ACTIVE_HIGH>;
438
439 backlight = <&backlight>;
440 };
441
167e6279
LD		 442 regulators {
443 compatible = "simple-bus";
444 #address-cells = <1>;
445 #size-cells = <0>;
446
447 vdd_ac_bat_reg: regulator@0 {
448 compatible = "regulator-fixed";
449 reg = <0>;
450 regulator-name = "vdd_ac_bat";
451 regulator-min-microvolt = <5000000>;
452 regulator-max-microvolt = <5000000>;
453 regulator-always-on;
454 };
fa4a9252
LD		 455
456 cam_1v8_reg: regulator@1 {
457 compatible = "regulator-fixed";
458 reg = <1>;
459 regulator-name = "cam_1v8";
460 regulator-min-microvolt = <1800000>;
461 regulator-max-microvolt = <1800000>;
462 enable-active-high;
3325f1bc 463 gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 464 vin-supply = <&vio_reg>;
465 };
466
467 cp_5v_reg: regulator@2 {
468 compatible = "regulator-fixed";
469 reg = <2>;
470 regulator-name = "cp_5v";
471 regulator-min-microvolt = <5000000>;
472 regulator-max-microvolt = <5000000>;
473 regulator-boot-on;
474 regulator-always-on;
475 enable-active-high;
3325f1bc 476 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 477 };
478
479 emmc_3v3_reg: regulator@3 {
480 compatible = "regulator-fixed";
481 reg = <3>;
482 regulator-name = "emmc_3v3";
483 regulator-min-microvolt = <3300000>;
484 regulator-max-microvolt = <3300000>;
485 regulator-always-on;
486 regulator-boot-on;
487 enable-active-high;
3325f1bc 488 gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 489 vin-supply = <&sys_3v3_reg>;
490 };
491
492 modem_3v3_reg: regulator@4 {
493 compatible = "regulator-fixed";
494 reg = <4>;
495 regulator-name = "modem_3v3";
496 regulator-min-microvolt = <3300000>;
497 regulator-max-microvolt = <3300000>;
498 enable-active-high;
3325f1bc 499 gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 500 };
501
502 pex_hvdd_3v3_reg: regulator@5 {
503 compatible = "regulator-fixed";
504 reg = <5>;
505 regulator-name = "pex_hvdd_3v3";
506 regulator-min-microvolt = <3300000>;
507 regulator-max-microvolt = <3300000>;
508 enable-active-high;
3325f1bc 509 gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 510 vin-supply = <&sys_3v3_reg>;
511 };
512
513 vdd_cam1_ldo_reg: regulator@6 {
514 compatible = "regulator-fixed";
515 reg = <6>;
516 regulator-name = "vdd_cam1_ldo";
517 regulator-min-microvolt = <2800000>;
518 regulator-max-microvolt = <2800000>;
519 enable-active-high;
3325f1bc 520 gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 521 vin-supply = <&sys_3v3_reg>;
522 };
523
524 vdd_cam2_ldo_reg: regulator@7 {
525 compatible = "regulator-fixed";
526 reg = <7>;
527 regulator-name = "vdd_cam2_ldo";
528 regulator-min-microvolt = <2800000>;
529 regulator-max-microvolt = <2800000>;
530 enable-active-high;
3325f1bc 531 gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 532 vin-supply = <&sys_3v3_reg>;
533 };
534
535 vdd_cam3_ldo_reg: regulator@8 {
536 compatible = "regulator-fixed";
537 reg = <8>;
538 regulator-name = "vdd_cam3_ldo";
539 regulator-min-microvolt = <3300000>;
540 regulator-max-microvolt = <3300000>;
541 enable-active-high;
3325f1bc 542 gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 543 vin-supply = <&sys_3v3_reg>;
544 };
545
546 vdd_com_reg: regulator@9 {
547 compatible = "regulator-fixed";
548 reg = <9>;
549 regulator-name = "vdd_com";
550 regulator-min-microvolt = <3300000>;
551 regulator-max-microvolt = <3300000>;
6fb11131
WN		 552 regulator-always-on;
553 regulator-boot-on;
fa4a9252 554 enable-active-high;
3325f1bc 555 gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 556 vin-supply = <&sys_3v3_reg>;
557 };
558
559 vdd_fuse_3v3_reg: regulator@10 {
560 compatible = "regulator-fixed";
561 reg = <10>;
562 regulator-name = "vdd_fuse_3v3";
563 regulator-min-microvolt = <3300000>;
564 regulator-max-microvolt = <3300000>;
565 enable-active-high;
3325f1bc 566 gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 567 vin-supply = <&sys_3v3_reg>;
568 };
569
570 vdd_pnl1_reg: regulator@11 {
571 compatible = "regulator-fixed";
572 reg = <11>;
573 regulator-name = "vdd_pnl1";
574 regulator-min-microvolt = <3300000>;
575 regulator-max-microvolt = <3300000>;
576 regulator-always-on;
577 regulator-boot-on;
578 enable-active-high;
3325f1bc 579 gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 580 vin-supply = <&sys_3v3_reg>;
581 };
582
583 vdd_vid_reg: regulator@12 {
584 compatible = "regulator-fixed";
585 reg = <12>;
586 regulator-name = "vddio_vid";
587 regulator-min-microvolt = <5000000>;
588 regulator-max-microvolt = <5000000>;
589 enable-active-high;
3325f1bc 590 gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
fa4a9252
LD		 591 gpio-open-drain;
592 vin-supply = <&vdd_5v0_reg>;
593 };
167e6279
LD		 594 };
595
8c6a3852
SW		 596 sound {
597 compatible = "nvidia,tegra-audio-wm8903-cardhu",
598 "nvidia,tegra-audio-wm8903";
599 nvidia,model = "NVIDIA Tegra Cardhu";
600
601 nvidia,audio-routing =
602 "Headphone Jack", "HPOUTR",
603 "Headphone Jack", "HPOUTL",
604 "Int Spk", "ROP",
605 "Int Spk", "RON",
606 "Int Spk", "LOP",
607 "Int Spk", "LON",
608 "Mic Jack", "MICBIAS",
609 "IN1L", "Mic Jack";
610
611 nvidia,i2s-controller = <&tegra_i2s1>;
612 nvidia,audio-codec = <&wm8903>;
613
3325f1bc
SW		 614 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
615 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
616 GPIO_ACTIVE_HIGH>;
f9cd2b3b 617
05849c93
HD		 618 clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
619 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
620 <&tegra_car TEGRA30_CLK_EXTERN1>;
f9cd2b3b 621 clock-names = "pll_a", "pll_a_out0", "mclk";
8c6a3852 622 };
5780c206
TR		 623
624 gpio-keys {
625 compatible = "gpio-keys";
626
627 power {
628 label = "Power";
629 interrupt-parent = <&pmic>;
630 interrupts = <2 0>;
631 linux,code = <KEY_POWER>;
632 debounce-interval = <100>;
d1c04d30 633 wakeup-source;
5780c206
TR		 634 };
635
636 volume-down {
637 label = "Volume Down";
638 gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_LOW>;
639 linux,code = <KEY_VOLUMEDOWN>;
640 debounce-interval = <10>;
641 };
642
643 volume-up {
644 label = "Volume Up";
645 gpios = <&gpio TEGRA_GPIO(R, 1) GPIO_ACTIVE_LOW>;
646 linux,code = <KEY_VOLUMEUP>;
647 debounce-interval = <10>;
648 };
649 };
64c4e9f8 650};
Linux kernel - Deliverables
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