[deliverable/linux.git] / arch / arm / boot / dts / tegra30-cardhu.dtsi

/include/ "tegra30.dtsi"

/**
 * This file contains common DT entry for all fab version of Cardhu.
 * There is multiple fab version of Cardhu starting from A01 to A07.
 * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
 * A02 will have different sets of GPIOs for fixed regulator compare to
 * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
 * compatible with fab version A04. Based on Cardhu fab version, the
 * related dts file need to be chosen like for Cardhu fab version A02,
 * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
 * tegra30-cardhu-a04.dts.
 * The identification of board is done in two ways, by looking the sticker
 * on PCB and by reading board id eeprom.
 * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
 * number is the fab version like here it is 002 and hence fab version A02.
 * The (downstream internal) U-Boot of Cardhu display the board-id as
 * follows:
 * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
 * In this Fab version is 02 i.e. A02.
 * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
 * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
 * wide.
 */

/ {
	model = "NVIDIA Tegra30 Cardhu evaluation board";
	compatible = "nvidia,cardhu", "nvidia,tegra30";

	memory {
		reg = <0x80000000 0x40000000>;
	};

	pinmux {
		pinctrl-names = "default";
		pinctrl-0 = <&state_default>;

		state_default: pinmux {
			sdmmc1_clk_pz0 {
				nvidia,pins = "sdmmc1_clk_pz0";
				nvidia,function = "sdmmc1";
				nvidia,pull = <0>;
				nvidia,tristate = <0>;
			};
			sdmmc1_cmd_pz1 {
				nvidia,pins =	"sdmmc1_cmd_pz1",
						"sdmmc1_dat0_py7",
						"sdmmc1_dat1_py6",
						"sdmmc1_dat2_py5",
						"sdmmc1_dat3_py4";
				nvidia,function = "sdmmc1";
				nvidia,pull = <2>;
				nvidia,tristate = <0>;
			};
			sdmmc3_clk_pa6 {
				nvidia,pins = "sdmmc3_clk_pa6";
				nvidia,function = "sdmmc3";
				nvidia,pull = <0>;
				nvidia,tristate = <0>;
			};
			sdmmc3_cmd_pa7 {
				nvidia,pins =	"sdmmc3_cmd_pa7",
						"sdmmc3_dat0_pb7",
						"sdmmc3_dat1_pb6",
						"sdmmc3_dat2_pb5",
						"sdmmc3_dat3_pb4";
				nvidia,function = "sdmmc3";
				nvidia,pull = <2>;
				nvidia,tristate = <0>;
			};
			sdmmc4_clk_pcc4 {
				nvidia,pins =	"sdmmc4_clk_pcc4",
						"sdmmc4_rst_n_pcc3";
				nvidia,function = "sdmmc4";
				nvidia,pull = <0>;
				nvidia,tristate = <0>;
			};
			sdmmc4_dat0_paa0 {
				nvidia,pins =	"sdmmc4_dat0_paa0",
						"sdmmc4_dat1_paa1",
						"sdmmc4_dat2_paa2",
						"sdmmc4_dat3_paa3",
						"sdmmc4_dat4_paa4",
						"sdmmc4_dat5_paa5",
						"sdmmc4_dat6_paa6",
						"sdmmc4_dat7_paa7";
				nvidia,function = "sdmmc4";
				nvidia,pull = <2>;
				nvidia,tristate = <0>;
			};
			dap2_fs_pa2 {
				nvidia,pins =	"dap2_fs_pa2",
						"dap2_sclk_pa3",
						"dap2_din_pa4",
						"dap2_dout_pa5";
				nvidia,function = "i2s1";
				nvidia,pull = <0>;
				nvidia,tristate = <0>;
			};
			sdio3 {
				nvidia,pins = "drive_sdio3";
				nvidia,high-speed-mode = <0>;
				nvidia,schmitt = <0>;
				nvidia,pull-down-strength = <46>;
				nvidia,pull-up-strength = <42>;
				nvidia,slew-rate-rising = <1>;
				nvidia,slew-rate-falling = <1>;
			};
			uart3_txd_pw6 {
				nvidia,pins =	"uart3_txd_pw6",
						"uart3_cts_n_pa1",
						"uart3_rts_n_pc0",
						"uart3_rxd_pw7";
				nvidia,function = "uartc";
				nvidia,pull = <0>;
				nvidia,tristate = <0>;
			};
		};
	};

	serial@70006000 {
		status = "okay";
	};

	serial@70006200 {
		compatible = "nvidia,tegra30-hsuart";
		status = "okay";
	};

	i2c@7000c000 {
		status = "okay";
		clock-frequency = <100000>;
	};

	i2c@7000c400 {
		status = "okay";
		clock-frequency = <100000>;
	};

	i2c@7000c500 {
		status = "okay";
		clock-frequency = <100000>;

		/* ALS and Proximity sensor */
		isl29028@44 {
			compatible = "isil,isl29028";
			reg = <0x44>;
			interrupt-parent = <&gpio>;
			interrupts = <88 0x04>; /*gpio PL0 */
		};
	};

	i2c@7000c700 {
		status = "okay";
		clock-frequency = <100000>;
	};

	i2c@7000d000 {
		status = "okay";
		clock-frequency = <100000>;

		wm8903: wm8903@1a {
			compatible = "wlf,wm8903";
			reg = <0x1a>;
			interrupt-parent = <&gpio>;
			interrupts = <179 0x04>; /* gpio PW3 */

			gpio-controller;
			#gpio-cells = <2>;

			micdet-cfg = <0>;
			micdet-delay = <100>;
			gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
		};

		tps62361 {
			compatible = "ti,tps62361";
			reg = <0x60>;

			regulator-name = "tps62361-vout";
			regulator-min-microvolt = <500000>;
			regulator-max-microvolt = <1500000>;
			regulator-boot-on;
			regulator-always-on;
			ti,vsel0-state-high;
			ti,vsel1-state-high;
		};

		pmic: tps65911@2d {
			compatible = "ti,tps65911";
			reg = <0x2d>;

			interrupts = <0 86 0x4>;
			#interrupt-cells = <2>;
			interrupt-controller;

			ti,system-power-controller;

			#gpio-cells = <2>;
			gpio-controller;

			vcc1-supply = <&vdd_ac_bat_reg>;
			vcc2-supply = <&vdd_ac_bat_reg>;
			vcc3-supply = <&vio_reg>;
			vcc4-supply = <&vdd_5v0_reg>;
			vcc5-supply = <&vdd_ac_bat_reg>;
			vcc6-supply = <&vdd2_reg>;
			vcc7-supply = <&vdd_ac_bat_reg>;
			vccio-supply = <&vdd_ac_bat_reg>;

			regulators {
				vdd1_reg: vdd1 {
					regulator-name = "vddio_ddr_1v2";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
				};

				vdd2_reg: vdd2 {
					regulator-name = "vdd_1v5_gen";
					regulator-min-microvolt = <1500000>;
					regulator-max-microvolt = <1500000>;
					regulator-always-on;
				};

				vddctrl_reg: vddctrl {
					regulator-name = "vdd_cpu,vdd_sys";
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1000000>;
					regulator-always-on;
				};

				vio_reg: vio {
					regulator-name = "vdd_1v8_gen";
					regulator-min-microvolt = <1800000>;
					regulator-max-microvolt = <1800000>;
					regulator-always-on;
				};

				ldo1_reg: ldo1 {
					regulator-name = "vdd_pexa,vdd_pexb";
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
				};

				ldo2_reg: ldo2 {
					regulator-name = "vdd_sata,avdd_plle";
					regulator-min-microvolt = <1050000>;
					regulator-max-microvolt = <1050000>;
				};

				/* LDO3 is not connected to anything */

				ldo4_reg: ldo4 {
					regulator-name = "vdd_rtc";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
				};

				ldo5_reg: ldo5 {
					regulator-name = "vddio_sdmmc,avdd_vdac";
					regulator-min-microvolt = <3300000>;
					regulator-max-microvolt = <3300000>;
					regulator-always-on;
				};

				ldo6_reg: ldo6 {
					regulator-name = "avdd_dsi_csi,pwrdet_mipi";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
				};

				ldo7_reg: ldo7 {
					regulator-name = "vdd_pllm,x,u,a_p_c_s";
					regulator-min-microvolt = <1200000>;
					regulator-max-microvolt = <1200000>;
					regulator-always-on;
				};

				ldo8_reg: ldo8 {
					regulator-name = "vdd_ddr_hs";
					regulator-min-microvolt = <1000000>;
					regulator-max-microvolt = <1000000>;
					regulator-always-on;
				};
			};
		};
	};

	spi@7000da00 {
		status = "okay";
		spi-max-frequency = <25000000>;
		spi-flash@1 {
			compatible = "winbond,w25q32";
			reg = <1>;
			spi-max-frequency = <20000000>;
		};
	};

	ahub {
		i2s@70080400 {
			status = "okay";
		};
	};

	pmc {
		status = "okay";
		nvidia,invert-interrupt;
	};

	sdhci@78000000 {
		status = "okay";
		cd-gpios = <&gpio 69 1>; /* gpio PI5 */
		wp-gpios = <&gpio 155 0>; /* gpio PT3 */
		power-gpios = <&gpio 31 0>; /* gpio PD7 */
		bus-width = <4>;
	};

	sdhci@78000600 {
		status = "okay";
		bus-width = <8>;
		non-removable;
	};

	clocks {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		clk32k_in: clock {
			compatible = "fixed-clock";
			reg=<0>;
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		vdd_ac_bat_reg: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "vdd_ac_bat";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			regulator-always-on;
		};

		cam_1v8_reg: regulator@1 {
			compatible = "regulator-fixed";
			reg = <1>;
			regulator-name = "cam_1v8";
			regulator-min-microvolt = <1800000>;
			regulator-max-microvolt = <1800000>;
			enable-active-high;
			gpio = <&gpio 220 0>; /* gpio PBB4 */
			vin-supply = <&vio_reg>;
		};

		cp_5v_reg: regulator@2 {
			compatible = "regulator-fixed";
			reg = <2>;
			regulator-name = "cp_5v";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			regulator-boot-on;
			regulator-always-on;
			enable-active-high;
			gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
		};

		emmc_3v3_reg: regulator@3 {
			compatible = "regulator-fixed";
			reg = <3>;
			regulator-name = "emmc_3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
			regulator-boot-on;
			enable-active-high;
			gpio = <&gpio 25 0>; /* gpio PD1 */
			vin-supply = <&sys_3v3_reg>;
		};

		modem_3v3_reg: regulator@4 {
			compatible = "regulator-fixed";
			reg = <4>;
			regulator-name = "modem_3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			enable-active-high;
			gpio = <&gpio 30 0>; /* gpio PD6 */
		};

		pex_hvdd_3v3_reg: regulator@5 {
			compatible = "regulator-fixed";
			reg = <5>;
			regulator-name = "pex_hvdd_3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			enable-active-high;
			gpio = <&gpio 95 0>; /* gpio PL7 */
			vin-supply = <&sys_3v3_reg>;
		};

		vdd_cam1_ldo_reg: regulator@6 {
			compatible = "regulator-fixed";
			reg = <6>;
			regulator-name = "vdd_cam1_ldo";
			regulator-min-microvolt = <2800000>;
			regulator-max-microvolt = <2800000>;
			enable-active-high;
			gpio = <&gpio 142 0>; /* gpio PR6 */
			vin-supply = <&sys_3v3_reg>;
		};

		vdd_cam2_ldo_reg: regulator@7 {
			compatible = "regulator-fixed";
			reg = <7>;
			regulator-name = "vdd_cam2_ldo";
			regulator-min-microvolt = <2800000>;
			regulator-max-microvolt = <2800000>;
			enable-active-high;
			gpio = <&gpio 143 0>; /* gpio PR7 */
			vin-supply = <&sys_3v3_reg>;
		};

		vdd_cam3_ldo_reg: regulator@8 {
			compatible = "regulator-fixed";
			reg = <8>;
			regulator-name = "vdd_cam3_ldo";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			enable-active-high;
			gpio = <&gpio 144 0>; /* gpio PS0 */
			vin-supply = <&sys_3v3_reg>;
		};

		vdd_com_reg: regulator@9 {
			compatible = "regulator-fixed";
			reg = <9>;
			regulator-name = "vdd_com";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
			regulator-boot-on;
			enable-active-high;
			gpio = <&gpio 24 0>; /* gpio PD0 */
			vin-supply = <&sys_3v3_reg>;
		};

		vdd_fuse_3v3_reg: regulator@10 {
			compatible = "regulator-fixed";
			reg = <10>;
			regulator-name = "vdd_fuse_3v3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			enable-active-high;
			gpio = <&gpio 94 0>; /* gpio PL6 */
			vin-supply = <&sys_3v3_reg>;
		};

		vdd_pnl1_reg: regulator@11 {
			compatible = "regulator-fixed";
			reg = <11>;
			regulator-name = "vdd_pnl1";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
			regulator-boot-on;
			enable-active-high;
			gpio = <&gpio 92 0>; /* gpio PL4 */
			vin-supply = <&sys_3v3_reg>;
		};

		vdd_vid_reg: regulator@12 {
			compatible = "regulator-fixed";
			reg = <12>;
			regulator-name = "vddio_vid";
			regulator-min-microvolt = <5000000>;
			regulator-max-microvolt = <5000000>;
			enable-active-high;
			gpio = <&gpio 152 0>; /* GPIO PT0 */
			gpio-open-drain;
			vin-supply = <&vdd_5v0_reg>;
		};
	};

	sound {
		compatible = "nvidia,tegra-audio-wm8903-cardhu",
			     "nvidia,tegra-audio-wm8903";
		nvidia,model = "NVIDIA Tegra Cardhu";

		nvidia,audio-routing =
			"Headphone Jack", "HPOUTR",
			"Headphone Jack", "HPOUTL",
			"Int Spk", "ROP",
			"Int Spk", "RON",
			"Int Spk", "LOP",
			"Int Spk", "LON",
			"Mic Jack", "MICBIAS",
			"IN1L", "Mic Jack";

		nvidia,i2s-controller = <&tegra_i2s1>;
		nvidia,audio-codec = <&wm8903>;

		nvidia,spkr-en-gpios = <&wm8903 2 0>;
		nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */

		clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
		clock-names = "pll_a", "pll_a_out0", "mclk";
	};
};
Commit	Line	Data
64c4e9f8 PDS	1	/include/ "tegra30.dtsi"
64c4e9f8 PDS	2
640a7af5 LD	3	/**
	4	* This file contains common DT entry for all fab version of Cardhu.
	5	* There is multiple fab version of Cardhu starting from A01 to A07.
	6	* Cardhu fab version A01 and A03 are not supported. Cardhu fab version
	7	* A02 will have different sets of GPIOs for fixed regulator compare to
	8	* Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
	9	* compatible with fab version A04. Based on Cardhu fab version, the
	10	* related dts file need to be chosen like for Cardhu fab version A02,
	11	* use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
	12	* tegra30-cardhu-a04.dts.
	13	* The identification of board is done in two ways, by looking the sticker
	14	* on PCB and by reading board id eeprom.
	15	* The stciker will have number like 600-81291-1000-002 C.3. In this 4th
	16	* number is the fab version like here it is 002 and hence fab version A02.
	17	* The (downstream internal) U-Boot of Cardhu display the board-id as
	18	* follows:
	19	* BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
	20	* In this Fab version is 02 i.e. A02.
	21	* The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
	22	* The location 0x8 of this eeprom contains the Fab version. It is 1 byte
	23	* wide.
	24	*/
	25
64c4e9f8 PDS	26	/ {
	27	model = "NVIDIA Tegra30 Cardhu evaluation board";
	28	compatible = "nvidia,cardhu", "nvidia,tegra30";
	29
	30	memory {
95decf84	31	reg = <0x80000000 0x40000000>;
64c4e9f8 PDS	32	};
64c4e9f8 PDS	33
f9eb26a4	34	pinmux {
e5cbeef0 SW	35	pinctrl-names = "default";
	36	pinctrl-0 = <&state_default>;
	37
	38	state_default: pinmux {
	39	sdmmc1_clk_pz0 {
	40	nvidia,pins = "sdmmc1_clk_pz0";
	41	nvidia,function = "sdmmc1";
	42	nvidia,pull = <0>;
	43	nvidia,tristate = <0>;
	44	};
	45	sdmmc1_cmd_pz1 {
	46	nvidia,pins = "sdmmc1_cmd_pz1",
	47	"sdmmc1_dat0_py7",
	48	"sdmmc1_dat1_py6",
	49	"sdmmc1_dat2_py5",
	50	"sdmmc1_dat3_py4";
	51	nvidia,function = "sdmmc1";
	52	nvidia,pull = <2>;
	53	nvidia,tristate = <0>;
	54	};
6fb11131 WN	55	sdmmc3_clk_pa6 {
	56	nvidia,pins = "sdmmc3_clk_pa6";
	57	nvidia,function = "sdmmc3";
	58	nvidia,pull = <0>;
	59	nvidia,tristate = <0>;
	60	};
	61	sdmmc3_cmd_pa7 {
	62	nvidia,pins = "sdmmc3_cmd_pa7",
	63	"sdmmc3_dat0_pb7",
	64	"sdmmc3_dat1_pb6",
	65	"sdmmc3_dat2_pb5",
	66	"sdmmc3_dat3_pb4";
	67	nvidia,function = "sdmmc3";
	68	nvidia,pull = <2>;
	69	nvidia,tristate = <0>;
	70	};
e5cbeef0 SW	71	sdmmc4_clk_pcc4 {
	72	nvidia,pins = "sdmmc4_clk_pcc4",
	73	"sdmmc4_rst_n_pcc3";
	74	nvidia,function = "sdmmc4";
	75	nvidia,pull = <0>;
	76	nvidia,tristate = <0>;
	77	};
	78	sdmmc4_dat0_paa0 {
	79	nvidia,pins = "sdmmc4_dat0_paa0",
	80	"sdmmc4_dat1_paa1",
	81	"sdmmc4_dat2_paa2",
	82	"sdmmc4_dat3_paa3",
	83	"sdmmc4_dat4_paa4",
	84	"sdmmc4_dat5_paa5",
	85	"sdmmc4_dat6_paa6",
	86	"sdmmc4_dat7_paa7";
	87	nvidia,function = "sdmmc4";
	88	nvidia,pull = <2>;
	89	nvidia,tristate = <0>;
	90	};
8c6a3852 SW	91	dap2_fs_pa2 {
	92	nvidia,pins = "dap2_fs_pa2",
	93	"dap2_sclk_pa3",
	94	"dap2_din_pa4",
	95	"dap2_dout_pa5";
	96	nvidia,function = "i2s1";
	97	nvidia,pull = <0>;
	98	nvidia,tristate = <0>;
	99	};
6fb11131 WN	100	sdio3 {
	101	nvidia,pins = "drive_sdio3";
	102	nvidia,high-speed-mode = <0>;
	103	nvidia,schmitt = <0>;
	104	nvidia,pull-down-strength = <46>;
	105	nvidia,pull-up-strength = <42>;
	106	nvidia,slew-rate-rising = <1>;
	107	nvidia,slew-rate-falling = <1>;
	108	};
ecfd6c7f LD	109	uart3_txd_pw6 {
	110	nvidia,pins = "uart3_txd_pw6",
	111	"uart3_cts_n_pa1",
	112	"uart3_rts_n_pc0",
	113	"uart3_rxd_pw7";
	114	nvidia,function = "uartc";
	115	nvidia,pull = <0>;
	116	nvidia,tristate = <0>;
	117	};
e5cbeef0 SW	118	};
	119	};
	120
64c4e9f8	121	serial@70006000 {
2a5fdc9a	122	status = "okay";
64c4e9f8 PDS	123	};
64c4e9f8 PDS	124
ecfd6c7f LD	125	serial@70006200 {
	126	compatible = "nvidia,tegra30-hsuart";
	127	status = "okay";
ecfd6c7f LD	128	};
ecfd6c7f LD	129
64c4e9f8	130	i2c@7000c000 {
2a5fdc9a	131	status = "okay";
64c4e9f8 PDS	132	clock-frequency = <100000>;
	133	};
	134
	135	i2c@7000c400 {
2a5fdc9a	136	status = "okay";
64c4e9f8 PDS	137	clock-frequency = <100000>;
	138	};
	139
	140	i2c@7000c500 {
2a5fdc9a	141	status = "okay";
64c4e9f8	142	clock-frequency = <100000>;
b46b0b54 LD	143
	144	/* ALS and Proximity sensor */
	145	isl29028@44 {
	146	compatible = "isil,isl29028";
	147	reg = <0x44>;
	148	interrupt-parent = <&gpio>;
	149	interrupts = <88 0x04>; /gpio PL0 /
	150	};
64c4e9f8 PDS	151	};
	152
	153	i2c@7000c700 {
2a5fdc9a	154	status = "okay";
64c4e9f8 PDS	155	clock-frequency = <100000>;
	156	};
	157
	158	i2c@7000d000 {
2a5fdc9a	159	status = "okay";
64c4e9f8	160	clock-frequency = <100000>;
8c6a3852 SW	161
	162	wm8903: wm8903@1a {
	163	compatible = "wlf,wm8903";
	164	reg = <0x1a>;
	165	interrupt-parent = <&gpio>;
	166	interrupts = <179 0x04>; /* gpio PW3 */
	167
	168	gpio-controller;
	169	#gpio-cells = <2>;
	170
	171	micdet-cfg = <0>;
	172	micdet-delay = <100>;
	173	gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
	174	};
331da58c LD	175
	176	tps62361 {
	177	compatible = "ti,tps62361";
	178	reg = <0x60>;
	179
	180	regulator-name = "tps62361-vout";
	181	regulator-min-microvolt = <500000>;
	182	regulator-max-microvolt = <1500000>;
	183	regulator-boot-on;
	184	regulator-always-on;
	185	ti,vsel0-state-high;
	186	ti,vsel1-state-high;
	187	};
167e6279 LD	188
	189	pmic: tps65911@2d {
	190	compatible = "ti,tps65911";
	191	reg = <0x2d>;
	192
	193	interrupts = <0 86 0x4>;
	194	#interrupt-cells = <2>;
	195	interrupt-controller;
	196
44b12ef7 SW	197	ti,system-power-controller;
44b12ef7 SW	198
167e6279 LD	199	#gpio-cells = <2>;
	200	gpio-controller;
	201
	202	vcc1-supply = <&vdd_ac_bat_reg>;
	203	vcc2-supply = <&vdd_ac_bat_reg>;
	204	vcc3-supply = <&vio_reg>;
fa4a9252	205	vcc4-supply = <&vdd_5v0_reg>;
167e6279 LD	206	vcc5-supply = <&vdd_ac_bat_reg>;
	207	vcc6-supply = <&vdd2_reg>;
	208	vcc7-supply = <&vdd_ac_bat_reg>;
	209	vccio-supply = <&vdd_ac_bat_reg>;
	210
	211	regulators {
b9c665d7	212	vdd1_reg: vdd1 {
167e6279 LD	213	regulator-name = "vddio_ddr_1v2";
	214	regulator-min-microvolt = <1200000>;
	215	regulator-max-microvolt = <1200000>;
	216	regulator-always-on;
	217	};
	218
b9c665d7	219	vdd2_reg: vdd2 {
167e6279 LD	220	regulator-name = "vdd_1v5_gen";
	221	regulator-min-microvolt = <1500000>;
	222	regulator-max-microvolt = <1500000>;
	223	regulator-always-on;
	224	};
	225
b9c665d7	226	vddctrl_reg: vddctrl {
167e6279 LD	227	regulator-name = "vdd_cpu,vdd_sys";
	228	regulator-min-microvolt = <1000000>;
	229	regulator-max-microvolt = <1000000>;
	230	regulator-always-on;
	231	};
	232
b9c665d7	233	vio_reg: vio {
167e6279 LD	234	regulator-name = "vdd_1v8_gen";
	235	regulator-min-microvolt = <1800000>;
	236	regulator-max-microvolt = <1800000>;
	237	regulator-always-on;
	238	};
	239
b9c665d7	240	ldo1_reg: ldo1 {
167e6279 LD	241	regulator-name = "vdd_pexa,vdd_pexb";
	242	regulator-min-microvolt = <1050000>;
	243	regulator-max-microvolt = <1050000>;
	244	};
	245
b9c665d7	246	ldo2_reg: ldo2 {
167e6279 LD	247	regulator-name = "vdd_sata,avdd_plle";
	248	regulator-min-microvolt = <1050000>;
	249	regulator-max-microvolt = <1050000>;
	250	};
	251
	252	/* LDO3 is not connected to anything */
	253
b9c665d7	254	ldo4_reg: ldo4 {
167e6279 LD	255	regulator-name = "vdd_rtc";
	256	regulator-min-microvolt = <1200000>;
	257	regulator-max-microvolt = <1200000>;
	258	regulator-always-on;
	259	};
	260
b9c665d7	261	ldo5_reg: ldo5 {
fa4a9252 LD	262	regulator-name = "vddio_sdmmc,avdd_vdac";
	263	regulator-min-microvolt = <3300000>;
	264	regulator-max-microvolt = <3300000>;
	265	regulator-always-on;
	266	};
	267
b9c665d7	268	ldo6_reg: ldo6 {
167e6279 LD	269	regulator-name = "avdd_dsi_csi,pwrdet_mipi";
	270	regulator-min-microvolt = <1200000>;
	271	regulator-max-microvolt = <1200000>;
	272	};
	273
b9c665d7	274	ldo7_reg: ldo7 {
167e6279 LD	275	regulator-name = "vdd_pllm,x,u,a_p_c_s";
	276	regulator-min-microvolt = <1200000>;
	277	regulator-max-microvolt = <1200000>;
	278	regulator-always-on;
	279	};
	280
b9c665d7	281	ldo8_reg: ldo8 {
167e6279 LD	282	regulator-name = "vdd_ddr_hs";
	283	regulator-min-microvolt = <1000000>;
	284	regulator-max-microvolt = <1000000>;
	285	regulator-always-on;
	286	};
	287	};
	288	};
64c4e9f8	289	};
850c4c8f	290
c42cb1c3 LD	291	spi@7000da00 {
	292	status = "okay";
	293	spi-max-frequency = <25000000>;
	294	spi-flash@1 {
	295	compatible = "winbond,w25q32";
	296	reg = <1>;
	297	spi-max-frequency = <20000000>;
	298	};
	299	};
	300
f9eb26a4	301	ahub {
2a5fdc9a SW	302	i2s@70080400 {
2a5fdc9a SW	303	status = "okay";
8c6a3852 SW	304	};
	305	};
	306
167e6279 LD	307	pmc {
	308	status = "okay";
	309	nvidia,invert-interrupt;
	310	};
	311
c04abb3a	312	sdhci@78000000 {
2a5fdc9a	313	status = "okay";
908ab936	314	cd-gpios = <&gpio 69 1>; /* gpio PI5 */
c04abb3a SW	315	wp-gpios = <&gpio 155 0>; /* gpio PT3 */
c04abb3a SW	316	power-gpios = <&gpio 31 0>; /* gpio PD7 */
7f217794	317	bus-width = <4>;
c04abb3a SW	318	};
c04abb3a SW	319
c04abb3a	320	sdhci@78000600 {
2a5fdc9a	321	status = "okay";
7f217794	322	bus-width = <8>;
7a2617a6	323	non-removable;
c04abb3a SW	324	};
c04abb3a SW	325
7021d122 JL	326	clocks {
	327	compatible = "simple-bus";
	328	#address-cells = <1>;
	329	#size-cells = <0>;
	330
	331	clk32k_in: clock {
	332	compatible = "fixed-clock";
	333	reg=<0>;
	334	#clock-cells = <0>;
	335	clock-frequency = <32768>;
	336	};
	337	};
	338
167e6279 LD	339	regulators {
	340	compatible = "simple-bus";
	341	#address-cells = <1>;
	342	#size-cells = <0>;
	343
	344	vdd_ac_bat_reg: regulator@0 {
	345	compatible = "regulator-fixed";
	346	reg = <0>;
	347	regulator-name = "vdd_ac_bat";
	348	regulator-min-microvolt = <5000000>;
	349	regulator-max-microvolt = <5000000>;
	350	regulator-always-on;
	351	};
fa4a9252 LD	352
	353	cam_1v8_reg: regulator@1 {
	354	compatible = "regulator-fixed";
	355	reg = <1>;
	356	regulator-name = "cam_1v8";
	357	regulator-min-microvolt = <1800000>;
	358	regulator-max-microvolt = <1800000>;
	359	enable-active-high;
	360	gpio = <&gpio 220 0>; /* gpio PBB4 */
	361	vin-supply = <&vio_reg>;
	362	};
	363
	364	cp_5v_reg: regulator@2 {
	365	compatible = "regulator-fixed";
	366	reg = <2>;
	367	regulator-name = "cp_5v";
	368	regulator-min-microvolt = <5000000>;
	369	regulator-max-microvolt = <5000000>;
	370	regulator-boot-on;
	371	regulator-always-on;
	372	enable-active-high;
	373	gpio = <&pmic 0 0>; /* PMIC TPS65911 GPIO0 */
	374	};
	375
	376	emmc_3v3_reg: regulator@3 {
	377	compatible = "regulator-fixed";
	378	reg = <3>;
	379	regulator-name = "emmc_3v3";
	380	regulator-min-microvolt = <3300000>;
	381	regulator-max-microvolt = <3300000>;
	382	regulator-always-on;
	383	regulator-boot-on;
	384	enable-active-high;
	385	gpio = <&gpio 25 0>; /* gpio PD1 */
	386	vin-supply = <&sys_3v3_reg>;
	387	};
	388
	389	modem_3v3_reg: regulator@4 {
	390	compatible = "regulator-fixed";
	391	reg = <4>;
	392	regulator-name = "modem_3v3";
	393	regulator-min-microvolt = <3300000>;
	394	regulator-max-microvolt = <3300000>;
	395	enable-active-high;
	396	gpio = <&gpio 30 0>; /* gpio PD6 */
	397	};
	398
	399	pex_hvdd_3v3_reg: regulator@5 {
	400	compatible = "regulator-fixed";
	401	reg = <5>;
	402	regulator-name = "pex_hvdd_3v3";
	403	regulator-min-microvolt = <3300000>;
	404	regulator-max-microvolt = <3300000>;
	405	enable-active-high;
	406	gpio = <&gpio 95 0>; /* gpio PL7 */
	407	vin-supply = <&sys_3v3_reg>;
	408	};
	409
	410	vdd_cam1_ldo_reg: regulator@6 {
	411	compatible = "regulator-fixed";
	412	reg = <6>;
	413	regulator-name = "vdd_cam1_ldo";
	414	regulator-min-microvolt = <2800000>;
	415	regulator-max-microvolt = <2800000>;
416	enable-active-high;
417	gpio = <&gpio 142 0>; /* gpio PR6 */
418	vin-supply = <&sys_3v3_reg>;
419	};
420
421	vdd_cam2_ldo_reg: regulator@7 {
422	compatible = "regulator-fixed";
423	reg = <7>;
424	regulator-name = "vdd_cam2_ldo";
425	regulator-min-microvolt = <2800000>;
426	regulator-max-microvolt = <2800000>;
427	enable-active-high;
428	gpio = <&gpio 143 0>; /* gpio PR7 */
429	vin-supply = <&sys_3v3_reg>;
430	};
431
432	vdd_cam3_ldo_reg: regulator@8 {
433	compatible = "regulator-fixed";
434	reg = <8>;
435	regulator-name = "vdd_cam3_ldo";
436	regulator-min-microvolt = <3300000>;
437	regulator-max-microvolt = <3300000>;
438	enable-active-high;
439	gpio = <&gpio 144 0>; /* gpio PS0 */
440	vin-supply = <&sys_3v3_reg>;
441	};
442
443	vdd_com_reg: regulator@9 {
444	compatible = "regulator-fixed";
445	reg = <9>;
446	regulator-name = "vdd_com";
447	regulator-min-microvolt = <3300000>;
448	regulator-max-microvolt = <3300000>;
6fb11131 WN	449	regulator-always-on;
6fb11131 WN	450	regulator-boot-on;
fa4a9252 LD	451	enable-active-high;
	452	gpio = <&gpio 24 0>; /* gpio PD0 */
	453	vin-supply = <&sys_3v3_reg>;
	454	};
	455
	456	vdd_fuse_3v3_reg: regulator@10 {
	457	compatible = "regulator-fixed";
	458	reg = <10>;
	459	regulator-name = "vdd_fuse_3v3";
	460	regulator-min-microvolt = <3300000>;
	461	regulator-max-microvolt = <3300000>;
	462	enable-active-high;
	463	gpio = <&gpio 94 0>; /* gpio PL6 */
	464	vin-supply = <&sys_3v3_reg>;
	465	};
	466
	467	vdd_pnl1_reg: regulator@11 {
	468	compatible = "regulator-fixed";
	469	reg = <11>;
	470	regulator-name = "vdd_pnl1";
	471	regulator-min-microvolt = <3300000>;
	472	regulator-max-microvolt = <3300000>;
	473	regulator-always-on;
	474	regulator-boot-on;
	475	enable-active-high;
	476	gpio = <&gpio 92 0>; /* gpio PL4 */
	477	vin-supply = <&sys_3v3_reg>;
	478	};
	479
	480	vdd_vid_reg: regulator@12 {
	481	compatible = "regulator-fixed";
	482	reg = <12>;
	483	regulator-name = "vddio_vid";
	484	regulator-min-microvolt = <5000000>;
	485	regulator-max-microvolt = <5000000>;
	486	enable-active-high;
	487	gpio = <&gpio 152 0>; /* GPIO PT0 */
	488	gpio-open-drain;
	489	vin-supply = <&vdd_5v0_reg>;
	490	};
167e6279 LD	491	};
167e6279 LD	492
8c6a3852 SW	493	sound {
	494	compatible = "nvidia,tegra-audio-wm8903-cardhu",
	495	"nvidia,tegra-audio-wm8903";
	496	nvidia,model = "NVIDIA Tegra Cardhu";
	497
	498	nvidia,audio-routing =
	499	"Headphone Jack", "HPOUTR",
	500	"Headphone Jack", "HPOUTL",
	501	"Int Spk", "ROP",
	502	"Int Spk", "RON",
	503	"Int Spk", "LOP",
	504	"Int Spk", "LON",
	505	"Mic Jack", "MICBIAS",
	506	"IN1L", "Mic Jack";
	507
	508	nvidia,i2s-controller = <&tegra_i2s1>;
	509	nvidia,audio-codec = <&wm8903>;
	510
	511	nvidia,spkr-en-gpios = <&wm8903 2 0>;
	512	nvidia,hp-det-gpios = <&gpio 178 0>; /* gpio PW2 */
f9cd2b3b SW	513
	514	clocks = <&tegra_car 184>, <&tegra_car 185>, <&tegra_car 120>;
	515	clock-names = "pll_a", "pll_a_out0", "mclk";
8c6a3852	516	};
64c4e9f8	517	};