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ARM: tegra: colibri: Improve comment about thermal alert pin
[deliverable/linux.git] / arch / arm / boot / dts / tegra30-colibri.dtsi
CommitLineData
446e9c63
SA		 1#include <dt-bindings/input/input.h>
2#include "tegra30.dtsi"
3
4/*
39ebbf61
MZ		 5 * Toradex Colibri T30 Module Device Tree
6 * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A
446e9c63
SA		 7 */
8/ {
9 model = "Toradex Colibri T30";
10 compatible = "toradex,colibri_t30", "nvidia,tegra30";
11
12 memory {
13 reg = <0x80000000 0x40000000>;
14 };
15
16 host1x@50000000 {
17 hdmi@54280000 {
312d3732
MZ		 18 vdd-supply = <&avdd_hdmi_3v3_reg>;
19 pll-supply = <&avdd_hdmi_pll_1v8_reg>;
446e9c63
SA		 20
21 nvidia,hpd-gpio =
22 <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>;
23 nvidia,ddc-i2c-bus = <&hdmiddc>;
24 };
25 };
26
27 pinmux@70000868 {
28 pinctrl-names = "default";
29 pinctrl-0 = <&state_default>;
30
31 state_default: pinmux {
32 /* Colibri BL_ON */
33 pv2 {
34 nvidia,pins = "pv2";
35 nvidia,function = "rsvd4";
36 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
37 nvidia,tristate = <TEGRA_PIN_DISABLE>;
38 };
39
40 /* Colibri Backlight PWM<A> */
41 sdmmc3_dat3_pb4 {
42 nvidia,pins = "sdmmc3_dat3_pb4";
43 nvidia,function = "pwm0";
44 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
45 nvidia,tristate = <TEGRA_PIN_DISABLE>;
46 };
47
48 /* Colibri CAN_INT */
49 kb_row8_ps0 {
50 nvidia,pins = "kb_row8_ps0";
51 nvidia,function = "kbc";
52 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
53 nvidia,tristate = <TEGRA_PIN_DISABLE>;
54 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
55 };
56
57 /*
58 * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE
59 * todays display need DE, disable LCD_M1
60 */
61 lcd_m1_pw1 {
62 nvidia,pins = "lcd_m1_pw1";
63 nvidia,function = "rsvd3";
64 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
65 nvidia,tristate = <TEGRA_PIN_DISABLE>;
66 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
67 };
68
446e9c63
SA		 69 /* Colibri MMC */
70 kb_row10_ps2 {
71 nvidia,pins = "kb_row10_ps2";
72 nvidia,function = "sdmmc2";
73 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
74 nvidia,tristate = <TEGRA_PIN_DISABLE>;
75 };
76 kb_row11_ps3 {
77 nvidia,pins = "kb_row11_ps3",
78 "kb_row12_ps4",
79 "kb_row13_ps5",
80 "kb_row14_ps6",
81 "kb_row15_ps7";
82 nvidia,function = "sdmmc2";
83 nvidia,pull = <TEGRA_PIN_PULL_UP>;
84 nvidia,tristate = <TEGRA_PIN_DISABLE>;
85 };
86
87 /* Colibri SSP */
88 ulpi_clk_py0 {
89 nvidia,pins = "ulpi_clk_py0",
90 "ulpi_dir_py1",
91 "ulpi_nxt_py2",
92 "ulpi_stp_py3";
93 nvidia,function = "spi1";
94 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
95 nvidia,tristate = <TEGRA_PIN_DISABLE>;
96 };
97 sdmmc3_dat6_pd3 {
98 nvidia,pins = "sdmmc3_dat6_pd3",
99 "sdmmc3_dat7_pd4";
100 nvidia,function = "spdif";
101 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
102 nvidia,tristate = <TEGRA_PIN_ENABLE>;
103 };
104
105 /* Colibri UART_A */
106 ulpi_data0 {
107 nvidia,pins = "ulpi_data0_po1",
108 "ulpi_data1_po2",
109 "ulpi_data2_po3",
110 "ulpi_data3_po4",
111 "ulpi_data4_po5",
112 "ulpi_data5_po6",
113 "ulpi_data6_po7",
114 "ulpi_data7_po0";
115 nvidia,function = "uarta";
116 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
117 nvidia,tristate = <TEGRA_PIN_DISABLE>;
118 };
119
120 /* Colibri UART_B */
121 gmi_a16_pj7 {
122 nvidia,pins = "gmi_a16_pj7",
123 "gmi_a17_pb0",
124 "gmi_a18_pb1",
125 "gmi_a19_pk7";
126 nvidia,function = "uartd";
127 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
128 nvidia,tristate = <TEGRA_PIN_DISABLE>;
129 };
130
131 /* Colibri UART_C */
132 uart2_rxd {
133 nvidia,pins = "uart2_rxd_pc3",
134 "uart2_txd_pc2";
135 nvidia,function = "uartb";
136 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
137 nvidia,tristate = <TEGRA_PIN_DISABLE>;
138 };
139
140 /* eMMC */
141 sdmmc4_clk_pcc4 {
142 nvidia,pins = "sdmmc4_clk_pcc4",
143 "sdmmc4_rst_n_pcc3";
144 nvidia,function = "sdmmc4";
145 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
146 nvidia,tristate = <TEGRA_PIN_DISABLE>;
147 };
148 sdmmc4_dat0_paa0 {
149 nvidia,pins = "sdmmc4_dat0_paa0",
150 "sdmmc4_dat1_paa1",
151 "sdmmc4_dat2_paa2",
152 "sdmmc4_dat3_paa3",
153 "sdmmc4_dat4_paa4",
154 "sdmmc4_dat5_paa5",
155 "sdmmc4_dat6_paa6",
156 "sdmmc4_dat7_paa7";
157 nvidia,function = "sdmmc4";
158 nvidia,pull = <TEGRA_PIN_PULL_UP>;
159 nvidia,tristate = <TEGRA_PIN_DISABLE>;
160 };
62bcaba1
MZ		 161
162 /*
163 * THERMD_ALERT#, unlatched I2C address pin of LM95245
164 * temperature sensor therefore requires disabling for
165 * now
166 */
167 lcd_dc1_pd2 {
168 nvidia,pins = "lcd_dc1_pd2";
169 nvidia,function = "rsvd3";
170 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
171 nvidia,tristate = <TEGRA_PIN_DISABLE>;
172 nvidia,enable-input = <TEGRA_PIN_ENABLE>;
173 };
446e9c63
SA		 174 };
175 };
176
177 hdmiddc: i2c@7000c700 {
178 clock-frequency = <100000>;
179 };
180
181 /*
182 * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and
183 * touch screen controller
184 */
185 i2c@7000d000 {
186 status = "okay";
187 clock-frequency = <100000>;
188
189 pmic: tps65911@2d {
190 compatible = "ti,tps65911";
191 reg = <0x2d>;
192
193 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
194 #interrupt-cells = <2>;
195 interrupt-controller;
196
197 ti,system-power-controller;
198
199 #gpio-cells = <2>;
200 gpio-controller;
201
202 vcc1-supply = <&sys_3v3_reg>;
203 vcc2-supply = <&sys_3v3_reg>;
204 vcc3-supply = <&vio_reg>;
205 vcc4-supply = <&sys_3v3_reg>;
206 vcc5-supply = <&sys_3v3_reg>;
207 vcc6-supply = <&vio_reg>;
caa9eac5 208 vcc7-supply = <&charge_pump_5v0_reg>;
446e9c63
SA		 209 vccio-supply = <&sys_3v3_reg>;
210
211 regulators {
212 /* SW1: +V1.35_VDDIO_DDR */
213 vdd1_reg: vdd1 {
214 regulator-name = "vddio_ddr_1v35";
215 regulator-min-microvolt = <1350000>;
216 regulator-max-microvolt = <1350000>;
217 regulator-always-on;
218 };
219
220 /* SW2: unused */
221
222 /* SW CTRL: +V1.0_VDD_CPU */
223 vddctrl_reg: vddctrl {
224 regulator-name = "vdd_cpu,vdd_sys";
225 regulator-min-microvolt = <1150000>;
226 regulator-max-microvolt = <1150000>;
227 regulator-always-on;
228 };
229
230 /* SWIO: +V1.8 */
231 vio_reg: vio {
232 regulator-name = "vdd_1v8_gen";
233 regulator-min-microvolt = <1800000>;
234 regulator-max-microvolt = <1800000>;
235 regulator-always-on;
236 };
237
238 /* LDO1: unused */
239
240 /*
241 * EN_+V3.3 switching via FET:
242 * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN
243 * see also v3_3 fixed supply
244 */
245 ldo2_reg: ldo2 {
246 regulator-name = "en_3v3";
247 regulator-min-microvolt = <3300000>;
248 regulator-max-microvolt = <3300000>;
249 regulator-always-on;
250 };
251
252 /* LDO3: unused */
253
254 /* +V1.2_VDD_RTC */
255 ldo4_reg: ldo4 {
256 regulator-name = "vdd_rtc";
257 regulator-min-microvolt = <1200000>;
258 regulator-max-microvolt = <1200000>;
259 regulator-always-on;
260 };
261
262 /*
263 * +V2.8_AVDD_VDAC:
264 * only required for analog RGB
265 */
266 ldo5_reg: ldo5 {
267 regulator-name = "avdd_vdac";
268 regulator-min-microvolt = <2800000>;
269 regulator-max-microvolt = <2800000>;
270 regulator-always-on;
271 };
272
273 /*
274 * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V
275 * but LDO6 can't set voltage in 50mV
276 * granularity
277 */
278 ldo6_reg: ldo6 {
279 regulator-name = "avdd_plle";
280 regulator-min-microvolt = <1100000>;
281 regulator-max-microvolt = <1100000>;
282 };
283
284 /* +V1.2_AVDD_PLL */
285 ldo7_reg: ldo7 {
286 regulator-name = "avdd_pll";
287 regulator-min-microvolt = <1200000>;
288 regulator-max-microvolt = <1200000>;
289 regulator-always-on;
290 };
291
292 /* +V1.0_VDD_DDR_HS */
293 ldo8_reg: ldo8 {
294 regulator-name = "vdd_ddr_hs";
295 regulator-min-microvolt = <1000000>;
296 regulator-max-microvolt = <1000000>;
297 regulator-always-on;
298 };
299 };
300 };
301
302 /*
303 * LM95245 temperature sensor
304 * Note: OVERT_N directly connected to PMIC PWRDN
305 */
306 temp-sensor@4c {
307 compatible = "national,lm95245";
308 reg = <0x4c>;
309 };
310
311 /* SW: +V1.2_VDD_CORE */
312 tps62362@60 {
313 compatible = "ti,tps62362";
314 reg = <0x60>;
315
316 regulator-name = "tps62362-vout";
317 regulator-min-microvolt = <900000>;
318 regulator-max-microvolt = <1400000>;
319 regulator-boot-on;
320 regulator-always-on;
321 ti,vsel0-state-low;
322 /* VSEL1: EN_CORE_DVFS_N low for DVFS */
323 ti,vsel1-state-low;
324 };
325 };
326
327 pmc@7000e400 {
328 nvidia,invert-interrupt;
329 nvidia,suspend-mode = <1>;
330 nvidia,cpu-pwr-good-time = <5000>;
331 nvidia,cpu-pwr-off-time = <5000>;
332 nvidia,core-pwr-good-time = <3845 3845>;
333 nvidia,core-pwr-off-time = <0>;
334 nvidia,core-power-req-active-high;
335 nvidia,sys-clock-req-active-high;
336 };
337
338 emmc: sdhci@78000600 {
339 status = "okay";
340 bus-width = <8>;
341 non-removable;
342 };
343
344 /* EHCI instance 1: USB2_DP/N -> AX88772B */
345 usb@7d004000 {
346 status = "okay";
347 };
348
349 usb-phy@7d004000 {
350 status = "okay";
351 nvidia,is-wired = <1>;
352 };
353
354 clocks {
355 compatible = "simple-bus";
356 #address-cells = <1>;
357 #size-cells = <0>;
358
359 clk32k_in: clk@0 {
360 compatible = "fixed-clock";
361 reg=<0>;
362 #clock-cells = <0>;
363 clock-frequency = <32768>;
364 };
365 };
366
367 regulators {
368 compatible = "simple-bus";
369 #address-cells = <1>;
370 #size-cells = <0>;
371
312d3732 372 avdd_hdmi_pll_1v8_reg: regulator@100 {
446e9c63
SA		 373 compatible = "regulator-fixed";
374 reg = <100>;
312d3732
MZ		 375 regulator-name = "+V1.8_AVDD_HDMI_PLL";
376 regulator-min-microvolt = <1800000>;
377 regulator-max-microvolt = <1800000>;
378 enable-active-high;
379 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
380 vin-supply = <&vio_reg>;
381 };
382
383 sys_3v3_reg: regulator@101 {
384 compatible = "regulator-fixed";
385 reg = <101>;
446e9c63
SA		 386 regulator-name = "3v3";
387 regulator-min-microvolt = <3300000>;
388 regulator-max-microvolt = <3300000>;
389 regulator-always-on;
390 };
caa9eac5 391
312d3732 392 avdd_hdmi_3v3_reg: regulator@102 {
caa9eac5 393 compatible = "regulator-fixed";
312d3732
MZ		 394 reg = <102>;
395 regulator-name = "+V3.3_AVDD_HDMI";
396 regulator-min-microvolt = <3300000>;
397 regulator-max-microvolt = <3300000>;
398 enable-active-high;
399 gpio = <&pmic 6 GPIO_ACTIVE_HIGH>;
400 vin-supply = <&sys_3v3_reg>;
401 };
402
403 charge_pump_5v0_reg: regulator@103 {
404 compatible = "regulator-fixed";
405 reg = <103>;
caa9eac5
MZ		 406 regulator-name = "5v0";
407 regulator-min-microvolt = <5000000>;
408 regulator-max-microvolt = <5000000>;
409 regulator-always-on;
410 };
446e9c63
SA		 411 };
412};
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