Commit | Line | Data |
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446e9c63 SA |
1 | #include <dt-bindings/input/input.h> |
2 | #include "tegra30.dtsi" | |
3 | ||
4 | /* | |
39ebbf61 MZ |
5 | * Toradex Colibri T30 Module Device Tree |
6 | * Compatible for Revisions V1.1B, V1.1C, V1.1D, V1.1E; IT: V1.1A | |
446e9c63 SA |
7 | */ |
8 | / { | |
9 | model = "Toradex Colibri T30"; | |
10 | compatible = "toradex,colibri_t30", "nvidia,tegra30"; | |
11 | ||
12 | memory { | |
13 | reg = <0x80000000 0x40000000>; | |
14 | }; | |
15 | ||
16 | host1x@50000000 { | |
17 | hdmi@54280000 { | |
312d3732 MZ |
18 | vdd-supply = <&avdd_hdmi_3v3_reg>; |
19 | pll-supply = <&avdd_hdmi_pll_1v8_reg>; | |
446e9c63 SA |
20 | |
21 | nvidia,hpd-gpio = | |
22 | <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; | |
23 | nvidia,ddc-i2c-bus = <&hdmiddc>; | |
24 | }; | |
25 | }; | |
26 | ||
27 | pinmux@70000868 { | |
28 | pinctrl-names = "default"; | |
29 | pinctrl-0 = <&state_default>; | |
30 | ||
31 | state_default: pinmux { | |
32 | /* Colibri BL_ON */ | |
33 | pv2 { | |
34 | nvidia,pins = "pv2"; | |
35 | nvidia,function = "rsvd4"; | |
36 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
37 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
38 | }; | |
39 | ||
40 | /* Colibri Backlight PWM<A> */ | |
41 | sdmmc3_dat3_pb4 { | |
42 | nvidia,pins = "sdmmc3_dat3_pb4"; | |
43 | nvidia,function = "pwm0"; | |
44 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
45 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
46 | }; | |
47 | ||
48 | /* Colibri CAN_INT */ | |
49 | kb_row8_ps0 { | |
50 | nvidia,pins = "kb_row8_ps0"; | |
51 | nvidia,function = "kbc"; | |
52 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
53 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
54 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
55 | }; | |
56 | ||
57 | /* | |
58 | * Colibri L_BIAS, LCD_M1 is muxed with LCD_DE | |
59 | * todays display need DE, disable LCD_M1 | |
60 | */ | |
61 | lcd_m1_pw1 { | |
62 | nvidia,pins = "lcd_m1_pw1"; | |
63 | nvidia,function = "rsvd3"; | |
64 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
65 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
66 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
67 | }; | |
68 | ||
446e9c63 SA |
69 | /* Colibri MMC */ |
70 | kb_row10_ps2 { | |
71 | nvidia,pins = "kb_row10_ps2"; | |
72 | nvidia,function = "sdmmc2"; | |
73 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
74 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
75 | }; | |
76 | kb_row11_ps3 { | |
77 | nvidia,pins = "kb_row11_ps3", | |
78 | "kb_row12_ps4", | |
79 | "kb_row13_ps5", | |
80 | "kb_row14_ps6", | |
81 | "kb_row15_ps7"; | |
82 | nvidia,function = "sdmmc2"; | |
83 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
84 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
85 | }; | |
86 | ||
87 | /* Colibri SSP */ | |
88 | ulpi_clk_py0 { | |
89 | nvidia,pins = "ulpi_clk_py0", | |
90 | "ulpi_dir_py1", | |
91 | "ulpi_nxt_py2", | |
92 | "ulpi_stp_py3"; | |
93 | nvidia,function = "spi1"; | |
94 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
95 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
96 | }; | |
97 | sdmmc3_dat6_pd3 { | |
98 | nvidia,pins = "sdmmc3_dat6_pd3", | |
99 | "sdmmc3_dat7_pd4"; | |
100 | nvidia,function = "spdif"; | |
101 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
102 | nvidia,tristate = <TEGRA_PIN_ENABLE>; | |
103 | }; | |
104 | ||
105 | /* Colibri UART_A */ | |
106 | ulpi_data0 { | |
107 | nvidia,pins = "ulpi_data0_po1", | |
108 | "ulpi_data1_po2", | |
109 | "ulpi_data2_po3", | |
110 | "ulpi_data3_po4", | |
111 | "ulpi_data4_po5", | |
112 | "ulpi_data5_po6", | |
113 | "ulpi_data6_po7", | |
114 | "ulpi_data7_po0"; | |
115 | nvidia,function = "uarta"; | |
116 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
117 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
118 | }; | |
119 | ||
120 | /* Colibri UART_B */ | |
121 | gmi_a16_pj7 { | |
122 | nvidia,pins = "gmi_a16_pj7", | |
123 | "gmi_a17_pb0", | |
124 | "gmi_a18_pb1", | |
125 | "gmi_a19_pk7"; | |
126 | nvidia,function = "uartd"; | |
127 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
128 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
129 | }; | |
130 | ||
131 | /* Colibri UART_C */ | |
132 | uart2_rxd { | |
133 | nvidia,pins = "uart2_rxd_pc3", | |
134 | "uart2_txd_pc2"; | |
135 | nvidia,function = "uartb"; | |
136 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
137 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
138 | }; | |
139 | ||
140 | /* eMMC */ | |
141 | sdmmc4_clk_pcc4 { | |
142 | nvidia,pins = "sdmmc4_clk_pcc4", | |
143 | "sdmmc4_rst_n_pcc3"; | |
144 | nvidia,function = "sdmmc4"; | |
145 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
146 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
147 | }; | |
148 | sdmmc4_dat0_paa0 { | |
149 | nvidia,pins = "sdmmc4_dat0_paa0", | |
150 | "sdmmc4_dat1_paa1", | |
151 | "sdmmc4_dat2_paa2", | |
152 | "sdmmc4_dat3_paa3", | |
153 | "sdmmc4_dat4_paa4", | |
154 | "sdmmc4_dat5_paa5", | |
155 | "sdmmc4_dat6_paa6", | |
156 | "sdmmc4_dat7_paa7"; | |
157 | nvidia,function = "sdmmc4"; | |
158 | nvidia,pull = <TEGRA_PIN_PULL_UP>; | |
159 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
160 | }; | |
62bcaba1 | 161 | |
e48f6c0e MZ |
162 | /* Power I2C (On-module) */ |
163 | pwr_i2c_scl_pz6 { | |
164 | nvidia,pins = "pwr_i2c_scl_pz6", | |
165 | "pwr_i2c_sda_pz7"; | |
166 | nvidia,function = "i2cpwr"; | |
167 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
168 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
169 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
170 | nvidia,lock = <TEGRA_PIN_DISABLE>; | |
171 | nvidia,open-drain = <TEGRA_PIN_ENABLE>; | |
172 | }; | |
173 | ||
62bcaba1 MZ |
174 | /* |
175 | * THERMD_ALERT#, unlatched I2C address pin of LM95245 | |
176 | * temperature sensor therefore requires disabling for | |
177 | * now | |
178 | */ | |
179 | lcd_dc1_pd2 { | |
180 | nvidia,pins = "lcd_dc1_pd2"; | |
181 | nvidia,function = "rsvd3"; | |
182 | nvidia,pull = <TEGRA_PIN_PULL_NONE>; | |
183 | nvidia,tristate = <TEGRA_PIN_DISABLE>; | |
184 | nvidia,enable-input = <TEGRA_PIN_ENABLE>; | |
185 | }; | |
446e9c63 SA |
186 | }; |
187 | }; | |
188 | ||
189 | hdmiddc: i2c@7000c700 { | |
190 | clock-frequency = <100000>; | |
191 | }; | |
192 | ||
193 | /* | |
194 | * PWR_I2C: power I2C to audio codec, PMIC, temperature sensor and | |
195 | * touch screen controller | |
196 | */ | |
197 | i2c@7000d000 { | |
198 | status = "okay"; | |
199 | clock-frequency = <100000>; | |
200 | ||
201 | pmic: tps65911@2d { | |
202 | compatible = "ti,tps65911"; | |
203 | reg = <0x2d>; | |
204 | ||
205 | interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; | |
206 | #interrupt-cells = <2>; | |
207 | interrupt-controller; | |
208 | ||
209 | ti,system-power-controller; | |
210 | ||
211 | #gpio-cells = <2>; | |
212 | gpio-controller; | |
213 | ||
214 | vcc1-supply = <&sys_3v3_reg>; | |
215 | vcc2-supply = <&sys_3v3_reg>; | |
216 | vcc3-supply = <&vio_reg>; | |
217 | vcc4-supply = <&sys_3v3_reg>; | |
218 | vcc5-supply = <&sys_3v3_reg>; | |
219 | vcc6-supply = <&vio_reg>; | |
caa9eac5 | 220 | vcc7-supply = <&charge_pump_5v0_reg>; |
446e9c63 SA |
221 | vccio-supply = <&sys_3v3_reg>; |
222 | ||
223 | regulators { | |
224 | /* SW1: +V1.35_VDDIO_DDR */ | |
225 | vdd1_reg: vdd1 { | |
226 | regulator-name = "vddio_ddr_1v35"; | |
227 | regulator-min-microvolt = <1350000>; | |
228 | regulator-max-microvolt = <1350000>; | |
229 | regulator-always-on; | |
230 | }; | |
231 | ||
232 | /* SW2: unused */ | |
233 | ||
234 | /* SW CTRL: +V1.0_VDD_CPU */ | |
235 | vddctrl_reg: vddctrl { | |
236 | regulator-name = "vdd_cpu,vdd_sys"; | |
237 | regulator-min-microvolt = <1150000>; | |
238 | regulator-max-microvolt = <1150000>; | |
239 | regulator-always-on; | |
240 | }; | |
241 | ||
242 | /* SWIO: +V1.8 */ | |
243 | vio_reg: vio { | |
244 | regulator-name = "vdd_1v8_gen"; | |
245 | regulator-min-microvolt = <1800000>; | |
246 | regulator-max-microvolt = <1800000>; | |
247 | regulator-always-on; | |
248 | }; | |
249 | ||
250 | /* LDO1: unused */ | |
251 | ||
252 | /* | |
253 | * EN_+V3.3 switching via FET: | |
254 | * +V3.3_AUDIO_AVDD_S, +V3.3 and +V1.8_VDD_LAN | |
b038e3b9 | 255 | * see also 3v3 fixed supply |
446e9c63 SA |
256 | */ |
257 | ldo2_reg: ldo2 { | |
258 | regulator-name = "en_3v3"; | |
259 | regulator-min-microvolt = <3300000>; | |
260 | regulator-max-microvolt = <3300000>; | |
261 | regulator-always-on; | |
262 | }; | |
263 | ||
264 | /* LDO3: unused */ | |
265 | ||
266 | /* +V1.2_VDD_RTC */ | |
267 | ldo4_reg: ldo4 { | |
268 | regulator-name = "vdd_rtc"; | |
269 | regulator-min-microvolt = <1200000>; | |
270 | regulator-max-microvolt = <1200000>; | |
271 | regulator-always-on; | |
272 | }; | |
273 | ||
274 | /* | |
275 | * +V2.8_AVDD_VDAC: | |
276 | * only required for analog RGB | |
277 | */ | |
278 | ldo5_reg: ldo5 { | |
279 | regulator-name = "avdd_vdac"; | |
280 | regulator-min-microvolt = <2800000>; | |
281 | regulator-max-microvolt = <2800000>; | |
282 | regulator-always-on; | |
283 | }; | |
284 | ||
285 | /* | |
286 | * +V1.05_AVDD_PLLE: avdd_plle should be 1.05V | |
287 | * but LDO6 can't set voltage in 50mV | |
288 | * granularity | |
289 | */ | |
290 | ldo6_reg: ldo6 { | |
291 | regulator-name = "avdd_plle"; | |
292 | regulator-min-microvolt = <1100000>; | |
293 | regulator-max-microvolt = <1100000>; | |
294 | }; | |
295 | ||
296 | /* +V1.2_AVDD_PLL */ | |
297 | ldo7_reg: ldo7 { | |
298 | regulator-name = "avdd_pll"; | |
299 | regulator-min-microvolt = <1200000>; | |
300 | regulator-max-microvolt = <1200000>; | |
301 | regulator-always-on; | |
302 | }; | |
303 | ||
304 | /* +V1.0_VDD_DDR_HS */ | |
305 | ldo8_reg: ldo8 { | |
306 | regulator-name = "vdd_ddr_hs"; | |
307 | regulator-min-microvolt = <1000000>; | |
308 | regulator-max-microvolt = <1000000>; | |
309 | regulator-always-on; | |
310 | }; | |
311 | }; | |
312 | }; | |
313 | ||
314 | /* | |
315 | * LM95245 temperature sensor | |
316 | * Note: OVERT_N directly connected to PMIC PWRDN | |
317 | */ | |
318 | temp-sensor@4c { | |
319 | compatible = "national,lm95245"; | |
320 | reg = <0x4c>; | |
321 | }; | |
322 | ||
323 | /* SW: +V1.2_VDD_CORE */ | |
324 | tps62362@60 { | |
325 | compatible = "ti,tps62362"; | |
326 | reg = <0x60>; | |
327 | ||
328 | regulator-name = "tps62362-vout"; | |
329 | regulator-min-microvolt = <900000>; | |
330 | regulator-max-microvolt = <1400000>; | |
331 | regulator-boot-on; | |
332 | regulator-always-on; | |
333 | ti,vsel0-state-low; | |
334 | /* VSEL1: EN_CORE_DVFS_N low for DVFS */ | |
335 | ti,vsel1-state-low; | |
336 | }; | |
337 | }; | |
338 | ||
339 | pmc@7000e400 { | |
340 | nvidia,invert-interrupt; | |
341 | nvidia,suspend-mode = <1>; | |
342 | nvidia,cpu-pwr-good-time = <5000>; | |
343 | nvidia,cpu-pwr-off-time = <5000>; | |
344 | nvidia,core-pwr-good-time = <3845 3845>; | |
345 | nvidia,core-pwr-off-time = <0>; | |
346 | nvidia,core-power-req-active-high; | |
347 | nvidia,sys-clock-req-active-high; | |
348 | }; | |
349 | ||
350 | emmc: sdhci@78000600 { | |
351 | status = "okay"; | |
352 | bus-width = <8>; | |
353 | non-removable; | |
354 | }; | |
355 | ||
356 | /* EHCI instance 1: USB2_DP/N -> AX88772B */ | |
357 | usb@7d004000 { | |
358 | status = "okay"; | |
359 | }; | |
360 | ||
361 | usb-phy@7d004000 { | |
362 | status = "okay"; | |
363 | nvidia,is-wired = <1>; | |
364 | }; | |
365 | ||
366 | clocks { | |
367 | compatible = "simple-bus"; | |
368 | #address-cells = <1>; | |
369 | #size-cells = <0>; | |
370 | ||
371 | clk32k_in: clk@0 { | |
372 | compatible = "fixed-clock"; | |
373 | reg=<0>; | |
374 | #clock-cells = <0>; | |
375 | clock-frequency = <32768>; | |
376 | }; | |
377 | }; | |
378 | ||
379 | regulators { | |
380 | compatible = "simple-bus"; | |
381 | #address-cells = <1>; | |
382 | #size-cells = <0>; | |
383 | ||
312d3732 | 384 | avdd_hdmi_pll_1v8_reg: regulator@100 { |
446e9c63 SA |
385 | compatible = "regulator-fixed"; |
386 | reg = <100>; | |
312d3732 MZ |
387 | regulator-name = "+V1.8_AVDD_HDMI_PLL"; |
388 | regulator-min-microvolt = <1800000>; | |
389 | regulator-max-microvolt = <1800000>; | |
390 | enable-active-high; | |
391 | gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; | |
392 | vin-supply = <&vio_reg>; | |
393 | }; | |
394 | ||
395 | sys_3v3_reg: regulator@101 { | |
396 | compatible = "regulator-fixed"; | |
397 | reg = <101>; | |
446e9c63 SA |
398 | regulator-name = "3v3"; |
399 | regulator-min-microvolt = <3300000>; | |
400 | regulator-max-microvolt = <3300000>; | |
401 | regulator-always-on; | |
402 | }; | |
caa9eac5 | 403 | |
312d3732 | 404 | avdd_hdmi_3v3_reg: regulator@102 { |
caa9eac5 | 405 | compatible = "regulator-fixed"; |
312d3732 MZ |
406 | reg = <102>; |
407 | regulator-name = "+V3.3_AVDD_HDMI"; | |
408 | regulator-min-microvolt = <3300000>; | |
409 | regulator-max-microvolt = <3300000>; | |
410 | enable-active-high; | |
411 | gpio = <&pmic 6 GPIO_ACTIVE_HIGH>; | |
412 | vin-supply = <&sys_3v3_reg>; | |
413 | }; | |
414 | ||
415 | charge_pump_5v0_reg: regulator@103 { | |
416 | compatible = "regulator-fixed"; | |
417 | reg = <103>; | |
caa9eac5 MZ |
418 | regulator-name = "5v0"; |
419 | regulator-min-microvolt = <5000000>; | |
420 | regulator-max-microvolt = <5000000>; | |
421 | regulator-always-on; | |
422 | }; | |
446e9c63 SA |
423 | }; |
424 | }; |