[deliverable/linux.git] / arch / arm / boot / dts / tegra30.dtsi

/include/ "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra30";
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &uarta;
		serial1 = &uartb;
		serial2 = &uartc;
		serial3 = &uartd;
		serial4 = &uarte;
	};

	host1x {
		compatible = "nvidia,tegra30-host1x", "simple-bus";
		reg = <0x50000000 0x00024000>;
		interrupts = <0 65 0x04   /* mpcore syncpt */
			      0 67 0x04>; /* mpcore general */
		clocks = <&tegra_car 28>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe {
			compatible = "nvidia,tegra30-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <0 68 0x04>;
			clocks = <&tegra_car 60>;
		};

		vi {
			compatible = "nvidia,tegra30-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <0 69 0x04>;
			clocks = <&tegra_car 164>;
		};

		epp {
			compatible = "nvidia,tegra30-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <0 70 0x04>;
			clocks = <&tegra_car 19>;
		};

		isp {
			compatible = "nvidia,tegra30-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <0 71 0x04>;
			clocks = <&tegra_car 23>;
		};

		gr2d {
			compatible = "nvidia,tegra30-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <0 72 0x04>;
			clocks = <&tegra_car 21>;
		};

		gr3d {
			compatible = "nvidia,tegra30-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car 24 &tegra_car 98>;
			clock-names = "3d", "3d2";
		};

		dc@54200000 {
			compatible = "nvidia,tegra30-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <0 73 0x04>;
			clocks = <&tegra_car 27>, <&tegra_car 179>;
			clock-names = "disp1", "parent";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra30-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <0 74 0x04>;
			clocks = <&tegra_car 26>, <&tegra_car 179>;
			clock-names = "disp2", "parent";

			rgb {
				status = "disabled";
			};
		};

		hdmi {
			compatible = "nvidia,tegra30-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <0 75 0x04>;
			clocks = <&tegra_car 51>, <&tegra_car 189>;
			clock-names = "hdmi", "parent";
			status = "disabled";
		};

		tvo {
			compatible = "nvidia,tegra30-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <0 76 0x04>;
			clocks = <&tegra_car 169>;
			status = "disabled";
		};

		dsi {
			compatible = "nvidia,tegra30-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car 48>;
			status = "disabled";
		};
	};

	timer@50004600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x50040600 0x20>;
		interrupts = <1 13 0xf04>;
	};

	intc: interrupt-controller {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0x50043000 0x1000>;
		arm,data-latency = <6 6 2>;
		arm,tag-latency = <5 5 2>;
		cache-unified;
		cache-level = <2>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
		reg = <0x60005000 0x400>;
		interrupts = <0 0 0x04
			      0 1 0x04
			      0 41 0x04
			      0 42 0x04
			      0 121 0x04
			      0 122 0x04>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra30-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1400>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04
			      0 128 0x04
			      0 129 0x04
			      0 130 0x04
			      0 131 0x04
			      0 132 0x04
			      0 133 0x04
			      0 134 0x04
			      0 135 0x04
			      0 136 0x04
			      0 137 0x04
			      0 138 0x04
			      0 139 0x04
			      0 140 0x04
			      0 141 0x04
			      0 142 0x04
			      0 143 0x04>;
		clocks = <&tegra_car 34>;
	};

	ahb: ahb {
		compatible = "nvidia,tegra30-ahb";
		reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio {
		compatible = "nvidia,tegra30-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <0 32 0x04
			      0 33 0x04
			      0 34 0x04
			      0 35 0x04
			      0 55 0x04
			      0 87 0x04
			      0 89 0x04
			      0 125 0x04>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra30-pinmux";
		reg = <0x70000868 0xd4    /* Pad control registers */
		       0x70003000 0x3e4>; /* Mux registers */
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
	 * the APB DMA based serial driver, the comptible is
	 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <0 36 0x04>;
		nvidia,dma-request-selector = <&apbdma 8>;
		clocks = <&tegra_car 6>;
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <0 37 0x04>;
		nvidia,dma-request-selector = <&apbdma 9>;
		clocks = <&tegra_car 160>;
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <0 46 0x04>;
		nvidia,dma-request-selector = <&apbdma 10>;
		clocks = <&tegra_car 55>;
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <0 90 0x04>;
		nvidia,dma-request-selector = <&apbdma 19>;
		clocks = <&tegra_car 65>;
		status = "disabled";
	};

	uarte: serial@70006400 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <0 91 0x04>;
		nvidia,dma-request-selector = <&apbdma 20>;
		clocks = <&tegra_car 66>;
		status = "disabled";
	};

	pwm: pwm {
		compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car 17>;
	};

	rtc {
		compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <0 2 0x04>;
	};

	i2c@7000c000 {
		compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <0 38 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <0 84 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <0 92 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c700 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c700 0x100>;
		interrupts = <0 120 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 103>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000d000 0x100>;
		interrupts = <0 53 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d400 0x200>;
		interrupts = <0 59 0x04>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 41>;
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d600 0x200>;
		interrupts = <0 82 0x04>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 44>;
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d480 0x200>;
		interrupts = <0 83 0x04>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 46>;
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000da00 0x200>;
		interrupts = <0 93 0x04>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 68>;
		status = "disabled";
	};

	spi@7000dc00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000dc00 0x200>;
		interrupts = <0 94 0x04>;
		nvidia,dma-request-selector = <&apbdma 27>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 104>;
		status = "disabled";
	};

	spi@7000de00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000de00 0x200>;
		interrupts = <0 79 0x04>;
		nvidia,dma-request-selector = <&apbdma 28>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 105>;
		status = "disabled";
	};

	kbc {
		compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
		reg = <0x7000e200 0x100>;
		interrupts = <0 85 0x04>;
		clocks = <&tegra_car 36>;
		status = "disabled";
	};

	pmc {
		compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
		reg = <0x7000e400 0x400>;
	};

	memory-controller {
		compatible = "nvidia,tegra30-mc";
		reg = <0x7000f000 0x010
		       0x7000f03c 0x1b4
		       0x7000f200 0x028
		       0x7000f284 0x17c>;
		interrupts = <0 77 0x04>;
	};

	iommu {
		compatible = "nvidia,tegra30-smmu";
		reg = <0x7000f010 0x02c
		       0x7000f1f0 0x010
		       0x7000f228 0x05c>;
		nvidia,#asids = <4>;		/* # of ASIDs */
		dma-window = <0 0x40000000>;	/* IOVA start & length */
		nvidia,ahb = <&ahb>;
	};

	ahub {
		compatible = "nvidia,tegra30-ahub";
		reg = <0x70080000 0x200
		       0x70080200 0x100>;
		interrupts = <0 103 0x04>;
		nvidia,dma-request-selector = <&apbdma 1>;
		clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
			 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
			 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
			 <&tegra_car 110>, <&tegra_car 162>;
		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
			      "spdif_in";
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;

		tegra_i2s0: i2s@70080300 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080300 0x100>;
			nvidia,ahub-cif-ids = <4 4>;
			clocks = <&tegra_car 30>;
			status = "disabled";
		};

		tegra_i2s1: i2s@70080400 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080400 0x100>;
			nvidia,ahub-cif-ids = <5 5>;
			clocks = <&tegra_car 11>;
			status = "disabled";
		};

		tegra_i2s2: i2s@70080500 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080500 0x100>;
			nvidia,ahub-cif-ids = <6 6>;
			clocks = <&tegra_car 18>;
			status = "disabled";
		};

		tegra_i2s3: i2s@70080600 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080600 0x100>;
			nvidia,ahub-cif-ids = <7 7>;
			clocks = <&tegra_car 101>;
			status = "disabled";
		};

		tegra_i2s4: i2s@70080700 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080700 0x100>;
			nvidia,ahub-cif-ids = <8 8>;
			clocks = <&tegra_car 102>;
			status = "disabled";
		};
	};

	sdhci@78000000 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000000 0x200>;
		interrupts = <0 14 0x04>;
		clocks = <&tegra_car 14>;
		status = "disabled";
	};

	sdhci@78000200 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000200 0x200>;
		interrupts = <0 15 0x04>;
		clocks = <&tegra_car 9>;
		status = "disabled";
	};

	sdhci@78000400 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000400 0x200>;
		interrupts = <0 19 0x04>;
		clocks = <&tegra_car 69>;
		status = "disabled";
	};

	sdhci@78000600 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000600 0x200>;
		interrupts = <0 31 0x04>;
		clocks = <&tegra_car 15>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 144 0x04
			      0 145 0x04
			      0 146 0x04
			      0 147 0x04>;
	};
};
Commit	Line	Data
c3e00a0e PDS	1	/include/ "skeleton.dtsi"
	2
	3	/ {
	4	compatible = "nvidia,tegra30";
	5	interrupt-parent = <&intc>;
	6
b6551bb9 LD	7	aliases {
	8	serial0 = &uarta;
	9	serial1 = &uartb;
	10	serial2 = &uartc;
	11	serial3 = &uartd;
	12	serial4 = &uarte;
	13	};
	14
ed39097c TR	15	host1x {
	16	compatible = "nvidia,tegra30-host1x", "simple-bus";
	17	reg = <0x50000000 0x00024000>;
	18	interrupts = <0 65 0x04 /* mpcore syncpt */
	19	0 67 0x04>; /* mpcore general */
1cbc733d	20	clocks = <&tegra_car 28>;
ed39097c TR	21
	22	#address-cells = <1>;
	23	#size-cells = <1>;
	24
	25	ranges = <0x54000000 0x54000000 0x04000000>;
	26
	27	mpe {
	28	compatible = "nvidia,tegra30-mpe";
	29	reg = <0x54040000 0x00040000>;
	30	interrupts = <0 68 0x04>;
1cbc733d	31	clocks = <&tegra_car 60>;
ed39097c TR	32	};
	33
	34	vi {
	35	compatible = "nvidia,tegra30-vi";
	36	reg = <0x54080000 0x00040000>;
	37	interrupts = <0 69 0x04>;
1cbc733d	38	clocks = <&tegra_car 164>;
ed39097c TR	39	};
	40
	41	epp {
	42	compatible = "nvidia,tegra30-epp";
	43	reg = <0x540c0000 0x00040000>;
	44	interrupts = <0 70 0x04>;
1cbc733d	45	clocks = <&tegra_car 19>;
ed39097c TR	46	};
	47
	48	isp {
	49	compatible = "nvidia,tegra30-isp";
	50	reg = <0x54100000 0x00040000>;
	51	interrupts = <0 71 0x04>;
1cbc733d	52	clocks = <&tegra_car 23>;
ed39097c TR	53	};
	54
	55	gr2d {
	56	compatible = "nvidia,tegra30-gr2d";
	57	reg = <0x54140000 0x00040000>;
	58	interrupts = <0 72 0x04>;
1cbc733d	59	clocks = <&tegra_car 21>;
ed39097c TR	60	};
	61
	62	gr3d {
	63	compatible = "nvidia,tegra30-gr3d";
	64	reg = <0x54180000 0x00040000>;
1cbc733d PG	65	clocks = <&tegra_car 24 &tegra_car 98>;
1cbc733d PG	66	clock-names = "3d", "3d2";
ed39097c TR	67	};
	68
	69	dc@54200000 {
	70	compatible = "nvidia,tegra30-dc";
	71	reg = <0x54200000 0x00040000>;
	72	interrupts = <0 73 0x04>;
1cbc733d PG	73	clocks = <&tegra_car 27>, <&tegra_car 179>;
1cbc733d PG	74	clock-names = "disp1", "parent";
ed39097c TR	75
	76	rgb {
	77	status = "disabled";
	78	};
	79	};
	80
	81	dc@54240000 {
	82	compatible = "nvidia,tegra30-dc";
	83	reg = <0x54240000 0x00040000>;
	84	interrupts = <0 74 0x04>;
1cbc733d PG	85	clocks = <&tegra_car 26>, <&tegra_car 179>;
1cbc733d PG	86	clock-names = "disp2", "parent";
ed39097c TR	87
	88	rgb {
	89	status = "disabled";
	90	};
	91	};
	92
	93	hdmi {
	94	compatible = "nvidia,tegra30-hdmi";
	95	reg = <0x54280000 0x00040000>;
	96	interrupts = <0 75 0x04>;
1cbc733d PG	97	clocks = <&tegra_car 51>, <&tegra_car 189>;
1cbc733d PG	98	clock-names = "hdmi", "parent";
ed39097c TR	99	status = "disabled";
	100	};
	101
	102	tvo {
	103	compatible = "nvidia,tegra30-tvo";
	104	reg = <0x542c0000 0x00040000>;
	105	interrupts = <0 76 0x04>;
1cbc733d	106	clocks = <&tegra_car 169>;
ed39097c TR	107	status = "disabled";
	108	};
	109
	110	dsi {
	111	compatible = "nvidia,tegra30-dsi";
	112	reg = <0x54300000 0x00040000>;
1cbc733d	113	clocks = <&tegra_car 48>;
ed39097c TR	114	status = "disabled";
	115	};
	116	};
	117
73368ba0 SW	118	timer@50004600 {
	119	compatible = "arm,cortex-a9-twd-timer";
	120	reg = <0x50040600 0x20>;
	121	interrupts = <1 13 0xf04>;
	122	};
	123
f9eb26a4	124	intc: interrupt-controller {
c3e00a0e	125	compatible = "arm,cortex-a9-gic";
5ff48887 SW	126	reg = <0x50041000 0x1000
5ff48887 SW	127	0x50040100 0x0100>;
2eaab06e SW	128	interrupt-controller;
2eaab06e SW	129	#interrupt-cells = <3>;
c3e00a0e PDS	130	};
c3e00a0e PDS	131
bb2c1de9 SW	132	cache-controller {
	133	compatible = "arm,pl310-cache";
	134	reg = <0x50043000 0x1000>;
	135	arm,data-latency = <6 6 2>;
	136	arm,tag-latency = <5 5 2>;
	137	cache-unified;
	138	cache-level = <2>;
	139	};
	140
2f2b7fb2 SW	141	timer@60005000 {
	142	compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
	143	reg = <0x60005000 0x400>;
	144	interrupts = <0 0 0x04
	145	0 1 0x04
	146	0 41 0x04
	147	0 42 0x04
	148	0 121 0x04
	149	0 122 0x04>;
	150	};
	151
95985667 PG	152	tegra_car: clock {
	153	compatible = "nvidia,tegra30-car";
	154	reg = <0x60006000 0x1000>;
	155	#clock-cells = <1>;
	156	};
	157
f9eb26a4	158	apbdma: dma {
8051b75a SW	159	compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
8051b75a SW	160	reg = <0x6000a000 0x1400>;
95decf84 SW	161	interrupts = <0 104 0x04
	162	0 105 0x04
	163	0 106 0x04
	164	0 107 0x04
	165	0 108 0x04
	166	0 109 0x04
	167	0 110 0x04
	168	0 111 0x04
	169	0 112 0x04
	170	0 113 0x04
	171	0 114 0x04
	172	0 115 0x04
	173	0 116 0x04
	174	0 117 0x04
	175	0 118 0x04
	176	0 119 0x04
	177	0 128 0x04
	178	0 129 0x04
	179	0 130 0x04
	180	0 131 0x04
	181	0 132 0x04
	182	0 133 0x04
	183	0 134 0x04
	184	0 135 0x04
	185	0 136 0x04
	186	0 137 0x04
	187	0 138 0x04
	188	0 139 0x04
	189	0 140 0x04
	190	0 141 0x04
	191	0 142 0x04
	192	0 143 0x04>;
1cbc733d	193	clocks = <&tegra_car 34>;
8051b75a SW	194	};
8051b75a SW	195
c04abb3a SW	196	ahb: ahb {
	197	compatible = "nvidia,tegra30-ahb";
	198	reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e PDS	199	};
c3e00a0e PDS	200
f9eb26a4	201	gpio: gpio {
35f210ec	202	compatible = "nvidia,tegra30-gpio";
95decf84 SW	203	reg = <0x6000d000 0x1000>;
	204	interrupts = <0 32 0x04
	205	0 33 0x04
	206	0 34 0x04
	207	0 35 0x04
	208	0 55 0x04
	209	0 87 0x04
	210	0 89 0x04
	211	0 125 0x04>;
c3e00a0e PDS	212	#gpio-cells = <2>;
c3e00a0e PDS	213	gpio-controller;
6f74dc9b SW	214	#interrupt-cells = <2>;
6f74dc9b SW	215	interrupt-controller;
c3e00a0e PDS	216	};
c3e00a0e PDS	217
c04abb3a SW	218	pinmux: pinmux {
c04abb3a SW	219	compatible = "nvidia,tegra30-pinmux";
322337b8 PR	220	reg = <0x70000868 0xd4 /* Pad control registers */
322337b8 PR	221	0x70003000 0x3e4>; /* Mux registers */
c04abb3a SW	222	};
c04abb3a SW	223
b6551bb9 LD	224	/*
	225	* There are two serial driver i.e. 8250 based simple serial
	226	* driver and APB DMA based serial driver for higher baudrate
	227	* and performace. To enable the 8250 based driver, the compatible
	228	* is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
	229	* the APB DMA based serial driver, the comptible is
	230	* "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
	231	*/
	232	uarta: serial@70006000 {
c3e00a0e PDS	233	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	234	reg = <0x70006000 0x40>;
	235	reg-shift = <2>;
95decf84	236	interrupts = <0 36 0x04>;
b6551bb9	237	nvidia,dma-request-selector = <&apbdma 8>;
1cbc733d	238	clocks = <&tegra_car 6>;
223ef78d	239	status = "disabled";
c3e00a0e PDS	240	};
c3e00a0e PDS	241
b6551bb9	242	uartb: serial@70006040 {
c3e00a0e PDS	243	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	244	reg = <0x70006040 0x40>;
	245	reg-shift = <2>;
95decf84	246	interrupts = <0 37 0x04>;
b6551bb9	247	nvidia,dma-request-selector = <&apbdma 9>;
1cbc733d	248	clocks = <&tegra_car 160>;
223ef78d	249	status = "disabled";
c3e00a0e PDS	250	};
c3e00a0e PDS	251
b6551bb9	252	uartc: serial@70006200 {
c3e00a0e PDS	253	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	254	reg = <0x70006200 0x100>;
	255	reg-shift = <2>;
95decf84	256	interrupts = <0 46 0x04>;
b6551bb9	257	nvidia,dma-request-selector = <&apbdma 10>;
1cbc733d	258	clocks = <&tegra_car 55>;
223ef78d	259	status = "disabled";
c3e00a0e PDS	260	};
c3e00a0e PDS	261
b6551bb9	262	uartd: serial@70006300 {
c3e00a0e PDS	263	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	264	reg = <0x70006300 0x100>;
	265	reg-shift = <2>;
95decf84	266	interrupts = <0 90 0x04>;
b6551bb9	267	nvidia,dma-request-selector = <&apbdma 19>;
1cbc733d	268	clocks = <&tegra_car 65>;
223ef78d	269	status = "disabled";
c3e00a0e PDS	270	};
c3e00a0e PDS	271
b6551bb9	272	uarte: serial@70006400 {
c3e00a0e PDS	273	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	274	reg = <0x70006400 0x100>;
	275	reg-shift = <2>;
95decf84	276	interrupts = <0 91 0x04>;
b6551bb9	277	nvidia,dma-request-selector = <&apbdma 20>;
1cbc733d	278	clocks = <&tegra_car 66>;
223ef78d	279	status = "disabled";
c3e00a0e PDS	280	};
c3e00a0e PDS	281
2b8b15da	282	pwm: pwm {
140fd977 TR	283	compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
	284	reg = <0x7000a000 0x100>;
	285	#pwm-cells = <2>;
1cbc733d	286	clocks = <&tegra_car 17>;
140fd977 TR	287	};
140fd977 TR	288
380e04ac SW	289	rtc {
	290	compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
	291	reg = <0x7000e000 0x100>;
	292	interrupts = <0 2 0x04>;
	293	};
	294
c04abb3a	295	i2c@7000c000 {
c04abb3a SW	296	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	297	reg = <0x7000c000 0x100>;
	298	interrupts = <0 38 0x04>;
2eaab06e SW	299	#address-cells = <1>;
2eaab06e SW	300	#size-cells = <0>;
1cbc733d PG	301	clocks = <&tegra_car 12>, <&tegra_car 182>;
1cbc733d PG	302	clock-names = "div-clk", "fast-clk";
223ef78d	303	status = "disabled";
c3e00a0e PDS	304	};
c3e00a0e PDS	305
c04abb3a	306	i2c@7000c400 {
c04abb3a SW	307	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	308	reg = <0x7000c400 0x100>;
	309	interrupts = <0 84 0x04>;
2eaab06e SW	310	#address-cells = <1>;
2eaab06e SW	311	#size-cells = <0>;
1cbc733d PG	312	clocks = <&tegra_car 54>, <&tegra_car 182>;
1cbc733d PG	313	clock-names = "div-clk", "fast-clk";
223ef78d	314	status = "disabled";
c3e00a0e PDS	315	};
c3e00a0e PDS	316
c04abb3a	317	i2c@7000c500 {
c04abb3a SW	318	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	319	reg = <0x7000c500 0x100>;
	320	interrupts = <0 92 0x04>;
2eaab06e SW	321	#address-cells = <1>;
2eaab06e SW	322	#size-cells = <0>;
1cbc733d PG	323	clocks = <&tegra_car 67>, <&tegra_car 182>;
1cbc733d PG	324	clock-names = "div-clk", "fast-clk";
223ef78d	325	status = "disabled";
c3e00a0e PDS	326	};
c3e00a0e PDS	327
c04abb3a	328	i2c@7000c700 {
c04abb3a SW	329	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	330	reg = <0x7000c700 0x100>;
	331	interrupts = <0 120 0x04>;
2eaab06e SW	332	#address-cells = <1>;
2eaab06e SW	333	#size-cells = <0>;
1cbc733d PG	334	clocks = <&tegra_car 103>, <&tegra_car 182>;
1cbc733d PG	335	clock-names = "div-clk", "fast-clk";
223ef78d	336	status = "disabled";
c3e00a0e PDS	337	};
c3e00a0e PDS	338
c04abb3a	339	i2c@7000d000 {
c04abb3a SW	340	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	341	reg = <0x7000d000 0x100>;
	342	interrupts = <0 53 0x04>;
2eaab06e SW	343	#address-cells = <1>;
2eaab06e SW	344	#size-cells = <0>;
1cbc733d PG	345	clocks = <&tegra_car 47>, <&tegra_car 182>;
1cbc733d PG	346	clock-names = "div-clk", "fast-clk";
223ef78d	347	status = "disabled";
c04abb3a SW	348	};
c04abb3a SW	349
a86b0db3 LD	350	spi@7000d400 {
	351	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	352	reg = <0x7000d400 0x200>;
	353	interrupts = <0 59 0x04>;
	354	nvidia,dma-request-selector = <&apbdma 15>;
	355	#address-cells = <1>;
	356	#size-cells = <0>;
1cbc733d	357	clocks = <&tegra_car 41>;
a86b0db3 LD	358	status = "disabled";
	359	};
	360
	361	spi@7000d600 {
	362	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	363	reg = <0x7000d600 0x200>;
	364	interrupts = <0 82 0x04>;
	365	nvidia,dma-request-selector = <&apbdma 16>;
	366	#address-cells = <1>;
	367	#size-cells = <0>;
1cbc733d	368	clocks = <&tegra_car 44>;
a86b0db3 LD	369	status = "disabled";
	370	};
	371
	372	spi@7000d800 {
	373	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	374	reg = <0x7000d480 0x200>;
	375	interrupts = <0 83 0x04>;
	376	nvidia,dma-request-selector = <&apbdma 17>;
	377	#address-cells = <1>;
	378	#size-cells = <0>;
1cbc733d	379	clocks = <&tegra_car 46>;
a86b0db3 LD	380	status = "disabled";
	381	};
	382
	383	spi@7000da00 {
	384	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	385	reg = <0x7000da00 0x200>;
	386	interrupts = <0 93 0x04>;
	387	nvidia,dma-request-selector = <&apbdma 18>;
	388	#address-cells = <1>;
	389	#size-cells = <0>;
1cbc733d	390	clocks = <&tegra_car 68>;
a86b0db3 LD	391	status = "disabled";
	392	};
	393
	394	spi@7000dc00 {
	395	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	396	reg = <0x7000dc00 0x200>;
	397	interrupts = <0 94 0x04>;
	398	nvidia,dma-request-selector = <&apbdma 27>;
	399	#address-cells = <1>;
	400	#size-cells = <0>;
1cbc733d	401	clocks = <&tegra_car 104>;
a86b0db3 LD	402	status = "disabled";
	403	};
	404
	405	spi@7000de00 {
	406	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	407	reg = <0x7000de00 0x200>;
	408	interrupts = <0 79 0x04>;
	409	nvidia,dma-request-selector = <&apbdma 28>;
	410	#address-cells = <1>;
	411	#size-cells = <0>;
1cbc733d	412	clocks = <&tegra_car 105>;
a86b0db3 LD	413	status = "disabled";
	414	};
	415
699ed4b9 LD	416	kbc {
	417	compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
	418	reg = <0x7000e200 0x100>;
	419	interrupts = <0 85 0x04>;
	420	clocks = <&tegra_car 36>;
	421	status = "disabled";
	422	};
	423
c04abb3a SW	424	pmc {
	425	compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
	426	reg = <0x7000e400 0x400>;
	427	};
	428
a9140aa5	429	memory-controller {
c04abb3a SW	430	compatible = "nvidia,tegra30-mc";
	431	reg = <0x7000f000 0x010
	432	0x7000f03c 0x1b4
	433	0x7000f200 0x028
	434	0x7000f284 0x17c>;
	435	interrupts = <0 77 0x04>;
	436	};
	437
3fbf07d8	438	iommu {
c04abb3a SW	439	compatible = "nvidia,tegra30-smmu";
	440	reg = <0x7000f010 0x02c
	441	0x7000f1f0 0x010
	442	0x7000f228 0x05c>;
	443	nvidia,#asids = <4>; /* # of ASIDs */
	444	dma-window = <0 0x40000000>; /* IOVA start & length */
	445	nvidia,ahb = <&ahb>;
c3e00a0e	446	};
9ee6a5c4 SW	447
	448	ahub {
	449	compatible = "nvidia,tegra30-ahub";
5ff48887 SW	450	reg = <0x70080000 0x200
5ff48887 SW	451	0x70080200 0x100>;
95decf84	452	interrupts = <0 103 0x04>;
9ee6a5c4	453	nvidia,dma-request-selector = <&apbdma 1>;
1cbc733d PG	454	clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
	455	<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
	456	<&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
	457	<&tegra_car 110>, <&tegra_car 162>;
	458	clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
	459	"i2s3", "i2s4", "dam0", "dam1", "dam2",
	460	"spdif_in";
9ee6a5c4 SW	461	ranges;
	462	#address-cells = <1>;
	463	#size-cells = <1>;
	464
	465	tegra_i2s0: i2s@70080300 {
	466	compatible = "nvidia,tegra30-i2s";
	467	reg = <0x70080300 0x100>;
	468	nvidia,ahub-cif-ids = <4 4>;
1cbc733d	469	clocks = <&tegra_car 30>;
223ef78d	470	status = "disabled";
9ee6a5c4 SW	471	};
	472
	473	tegra_i2s1: i2s@70080400 {
	474	compatible = "nvidia,tegra30-i2s";
	475	reg = <0x70080400 0x100>;
	476	nvidia,ahub-cif-ids = <5 5>;
1cbc733d	477	clocks = <&tegra_car 11>;
223ef78d	478	status = "disabled";
9ee6a5c4 SW	479	};
	480
	481	tegra_i2s2: i2s@70080500 {
	482	compatible = "nvidia,tegra30-i2s";
	483	reg = <0x70080500 0x100>;
	484	nvidia,ahub-cif-ids = <6 6>;
1cbc733d	485	clocks = <&tegra_car 18>;
223ef78d	486	status = "disabled";
9ee6a5c4 SW	487	};
	488
	489	tegra_i2s3: i2s@70080600 {
	490	compatible = "nvidia,tegra30-i2s";
	491	reg = <0x70080600 0x100>;
	492	nvidia,ahub-cif-ids = <7 7>;
1cbc733d	493	clocks = <&tegra_car 101>;
223ef78d	494	status = "disabled";
9ee6a5c4 SW	495	};
	496
	497	tegra_i2s4: i2s@70080700 {
	498	compatible = "nvidia,tegra30-i2s";
	499	reg = <0x70080700 0x100>;
	500	nvidia,ahub-cif-ids = <8 8>;
1cbc733d	501	clocks = <&tegra_car 102>;
223ef78d	502	status = "disabled";
9ee6a5c4 SW	503	};
9ee6a5c4 SW	504	};
7868a9bc	505
c04abb3a SW	506	sdhci@78000000 {
	507	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	508	reg = <0x78000000 0x200>;
	509	interrupts = <0 14 0x04>;
1cbc733d	510	clocks = <&tegra_car 14>;
223ef78d	511	status = "disabled";
7868a9bc	512	};
ecf43742	513
c04abb3a SW	514	sdhci@78000200 {
	515	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	516	reg = <0x78000200 0x200>;
	517	interrupts = <0 15 0x04>;
1cbc733d	518	clocks = <&tegra_car 9>;
223ef78d	519	status = "disabled";
ecf43742	520	};
54174a33	521
c04abb3a SW	522	sdhci@78000400 {
	523	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	524	reg = <0x78000400 0x200>;
	525	interrupts = <0 19 0x04>;
1cbc733d	526	clocks = <&tegra_car 69>;
223ef78d	527	status = "disabled";
c04abb3a SW	528	};
	529
	530	sdhci@78000600 {
	531	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	532	reg = <0x78000600 0x200>;
	533	interrupts = <0 31 0x04>;
1cbc733d	534	clocks = <&tegra_car 15>;
223ef78d	535	status = "disabled";
c04abb3a SW	536	};
c04abb3a SW	537
7d19a34a HD	538	cpus {
	539	#address-cells = <1>;
	540	#size-cells = <0>;
	541
	542	cpu@0 {
	543	device_type = "cpu";
	544	compatible = "arm,cortex-a9";
	545	reg = <0>;
	546	};
	547
	548	cpu@1 {
	549	device_type = "cpu";
	550	compatible = "arm,cortex-a9";
	551	reg = <1>;
	552	};
	553
	554	cpu@2 {
	555	device_type = "cpu";
	556	compatible = "arm,cortex-a9";
	557	reg = <2>;
	558	};
	559
	560	cpu@3 {
	561	device_type = "cpu";
	562	compatible = "arm,cortex-a9";
	563	reg = <3>;
	564	};
	565	};
	566
c04abb3a SW	567	pmu {
	568	compatible = "arm,cortex-a9-pmu";
	569	interrupts = <0 144 0x04
	570	0 145 0x04
	571	0 146 0x04
	572	0 147 0x04>;
54174a33	573	};
c3e00a0e	574	};