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Merge tag 'armsoc-cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
[deliverable/linux.git] / arch / arm / boot / dts / tegra30.dtsi
CommitLineData
05849c93 1#include <dt-bindings/clock/tegra30-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
6d9adf6f 3#include <dt-bindings/memory/tegra30-mc.h>
a47c662a 4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 5#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 6
1bd0bd49 7#include "skeleton.dtsi"
c3e00a0e
PDS		 8
9/ {
10 compatible = "nvidia,tegra30";
870c81a4 11 interrupt-parent = <&lic>;
c3e00a0e 12
58ecb23f 13 pcie-controller@00003000 {
e07e3dbd
TR		 14 compatible = "nvidia,tegra30-pcie";
15 device_type = "pci";
16 reg = <0x00003000 0x00000800 /* PADS registers */
17 0x00003800 0x00000200 /* AFI registers */
18 0x10000000 0x10000000>; /* configuration space */
19 reg-names = "pads", "afi", "cs";
20 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
21 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
22 interrupt-names = "intr", "msi";
23
97070bd4
LS		 24 #interrupt-cells = <1>;
25 interrupt-map-mask = <0 0 0 0>;
26 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
27
e07e3dbd
TR		 28 bus-range = <0x00 0xff>;
29 #address-cells = <3>;
30 #size-cells = <2>;
31
32 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
33 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
34 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
35 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 36 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
37 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
e07e3dbd
TR		 38
39 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
40 <&tegra_car TEGRA30_CLK_AFI>,
e07e3dbd
TR		 41 <&tegra_car TEGRA30_CLK_PLL_E>,
42 <&tegra_car TEGRA30_CLK_CML0>;
2bd541ff 43 clock-names = "pex", "afi", "pll_e", "cml";
3393d422
SW		 44 resets = <&tegra_car 70>,
45 <&tegra_car 72>,
46 <&tegra_car 74>;
47 reset-names = "pex", "afi", "pcie_x";
e07e3dbd
TR		 48 status = "disabled";
49
50 pci@1,0 {
51 device_type = "pci";
52 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
53 reg = <0x000800 0 0 0 0>;
54 status = "disabled";
55
56 #address-cells = <3>;
57 #size-cells = <2>;
58 ranges;
59
60 nvidia,num-lanes = <2>;
61 };
62
63 pci@2,0 {
64 device_type = "pci";
65 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
66 reg = <0x001000 0 0 0 0>;
67 status = "disabled";
68
69 #address-cells = <3>;
70 #size-cells = <2>;
71 ranges;
72
73 nvidia,num-lanes = <2>;
74 };
75
76 pci@3,0 {
77 device_type = "pci";
78 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
79 reg = <0x001800 0 0 0 0>;
80 status = "disabled";
81
82 #address-cells = <3>;
83 #size-cells = <2>;
84 ranges;
85
86 nvidia,num-lanes = <2>;
87 };
88 };
89
58ecb23f 90 host1x@50000000 {
ed39097c
TR		 91 compatible = "nvidia,tegra30-host1x", "simple-bus";
92 reg = <0x50000000 0x00024000>;
6cecf916
SW		 93 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
94 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
05849c93 95 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
3393d422
SW		 96 resets = <&tegra_car 28>;
97 reset-names = "host1x";
ed39097c
TR		 98
99 #address-cells = <1>;
100 #size-cells = <1>;
101
102 ranges = <0x54000000 0x54000000 0x04000000>;
103
58ecb23f 104 mpe@54040000 {
ed39097c
TR		 105 compatible = "nvidia,tegra30-mpe";
106 reg = <0x54040000 0x00040000>;
6cecf916 107 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
05849c93 108 clocks = <&tegra_car TEGRA30_CLK_MPE>;
3393d422
SW		 109 resets = <&tegra_car 60>;
110 reset-names = "mpe";
ed39097c
TR		 111 };
112
58ecb23f 113 vi@54080000 {
ed39097c
TR		 114 compatible = "nvidia,tegra30-vi";
115 reg = <0x54080000 0x00040000>;
6cecf916 116 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
05849c93 117 clocks = <&tegra_car TEGRA30_CLK_VI>;
3393d422
SW		 118 resets = <&tegra_car 20>;
119 reset-names = "vi";
ed39097c
TR		 120 };
121
58ecb23f 122 epp@540c0000 {
ed39097c
TR		 123 compatible = "nvidia,tegra30-epp";
124 reg = <0x540c0000 0x00040000>;
6cecf916 125 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
05849c93 126 clocks = <&tegra_car TEGRA30_CLK_EPP>;
3393d422
SW		 127 resets = <&tegra_car 19>;
128 reset-names = "epp";
ed39097c
TR		 129 };
130
58ecb23f 131 isp@54100000 {
ed39097c
TR		 132 compatible = "nvidia,tegra30-isp";
133 reg = <0x54100000 0x00040000>;
6cecf916 134 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
05849c93 135 clocks = <&tegra_car TEGRA30_CLK_ISP>;
3393d422
SW		 136 resets = <&tegra_car 23>;
137 reset-names = "isp";
ed39097c
TR		 138 };
139
58ecb23f 140 gr2d@54140000 {
ed39097c
TR		 141 compatible = "nvidia,tegra30-gr2d";
142 reg = <0x54140000 0x00040000>;
6cecf916 143 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
da45d738 144 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
3393d422
SW		 145 resets = <&tegra_car 21>;
146 reset-names = "2d";
ed39097c
TR		 147 };
148
58ecb23f 149 gr3d@54180000 {
ed39097c
TR		 150 compatible = "nvidia,tegra30-gr3d";
151 reg = <0x54180000 0x00040000>;
c71d3909
TR		 152 clocks = <&tegra_car TEGRA30_CLK_GR3D
153 &tegra_car TEGRA30_CLK_GR3D2>;
1cbc733d 154 clock-names = "3d", "3d2";
3393d422
SW		 155 resets = <&tegra_car 24>,
156 <&tegra_car 98>;
157 reset-names = "3d", "3d2";
ed39097c
TR		 158 };
159
160 dc@54200000 {
05465f4e 161 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
ed39097c 162 reg = <0x54200000 0x00040000>;
6cecf916 163 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 164 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
165 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 166 clock-names = "dc", "parent";
3393d422
SW		 167 resets = <&tegra_car 27>;
168 reset-names = "dc";
ed39097c 169
6d9adf6f
TR		 170 iommus = <&mc TEGRA_SWGROUP_DC>;
171
688b56b4
TR		 172 nvidia,head = <0>;
173
ed39097c
TR		 174 rgb {
175 status = "disabled";
176 };
177 };
178
179 dc@54240000 {
180 compatible = "nvidia,tegra30-dc";
181 reg = <0x54240000 0x00040000>;
6cecf916 182 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 183 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
184 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 185 clock-names = "dc", "parent";
3393d422
SW		 186 resets = <&tegra_car 26>;
187 reset-names = "dc";
ed39097c 188
6d9adf6f
TR		 189 iommus = <&mc TEGRA_SWGROUP_DCB>;
190
688b56b4
TR		 191 nvidia,head = <1>;
192
ed39097c
TR		 193 rgb {
194 status = "disabled";
195 };
196 };
197
58ecb23f 198 hdmi@54280000 {
ed39097c
TR		 199 compatible = "nvidia,tegra30-hdmi";
200 reg = <0x54280000 0x00040000>;
6cecf916 201 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 202 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
203 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
1cbc733d 204 clock-names = "hdmi", "parent";
3393d422
SW		 205 resets = <&tegra_car 51>;
206 reset-names = "hdmi";
ed39097c
TR		 207 status = "disabled";
208 };
209
58ecb23f 210 tvo@542c0000 {
ed39097c
TR		 211 compatible = "nvidia,tegra30-tvo";
212 reg = <0x542c0000 0x00040000>;
6cecf916 213 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
05849c93 214 clocks = <&tegra_car TEGRA30_CLK_TVO>;
ed39097c
TR		 215 status = "disabled";
216 };
217
58ecb23f 218 dsi@54300000 {
ed39097c
TR		 219 compatible = "nvidia,tegra30-dsi";
220 reg = <0x54300000 0x00040000>;
05849c93 221 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
3393d422
SW		 222 resets = <&tegra_car 48>;
223 reset-names = "dsi";
ed39097c
TR		 224 status = "disabled";
225 };
226 };
227
2cda1880 228 timer@50040600 {
73368ba0
SW		 229 compatible = "arm,cortex-a9-twd-timer";
230 reg = <0x50040600 0x20>;
870c81a4 231 interrupt-parent = <&intc>;
6cecf916
SW		 232 interrupts = <GIC_PPI 13
233 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
05849c93 234 clocks = <&tegra_car TEGRA30_CLK_TWD>;
73368ba0
SW		 235 };
236
58ecb23f 237 intc: interrupt-controller@50041000 {
c3e00a0e 238 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 239 reg = <0x50041000 0x1000
240 0x50040100 0x0100>;
2eaab06e
SW		 241 interrupt-controller;
242 #interrupt-cells = <3>;
870c81a4 243 interrupt-parent = <&intc>;
c3e00a0e
PDS		 244 };
245
58ecb23f 246 cache-controller@50043000 {
bb2c1de9
SW		 247 compatible = "arm,pl310-cache";
248 reg = <0x50043000 0x1000>;
249 arm,data-latency = <6 6 2>;
250 arm,tag-latency = <5 5 2>;
251 cache-unified;
252 cache-level = <2>;
253 };
254
870c81a4
MZ		 255 lic: interrupt-controller@60004000 {
256 compatible = "nvidia,tegra30-ictlr";
257 reg = <0x60004000 0x100>,
258 <0x60004100 0x50>,
259 <0x60004200 0x50>,
260 <0x60004300 0x50>,
261 <0x60004400 0x50>;
262 interrupt-controller;
263 #interrupt-cells = <3>;
264 interrupt-parent = <&intc>;
265 };
266
2f2b7fb2
SW		 267 timer@60005000 {
268 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
269 reg = <0x60005000 0x400>;
6cecf916
SW		 270 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
271 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
272 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
273 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
274 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
275 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
05849c93 276 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
2f2b7fb2
SW		 277 };
278
58ecb23f 279 tegra_car: clock@60006000 {
95985667
PG		 280 compatible = "nvidia,tegra30-car";
281 reg = <0x60006000 0x1000>;
282 #clock-cells = <1>;
3393d422 283 #reset-cells = <1>;
95985667
PG		 284 };
285
b1023134
TR		 286 flow-controller@60007000 {
287 compatible = "nvidia,tegra30-flowctrl";
288 reg = <0x60007000 0x1000>;
289 };
290
58ecb23f 291 apbdma: dma@6000a000 {
8051b75a
SW		 292 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
293 reg = <0x6000a000 0x1400>;
6cecf916
SW		 294 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
312 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
313 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
314 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
315 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
316 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
317 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
318 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
319 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
320 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
321 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
322 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
323 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
324 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
325 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
05849c93 326 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
3393d422
SW		 327 resets = <&tegra_car 34>;
328 reset-names = "dma";
034d023f 329 #dma-cells = <1>;
8051b75a
SW		 330 };
331
58ecb23f 332 ahb: ahb@6000c004 {
c04abb3a
SW		 333 compatible = "nvidia,tegra30-ahb";
334 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e
PDS		 335 };
336
58ecb23f 337 gpio: gpio@6000d000 {
35f210ec 338 compatible = "nvidia,tegra30-gpio";
95decf84 339 reg = <0x6000d000 0x1000>;
6cecf916
SW		 340 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
341 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
342 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
343 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
344 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
345 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
346 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
347 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
c3e00a0e
PDS		 348 #gpio-cells = <2>;
349 gpio-controller;
6f74dc9b
SW		 350 #interrupt-cells = <2>;
351 interrupt-controller;
c3e00a0e
PDS		 352 };
353
155dfc7b
PDS		 354 apbmisc@70000800 {
355 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
356 reg = <0x70000800 0x64 /* Chip revision */
357 0x70000008 0x04>; /* Strapping options */
358 };
359
58ecb23f 360 pinmux: pinmux@70000868 {
c04abb3a 361 compatible = "nvidia,tegra30-pinmux";
322337b8
PR		 362 reg = <0x70000868 0xd4 /* Pad control registers */
363 0x70003000 0x3e4>; /* Mux registers */
c04abb3a
SW		 364 };
365
b6551bb9
LD		 366 /*
367 * There are two serial driver i.e. 8250 based simple serial
368 * driver and APB DMA based serial driver for higher baudrate
369 * and performace. To enable the 8250 based driver, the compatible
370 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
371 * the APB DMA based serial driver, the comptible is
372 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
373 */
374 uarta: serial@70006000 {
c3e00a0e
PDS		 375 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
376 reg = <0x70006000 0x40>;
377 reg-shift = <2>;
6cecf916 378 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
05849c93 379 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
3393d422
SW		 380 resets = <&tegra_car 6>;
381 reset-names = "serial";
034d023f
SW		 382 dmas = <&apbdma 8>, <&apbdma 8>;
383 dma-names = "rx", "tx";
223ef78d 384 status = "disabled";
c3e00a0e
PDS		 385 };
386
b6551bb9 387 uartb: serial@70006040 {
c3e00a0e
PDS		 388 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
389 reg = <0x70006040 0x40>;
390 reg-shift = <2>;
6cecf916 391 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
05849c93 392 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
3393d422
SW		 393 resets = <&tegra_car 7>;
394 reset-names = "serial";
034d023f
SW		 395 dmas = <&apbdma 9>, <&apbdma 9>;
396 dma-names = "rx", "tx";
223ef78d 397 status = "disabled";
c3e00a0e
PDS		 398 };
399
b6551bb9 400 uartc: serial@70006200 {
c3e00a0e
PDS		 401 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
402 reg = <0x70006200 0x100>;
403 reg-shift = <2>;
6cecf916 404 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
05849c93 405 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
3393d422
SW		 406 resets = <&tegra_car 55>;
407 reset-names = "serial";
034d023f
SW		 408 dmas = <&apbdma 10>, <&apbdma 10>;
409 dma-names = "rx", "tx";
223ef78d 410 status = "disabled";
c3e00a0e
PDS		 411 };
412
b6551bb9 413 uartd: serial@70006300 {
c3e00a0e
PDS		 414 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
415 reg = <0x70006300 0x100>;
416 reg-shift = <2>;
6cecf916 417 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
05849c93 418 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
3393d422
SW		 419 resets = <&tegra_car 65>;
420 reset-names = "serial";
034d023f
SW		 421 dmas = <&apbdma 19>, <&apbdma 19>;
422 dma-names = "rx", "tx";
223ef78d 423 status = "disabled";
c3e00a0e
PDS		 424 };
425
b6551bb9 426 uarte: serial@70006400 {
c3e00a0e
PDS		 427 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
428 reg = <0x70006400 0x100>;
429 reg-shift = <2>;
6cecf916 430 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
05849c93 431 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
3393d422
SW		 432 resets = <&tegra_car 66>;
433 reset-names = "serial";
034d023f
SW		 434 dmas = <&apbdma 20>, <&apbdma 20>;
435 dma-names = "rx", "tx";
223ef78d 436 status = "disabled";
c3e00a0e
PDS		 437 };
438
58ecb23f 439 pwm: pwm@7000a000 {
140fd977
TR		 440 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
441 reg = <0x7000a000 0x100>;
442 #pwm-cells = <2>;
05849c93 443 clocks = <&tegra_car TEGRA30_CLK_PWM>;
3393d422
SW		 444 resets = <&tegra_car 17>;
445 reset-names = "pwm";
b69cd984 446 status = "disabled";
140fd977
TR		 447 };
448
58ecb23f 449 rtc@7000e000 {
380e04ac
SW		 450 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
451 reg = <0x7000e000 0x100>;
6cecf916 452 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
05849c93 453 clocks = <&tegra_car TEGRA30_CLK_RTC>;
380e04ac
SW		 454 };
455
c04abb3a 456 i2c@7000c000 {
c04abb3a
SW		 457 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
458 reg = <0x7000c000 0x100>;
6cecf916 459 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 460 #address-cells = <1>;
461 #size-cells = <0>;
05849c93
HD		 462 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
463 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 464 clock-names = "div-clk", "fast-clk";
3393d422
SW		 465 resets = <&tegra_car 12>;
466 reset-names = "i2c";
034d023f
SW		 467 dmas = <&apbdma 21>, <&apbdma 21>;
468 dma-names = "rx", "tx";
223ef78d 469 status = "disabled";
c3e00a0e
PDS		 470 };
471
c04abb3a 472 i2c@7000c400 {
c04abb3a
SW		 473 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
474 reg = <0x7000c400 0x100>;
6cecf916 475 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 476 #address-cells = <1>;
477 #size-cells = <0>;
05849c93
HD		 478 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
479 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 480 clock-names = "div-clk", "fast-clk";
3393d422
SW		 481 resets = <&tegra_car 54>;
482 reset-names = "i2c";
034d023f
SW		 483 dmas = <&apbdma 22>, <&apbdma 22>;
484 dma-names = "rx", "tx";
223ef78d 485 status = "disabled";
c3e00a0e
PDS		 486 };
487
c04abb3a 488 i2c@7000c500 {
c04abb3a
SW		 489 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
490 reg = <0x7000c500 0x100>;
6cecf916 491 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 492 #address-cells = <1>;
493 #size-cells = <0>;
05849c93
HD		 494 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
495 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 496 clock-names = "div-clk", "fast-clk";
3393d422
SW		 497 resets = <&tegra_car 67>;
498 reset-names = "i2c";
034d023f
SW		 499 dmas = <&apbdma 23>, <&apbdma 23>;
500 dma-names = "rx", "tx";
223ef78d 501 status = "disabled";
c3e00a0e
PDS		 502 };
503
c04abb3a 504 i2c@7000c700 {
c04abb3a
SW		 505 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
506 reg = <0x7000c700 0x100>;
6cecf916 507 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 508 #address-cells = <1>;
509 #size-cells = <0>;
05849c93
HD		 510 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
511 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
3393d422
SW		 512 resets = <&tegra_car 103>;
513 reset-names = "i2c";
1cbc733d 514 clock-names = "div-clk", "fast-clk";
034d023f
SW		 515 dmas = <&apbdma 26>, <&apbdma 26>;
516 dma-names = "rx", "tx";
223ef78d 517 status = "disabled";
c3e00a0e
PDS		 518 };
519
c04abb3a 520 i2c@7000d000 {
c04abb3a
SW		 521 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
522 reg = <0x7000d000 0x100>;
6cecf916 523 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 524 #address-cells = <1>;
525 #size-cells = <0>;
05849c93
HD		 526 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
527 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 528 clock-names = "div-clk", "fast-clk";
3393d422
SW		 529 resets = <&tegra_car 47>;
530 reset-names = "i2c";
034d023f
SW		 531 dmas = <&apbdma 24>, <&apbdma 24>;
532 dma-names = "rx", "tx";
223ef78d 533 status = "disabled";
c04abb3a
SW		 534 };
535
a86b0db3
LD		 536 spi@7000d400 {
537 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
538 reg = <0x7000d400 0x200>;
6cecf916 539 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 540 #address-cells = <1>;
541 #size-cells = <0>;
05849c93 542 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
3393d422
SW		 543 resets = <&tegra_car 41>;
544 reset-names = "spi";
034d023f
SW		 545 dmas = <&apbdma 15>, <&apbdma 15>;
546 dma-names = "rx", "tx";
a86b0db3
LD		 547 status = "disabled";
548 };
549
550 spi@7000d600 {
551 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
552 reg = <0x7000d600 0x200>;
6cecf916 553 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 554 #address-cells = <1>;
555 #size-cells = <0>;
05849c93 556 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
3393d422
SW		 557 resets = <&tegra_car 44>;
558 reset-names = "spi";
034d023f
SW		 559 dmas = <&apbdma 16>, <&apbdma 16>;
560 dma-names = "rx", "tx";
a86b0db3
LD		 561 status = "disabled";
562 };
563
564 spi@7000d800 {
565 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
57471c8d 566 reg = <0x7000d800 0x200>;
6cecf916 567 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 568 #address-cells = <1>;
569 #size-cells = <0>;
05849c93 570 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
3393d422
SW		 571 resets = <&tegra_car 46>;
572 reset-names = "spi";
034d023f
SW		 573 dmas = <&apbdma 17>, <&apbdma 17>;
574 dma-names = "rx", "tx";
a86b0db3
LD		 575 status = "disabled";
576 };
577
578 spi@7000da00 {
579 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
580 reg = <0x7000da00 0x200>;
6cecf916 581 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 582 #address-cells = <1>;
583 #size-cells = <0>;
05849c93 584 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
3393d422
SW		 585 resets = <&tegra_car 68>;
586 reset-names = "spi";
034d023f
SW		 587 dmas = <&apbdma 18>, <&apbdma 18>;
588 dma-names = "rx", "tx";
a86b0db3
LD		 589 status = "disabled";
590 };
591
592 spi@7000dc00 {
593 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
594 reg = <0x7000dc00 0x200>;
6cecf916 595 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 596 #address-cells = <1>;
597 #size-cells = <0>;
05849c93 598 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
3393d422
SW		 599 resets = <&tegra_car 104>;
600 reset-names = "spi";
034d023f
SW		 601 dmas = <&apbdma 27>, <&apbdma 27>;
602 dma-names = "rx", "tx";
a86b0db3
LD		 603 status = "disabled";
604 };
605
606 spi@7000de00 {
607 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
608 reg = <0x7000de00 0x200>;
6cecf916 609 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 610 #address-cells = <1>;
611 #size-cells = <0>;
05849c93 612 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
3393d422
SW		 613 resets = <&tegra_car 106>;
614 reset-names = "spi";
034d023f
SW		 615 dmas = <&apbdma 28>, <&apbdma 28>;
616 dma-names = "rx", "tx";
a86b0db3
LD		 617 status = "disabled";
618 };
619
58ecb23f 620 kbc@7000e200 {
699ed4b9
LD		 621 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
622 reg = <0x7000e200 0x100>;
6cecf916 623 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
05849c93 624 clocks = <&tegra_car TEGRA30_CLK_KBC>;
3393d422
SW		 625 resets = <&tegra_car 36>;
626 reset-names = "kbc";
699ed4b9
LD		 627 status = "disabled";
628 };
629
58ecb23f 630 pmc@7000e400 {
2b84e53b 631 compatible = "nvidia,tegra30-pmc";
c04abb3a 632 reg = <0x7000e400 0x400>;
05849c93 633 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
7021d122 634 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 635 };
636
a9fe468f 637 mc: memory-controller@7000f000 {
c04abb3a 638 compatible = "nvidia,tegra30-mc";
a9fe468f
TR		 639 reg = <0x7000f000 0x400>;
640 clocks = <&tegra_car TEGRA30_CLK_MC>;
641 clock-names = "mc";
642
6cecf916 643 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a 644
a9fe468f 645 #iommu-cells = <1>;
c3e00a0e 646 };
9ee6a5c4 647
155dfc7b
PDS		 648 fuse@7000f800 {
649 compatible = "nvidia,tegra30-efuse";
650 reg = <0x7000f800 0x400>;
651 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
652 clock-names = "fuse";
653 resets = <&tegra_car 39>;
654 reset-names = "fuse";
655 };
656
cbee2613
MZ		 657 hda@70030000 {
658 compatible = "nvidia,tegra30-hda";
659 reg = <0x70030000 0x10000>;
660 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
661 clocks = <&tegra_car TEGRA30_CLK_HDA>,
662 <&tegra_car TEGRA30_CLK_HDA2HDMI>,
663 <&tegra_car TEGRA30_CLK_HDA2CODEC_2X>;
664 clock-names = "hda", "hda2hdmi", "hda2codec_2x";
665 resets = <&tegra_car 125>, /* hda */
666 <&tegra_car 128>, /* hda2hdmi */
667 <&tegra_car 111>; /* hda2codec_2x */
668 reset-names = "hda", "hda2hdmi", "hda2codec_2x";
669 status = "disabled";
670 };
671
58ecb23f 672 ahub@70080000 {
9ee6a5c4 673 compatible = "nvidia,tegra30-ahub";
5ff48887
SW		 674 reg = <0x70080000 0x200
675 0x70080200 0x100>;
6cecf916 676 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
05849c93 677 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
2bd541ff
SW		 678 <&tegra_car TEGRA30_CLK_APBIF>;
679 clock-names = "d_audio", "apbif";
3393d422
SW		 680 resets = <&tegra_car 106>, /* d_audio */
681 <&tegra_car 107>, /* apbif */
682 <&tegra_car 30>, /* i2s0 */
683 <&tegra_car 11>, /* i2s1 */
684 <&tegra_car 18>, /* i2s2 */
685 <&tegra_car 101>, /* i2s3 */
686 <&tegra_car 102>, /* i2s4 */
687 <&tegra_car 108>, /* dam0 */
688 <&tegra_car 109>, /* dam1 */
689 <&tegra_car 110>, /* dam2 */
690 <&tegra_car 10>; /* spdif */
691 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
692 "i2s3", "i2s4", "dam0", "dam1", "dam2",
693 "spdif";
034d023f
SW		 694 dmas = <&apbdma 1>, <&apbdma 1>,
695 <&apbdma 2>, <&apbdma 2>,
696 <&apbdma 3>, <&apbdma 3>,
697 <&apbdma 4>, <&apbdma 4>;
698 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
699 "rx3", "tx3";
9ee6a5c4
SW		 700 ranges;
701 #address-cells = <1>;
702 #size-cells = <1>;
703
704 tegra_i2s0: i2s@70080300 {
705 compatible = "nvidia,tegra30-i2s";
706 reg = <0x70080300 0x100>;
707 nvidia,ahub-cif-ids = <4 4>;
05849c93 708 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
3393d422
SW		 709 resets = <&tegra_car 30>;
710 reset-names = "i2s";
223ef78d 711 status = "disabled";
9ee6a5c4
SW		 712 };
713
714 tegra_i2s1: i2s@70080400 {
715 compatible = "nvidia,tegra30-i2s";
716 reg = <0x70080400 0x100>;
717 nvidia,ahub-cif-ids = <5 5>;
05849c93 718 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
3393d422
SW		 719 resets = <&tegra_car 11>;
720 reset-names = "i2s";
223ef78d 721 status = "disabled";
9ee6a5c4
SW		 722 };
723
724 tegra_i2s2: i2s@70080500 {
725 compatible = "nvidia,tegra30-i2s";
726 reg = <0x70080500 0x100>;
727 nvidia,ahub-cif-ids = <6 6>;
05849c93 728 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
3393d422
SW		 729 resets = <&tegra_car 18>;
730 reset-names = "i2s";
223ef78d 731 status = "disabled";
9ee6a5c4
SW		 732 };
733
734 tegra_i2s3: i2s@70080600 {
735 compatible = "nvidia,tegra30-i2s";
736 reg = <0x70080600 0x100>;
737 nvidia,ahub-cif-ids = <7 7>;
05849c93 738 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
3393d422
SW		 739 resets = <&tegra_car 101>;
740 reset-names = "i2s";
223ef78d 741 status = "disabled";
9ee6a5c4
SW		 742 };
743
744 tegra_i2s4: i2s@70080700 {
745 compatible = "nvidia,tegra30-i2s";
746 reg = <0x70080700 0x100>;
747 nvidia,ahub-cif-ids = <8 8>;
05849c93 748 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
3393d422
SW		 749 resets = <&tegra_car 102>;
750 reset-names = "i2s";
223ef78d 751 status = "disabled";
9ee6a5c4
SW		 752 };
753 };
7868a9bc 754
c04abb3a
SW		 755 sdhci@78000000 {
756 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
757 reg = <0x78000000 0x200>;
6cecf916 758 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
05849c93 759 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
3393d422
SW		 760 resets = <&tegra_car 14>;
761 reset-names = "sdhci";
223ef78d 762 status = "disabled";
7868a9bc 763 };
ecf43742 764
c04abb3a
SW		 765 sdhci@78000200 {
766 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
767 reg = <0x78000200 0x200>;
6cecf916 768 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
05849c93 769 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
3393d422
SW		 770 resets = <&tegra_car 9>;
771 reset-names = "sdhci";
223ef78d 772 status = "disabled";
ecf43742 773 };
54174a33 774
c04abb3a
SW		 775 sdhci@78000400 {
776 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
777 reg = <0x78000400 0x200>;
6cecf916 778 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
05849c93 779 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
3393d422
SW		 780 resets = <&tegra_car 69>;
781 reset-names = "sdhci";
223ef78d 782 status = "disabled";
c04abb3a
SW		 783 };
784
785 sdhci@78000600 {
786 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
787 reg = <0x78000600 0x200>;
6cecf916 788 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
05849c93 789 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
3393d422
SW		 790 resets = <&tegra_car 15>;
791 reset-names = "sdhci";
223ef78d 792 status = "disabled";
c04abb3a
SW		 793 };
794
cc34c9f7
TT		 795 usb@7d000000 {
796 compatible = "nvidia,tegra30-ehci", "usb-ehci";
797 reg = <0x7d000000 0x4000>;
798 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
799 phy_type = "utmi";
800 clocks = <&tegra_car TEGRA30_CLK_USBD>;
3393d422
SW		 801 resets = <&tegra_car 22>;
802 reset-names = "usb";
cc34c9f7
TT		 803 nvidia,needs-double-reset;
804 nvidia,phy = <&phy1>;
805 status = "disabled";
806 };
807
808 phy1: usb-phy@7d000000 {
809 compatible = "nvidia,tegra30-usb-phy";
810 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
811 phy_type = "utmi";
812 clocks = <&tegra_car TEGRA30_CLK_USBD>,
813 <&tegra_car TEGRA30_CLK_PLL_U>,
814 <&tegra_car TEGRA30_CLK_USBD>;
815 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 816 resets = <&tegra_car 22>, <&tegra_car 22>;
817 reset-names = "usb", "utmi-pads";
cc34c9f7
TT		 818 nvidia,hssync-start-delay = <9>;
819 nvidia,idle-wait-delay = <17>;
820 nvidia,elastic-limit = <16>;
821 nvidia,term-range-adj = <6>;
822 nvidia,xcvr-setup = <51>;
823 nvidia.xcvr-setup-use-fuses;
824 nvidia,xcvr-lsfslew = <1>;
825 nvidia,xcvr-lsrslew = <1>;
826 nvidia,xcvr-hsslew = <32>;
827 nvidia,hssquelch-level = <2>;
828 nvidia,hsdiscon-level = <5>;
308efde2 829 nvidia,has-utmi-pad-registers;
cc34c9f7
TT		 830 status = "disabled";
831 };
832
833 usb@7d004000 {
834 compatible = "nvidia,tegra30-ehci", "usb-ehci";
835 reg = <0x7d004000 0x4000>;
836 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
fd6441ec 837 phy_type = "utmi";
cc34c9f7 838 clocks = <&tegra_car TEGRA30_CLK_USB2>;
3393d422
SW		 839 resets = <&tegra_car 58>;
840 reset-names = "usb";
cc34c9f7
TT		 841 nvidia,phy = <&phy2>;
842 status = "disabled";
843 };
844
845 phy2: usb-phy@7d004000 {
846 compatible = "nvidia,tegra30-usb-phy";
fd6441ec
EB		 847 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
848 phy_type = "utmi";
cc34c9f7
TT		 849 clocks = <&tegra_car TEGRA30_CLK_USB2>,
850 <&tegra_car TEGRA30_CLK_PLL_U>,
fd6441ec
EB		 851 <&tegra_car TEGRA30_CLK_USBD>;
852 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 853 resets = <&tegra_car 58>, <&tegra_car 22>;
854 reset-names = "usb", "utmi-pads";
fd6441ec
EB		 855 nvidia,hssync-start-delay = <9>;
856 nvidia,idle-wait-delay = <17>;
857 nvidia,elastic-limit = <16>;
858 nvidia,term-range-adj = <6>;
859 nvidia,xcvr-setup = <51>;
860 nvidia.xcvr-setup-use-fuses;
861 nvidia,xcvr-lsfslew = <2>;
862 nvidia,xcvr-lsrslew = <2>;
863 nvidia,xcvr-hsslew = <32>;
864 nvidia,hssquelch-level = <2>;
865 nvidia,hsdiscon-level = <5>;
cc34c9f7
TT		 866 status = "disabled";
867 };
868
869 usb@7d008000 {
870 compatible = "nvidia,tegra30-ehci", "usb-ehci";
871 reg = <0x7d008000 0x4000>;
872 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
873 phy_type = "utmi";
874 clocks = <&tegra_car TEGRA30_CLK_USB3>;
3393d422
SW		 875 resets = <&tegra_car 59>;
876 reset-names = "usb";
cc34c9f7
TT		 877 nvidia,phy = <&phy3>;
878 status = "disabled";
879 };
880
881 phy3: usb-phy@7d008000 {
882 compatible = "nvidia,tegra30-usb-phy";
883 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
884 phy_type = "utmi";
885 clocks = <&tegra_car TEGRA30_CLK_USB3>,
886 <&tegra_car TEGRA30_CLK_PLL_U>,
887 <&tegra_car TEGRA30_CLK_USBD>;
888 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 889 resets = <&tegra_car 59>, <&tegra_car 22>;
890 reset-names = "usb", "utmi-pads";
cc34c9f7
TT		 891 nvidia,hssync-start-delay = <0>;
892 nvidia,idle-wait-delay = <17>;
893 nvidia,elastic-limit = <16>;
894 nvidia,term-range-adj = <6>;
895 nvidia,xcvr-setup = <51>;
896 nvidia.xcvr-setup-use-fuses;
897 nvidia,xcvr-lsfslew = <2>;
898 nvidia,xcvr-lsrslew = <2>;
899 nvidia,xcvr-hsslew = <32>;
900 nvidia,hssquelch-level = <2>;
901 nvidia,hsdiscon-level = <5>;
902 status = "disabled";
903 };
904
7d19a34a
HD		 905 cpus {
906 #address-cells = <1>;
907 #size-cells = <0>;
908
909 cpu@0 {
910 device_type = "cpu";
911 compatible = "arm,cortex-a9";
912 reg = <0>;
913 };
914
915 cpu@1 {
916 device_type = "cpu";
917 compatible = "arm,cortex-a9";
918 reg = <1>;
919 };
920
921 cpu@2 {
922 device_type = "cpu";
923 compatible = "arm,cortex-a9";
924 reg = <2>;
925 };
926
927 cpu@3 {
928 device_type = "cpu";
929 compatible = "arm,cortex-a9";
930 reg = <3>;
931 };
932 };
933
c04abb3a
SW		 934 pmu {
935 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 936 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
937 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
938 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
939 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
54174a33 940 };
c3e00a0e 941};
Linux kernel - Deliverables
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