[deliverable/linux.git] / arch / arm / boot / dts / tegra30.dtsi

#include <dt-bindings/clock/tegra30-car.h>
#include <dt-bindings/gpio/tegra-gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

#include "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra30";
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &uarta;
		serial1 = &uartb;
		serial2 = &uartc;
		serial3 = &uartd;
		serial4 = &uarte;
	};

	host1x {
		compatible = "nvidia,tegra30-host1x", "simple-bus";
		reg = <0x50000000 0x00024000>;
		interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
			     <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
		clocks = <&tegra_car TEGRA30_CLK_HOST1X>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe {
			compatible = "nvidia,tegra30-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_MPE>;
		};

		vi {
			compatible = "nvidia,tegra30-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_VI>;
		};

		epp {
			compatible = "nvidia,tegra30-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_EPP>;
		};

		isp {
			compatible = "nvidia,tegra30-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_ISP>;
		};

		gr2d {
			compatible = "nvidia,tegra30-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_GR2D>;
		};

		gr3d {
			compatible = "nvidia,tegra30-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car 24 &tegra_car 98>;
			clock-names = "3d", "3d2";
		};

		dc@54200000 {
			compatible = "nvidia,tegra30-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_DISP1>,
				 <&tegra_car TEGRA30_CLK_PLL_P>;
			clock-names = "disp1", "parent";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra30-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_DISP2>,
				 <&tegra_car TEGRA30_CLK_PLL_P>;
			clock-names = "disp2", "parent";

			rgb {
				status = "disabled";
			};
		};

		hdmi {
			compatible = "nvidia,tegra30-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_HDMI>,
				 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
			clock-names = "hdmi", "parent";
			status = "disabled";
		};

		tvo {
			compatible = "nvidia,tegra30-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&tegra_car TEGRA30_CLK_TVO>;
			status = "disabled";
		};

		dsi {
			compatible = "nvidia,tegra30-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car TEGRA30_CLK_DSIA>;
			status = "disabled";
		};
	};

	timer@50004600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x50040600 0x20>;
		interrupts = <GIC_PPI 13
			(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
		clocks = <&tegra_car TEGRA30_CLK_TWD>;
	};

	intc: interrupt-controller {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0x50043000 0x1000>;
		arm,data-latency = <6 6 2>;
		arm,tag-latency = <5 5 2>;
		cache-unified;
		cache-level = <2>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
		reg = <0x60005000 0x400>;
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_TIMER>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra30-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1400>;
		interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
	};

	ahb: ahb {
		compatible = "nvidia,tegra30-ahb";
		reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio {
		compatible = "nvidia,tegra30-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra30-pinmux";
		reg = <0x70000868 0xd4    /* Pad control registers */
		       0x70003000 0x3e4>; /* Mux registers */
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
	 * the APB DMA based serial driver, the comptible is
	 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 8>;
		clocks = <&tegra_car TEGRA30_CLK_UARTA>;
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 9>;
		clocks = <&tegra_car TEGRA30_CLK_UARTB>;
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 10>;
		clocks = <&tegra_car TEGRA30_CLK_UARTC>;
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 19>;
		clocks = <&tegra_car TEGRA30_CLK_UARTD>;
		status = "disabled";
	};

	uarte: serial@70006400 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 20>;
		clocks = <&tegra_car TEGRA30_CLK_UARTE>;
		status = "disabled";
	};

	pwm: pwm {
		compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car TEGRA30_CLK_PWM>;
		status = "disabled";
	};

	rtc {
		compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_RTC>;
	};

	i2c@7000c000 {
		compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_I2C1>,
			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_I2C2>,
			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_I2C3>,
			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c700 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c700 0x100>;
		interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_I2C4>,
			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000d000 0x100>;
		interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_I2C5>,
			 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d400 0x200>;
		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_SBC1>;
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d600 0x200>;
		interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_SBC2>;
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d800 0x200>;
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_SBC3>;
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000da00 0x200>;
		interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_SBC4>;
		status = "disabled";
	};

	spi@7000dc00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000dc00 0x200>;
		interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 27>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_SBC5>;
		status = "disabled";
	};

	spi@7000de00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000de00 0x200>;
		interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 28>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car TEGRA30_CLK_SBC6>;
		status = "disabled";
	};

	kbc {
		compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
		reg = <0x7000e200 0x100>;
		interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_KBC>;
		status = "disabled";
	};

	pmc {
		compatible = "nvidia,tegra30-pmc";
		reg = <0x7000e400 0x400>;
		clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
	};

	memory-controller {
		compatible = "nvidia,tegra30-mc";
		reg = <0x7000f000 0x010
		       0x7000f03c 0x1b4
		       0x7000f200 0x028
		       0x7000f284 0x17c>;
		interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
	};

	iommu {
		compatible = "nvidia,tegra30-smmu";
		reg = <0x7000f010 0x02c
		       0x7000f1f0 0x010
		       0x7000f228 0x05c>;
		nvidia,#asids = <4>;		/* # of ASIDs */
		dma-window = <0 0x40000000>;	/* IOVA start & length */
		nvidia,ahb = <&ahb>;
	};

	ahub {
		compatible = "nvidia,tegra30-ahub";
		reg = <0x70080000 0x200
		       0x70080200 0x100>;
		interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
		nvidia,dma-request-selector = <&apbdma 1>;
		clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
			 <&tegra_car TEGRA30_CLK_APBIF>,
			 <&tegra_car TEGRA30_CLK_I2S0>,
			 <&tegra_car TEGRA30_CLK_I2S1>,
			 <&tegra_car TEGRA30_CLK_I2S2>,
			 <&tegra_car TEGRA30_CLK_I2S3>,
			 <&tegra_car TEGRA30_CLK_I2S4>,
			 <&tegra_car TEGRA30_CLK_DAM0>,
			 <&tegra_car TEGRA30_CLK_DAM1>,
			 <&tegra_car TEGRA30_CLK_DAM2>,
			 <&tegra_car TEGRA30_CLK_SPDIF_IN>;
		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
			      "spdif_in";
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;

		tegra_i2s0: i2s@70080300 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080300 0x100>;
			nvidia,ahub-cif-ids = <4 4>;
			clocks = <&tegra_car TEGRA30_CLK_I2S0>;
			status = "disabled";
		};

		tegra_i2s1: i2s@70080400 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080400 0x100>;
			nvidia,ahub-cif-ids = <5 5>;
			clocks = <&tegra_car TEGRA30_CLK_I2S1>;
			status = "disabled";
		};

		tegra_i2s2: i2s@70080500 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080500 0x100>;
			nvidia,ahub-cif-ids = <6 6>;
			clocks = <&tegra_car TEGRA30_CLK_I2S2>;
			status = "disabled";
		};

		tegra_i2s3: i2s@70080600 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080600 0x100>;
			nvidia,ahub-cif-ids = <7 7>;
			clocks = <&tegra_car TEGRA30_CLK_I2S3>;
			status = "disabled";
		};

		tegra_i2s4: i2s@70080700 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080700 0x100>;
			nvidia,ahub-cif-ids = <8 8>;
			clocks = <&tegra_car TEGRA30_CLK_I2S4>;
			status = "disabled";
		};
	};

	sdhci@78000000 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000000 0x200>;
		interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
		status = "disabled";
	};

	sdhci@78000200 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000200 0x200>;
		interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
		status = "disabled";
	};

	sdhci@78000400 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000400 0x200>;
		interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
		status = "disabled";
	};

	sdhci@78000600 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000600 0x200>;
		interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
	};
};
Commit	Line	Data
05849c93	1	#include <dt-bindings/clock/tegra30-car.h>
3325f1bc	2	#include <dt-bindings/gpio/tegra-gpio.h>
6cecf916	3	#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc	4
1bd0bd49	5	#include "skeleton.dtsi"
c3e00a0e PDS	6
	7	/ {
	8	compatible = "nvidia,tegra30";
	9	interrupt-parent = <&intc>;
	10
b6551bb9 LD	11	aliases {
	12	serial0 = &uarta;
	13	serial1 = &uartb;
	14	serial2 = &uartc;
	15	serial3 = &uartd;
	16	serial4 = &uarte;
	17	};
	18
ed39097c TR	19	host1x {
	20	compatible = "nvidia,tegra30-host1x", "simple-bus";
	21	reg = <0x50000000 0x00024000>;
6cecf916 SW	22	interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
6cecf916 SW	23	<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
05849c93	24	clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
ed39097c TR	25
	26	#address-cells = <1>;
	27	#size-cells = <1>;
	28
	29	ranges = <0x54000000 0x54000000 0x04000000>;
	30
	31	mpe {
	32	compatible = "nvidia,tegra30-mpe";
	33	reg = <0x54040000 0x00040000>;
6cecf916	34	interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
05849c93	35	clocks = <&tegra_car TEGRA30_CLK_MPE>;
ed39097c TR	36	};
	37
	38	vi {
	39	compatible = "nvidia,tegra30-vi";
	40	reg = <0x54080000 0x00040000>;
6cecf916	41	interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
05849c93	42	clocks = <&tegra_car TEGRA30_CLK_VI>;
ed39097c TR	43	};
	44
	45	epp {
	46	compatible = "nvidia,tegra30-epp";
	47	reg = <0x540c0000 0x00040000>;
6cecf916	48	interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
05849c93	49	clocks = <&tegra_car TEGRA30_CLK_EPP>;
ed39097c TR	50	};
	51
	52	isp {
	53	compatible = "nvidia,tegra30-isp";
	54	reg = <0x54100000 0x00040000>;
6cecf916	55	interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
05849c93	56	clocks = <&tegra_car TEGRA30_CLK_ISP>;
ed39097c TR	57	};
	58
	59	gr2d {
	60	compatible = "nvidia,tegra30-gr2d";
	61	reg = <0x54140000 0x00040000>;
6cecf916	62	interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
05849c93	63	clocks = <&tegra_car TEGRA30_CLK_GR2D>;
ed39097c TR	64	};
	65
	66	gr3d {
	67	compatible = "nvidia,tegra30-gr3d";
	68	reg = <0x54180000 0x00040000>;
1cbc733d PG	69	clocks = <&tegra_car 24 &tegra_car 98>;
1cbc733d PG	70	clock-names = "3d", "3d2";
ed39097c TR	71	};
	72
	73	dc@54200000 {
	74	compatible = "nvidia,tegra30-dc";
	75	reg = <0x54200000 0x00040000>;
6cecf916	76	interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
05849c93 HD	77	clocks = <&tegra_car TEGRA30_CLK_DISP1>,
05849c93 HD	78	<&tegra_car TEGRA30_CLK_PLL_P>;
1cbc733d	79	clock-names = "disp1", "parent";
ed39097c TR	80
	81	rgb {
	82	status = "disabled";
	83	};
	84	};
	85
	86	dc@54240000 {
	87	compatible = "nvidia,tegra30-dc";
	88	reg = <0x54240000 0x00040000>;
6cecf916	89	interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
05849c93 HD	90	clocks = <&tegra_car TEGRA30_CLK_DISP2>,
05849c93 HD	91	<&tegra_car TEGRA30_CLK_PLL_P>;
1cbc733d	92	clock-names = "disp2", "parent";
ed39097c TR	93
	94	rgb {
	95	status = "disabled";
	96	};
	97	};
	98
	99	hdmi {
	100	compatible = "nvidia,tegra30-hdmi";
	101	reg = <0x54280000 0x00040000>;
6cecf916	102	interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
05849c93 HD	103	clocks = <&tegra_car TEGRA30_CLK_HDMI>,
05849c93 HD	104	<&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
1cbc733d	105	clock-names = "hdmi", "parent";
ed39097c TR	106	status = "disabled";
	107	};
	108
	109	tvo {
	110	compatible = "nvidia,tegra30-tvo";
	111	reg = <0x542c0000 0x00040000>;
6cecf916	112	interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
05849c93	113	clocks = <&tegra_car TEGRA30_CLK_TVO>;
ed39097c TR	114	status = "disabled";
	115	};
	116
	117	dsi {
	118	compatible = "nvidia,tegra30-dsi";
	119	reg = <0x54300000 0x00040000>;
05849c93	120	clocks = <&tegra_car TEGRA30_CLK_DSIA>;
ed39097c TR	121	status = "disabled";
	122	};
	123	};
	124
73368ba0 SW	125	timer@50004600 {
	126	compatible = "arm,cortex-a9-twd-timer";
	127	reg = <0x50040600 0x20>;
6cecf916 SW	128	interrupts = <GIC_PPI 13
6cecf916 SW	129	(GIC_CPU_MASK_SIMPLE(4) \| IRQ_TYPE_LEVEL_HIGH)>;
05849c93	130	clocks = <&tegra_car TEGRA30_CLK_TWD>;
73368ba0 SW	131	};
73368ba0 SW	132
f9eb26a4	133	intc: interrupt-controller {
c3e00a0e	134	compatible = "arm,cortex-a9-gic";
5ff48887 SW	135	reg = <0x50041000 0x1000
5ff48887 SW	136	0x50040100 0x0100>;
2eaab06e SW	137	interrupt-controller;
2eaab06e SW	138	#interrupt-cells = <3>;
c3e00a0e PDS	139	};
c3e00a0e PDS	140
bb2c1de9 SW	141	cache-controller {
	142	compatible = "arm,pl310-cache";
	143	reg = <0x50043000 0x1000>;
	144	arm,data-latency = <6 6 2>;
	145	arm,tag-latency = <5 5 2>;
	146	cache-unified;
	147	cache-level = <2>;
	148	};
	149
2f2b7fb2 SW	150	timer@60005000 {
	151	compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
	152	reg = <0x60005000 0x400>;
6cecf916 SW	153	interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
	154	<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
	155	<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
	156	<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
	157	<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
	158	<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
05849c93	159	clocks = <&tegra_car TEGRA30_CLK_TIMER>;
2f2b7fb2 SW	160	};
2f2b7fb2 SW	161
95985667 PG	162	tegra_car: clock {
	163	compatible = "nvidia,tegra30-car";
	164	reg = <0x60006000 0x1000>;
	165	#clock-cells = <1>;
	166	};
	167
f9eb26a4	168	apbdma: dma {
8051b75a SW	169	compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
8051b75a SW	170	reg = <0x6000a000 0x1400>;
6cecf916 SW	171	interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
	172	<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
	173	<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
	174	<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
	175	<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
	176	<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
	177	<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
	178	<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
	179	<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
	180	<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
	181	<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
	182	<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
	183	<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
	184	<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
	185	<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
	186	<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
	187	<GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
	188	<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
	189	<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
	190	<GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
	191	<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
	192	<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
	193	<GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
	194	<GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
	195	<GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
	196	<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
	197	<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
	198	<GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
	199	<GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
	200	<GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
	201	<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
	202	<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
05849c93	203	clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
8051b75a SW	204	};
8051b75a SW	205
c04abb3a SW	206	ahb: ahb {
	207	compatible = "nvidia,tegra30-ahb";
	208	reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e PDS	209	};
c3e00a0e PDS	210
f9eb26a4	211	gpio: gpio {
35f210ec	212	compatible = "nvidia,tegra30-gpio";
95decf84	213	reg = <0x6000d000 0x1000>;
6cecf916 SW	214	interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
	215	<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
	216	<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
	217	<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
	218	<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
	219	<GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
	220	<GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
	221	<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
c3e00a0e PDS	222	#gpio-cells = <2>;
c3e00a0e PDS	223	gpio-controller;
6f74dc9b SW	224	#interrupt-cells = <2>;
6f74dc9b SW	225	interrupt-controller;
c3e00a0e PDS	226	};
c3e00a0e PDS	227
c04abb3a SW	228	pinmux: pinmux {
c04abb3a SW	229	compatible = "nvidia,tegra30-pinmux";
322337b8 PR	230	reg = <0x70000868 0xd4 /* Pad control registers */
322337b8 PR	231	0x70003000 0x3e4>; /* Mux registers */
c04abb3a SW	232	};
c04abb3a SW	233
b6551bb9 LD	234	/*
	235	* There are two serial driver i.e. 8250 based simple serial
	236	* driver and APB DMA based serial driver for higher baudrate
	237	* and performace. To enable the 8250 based driver, the compatible
	238	* is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
	239	* the APB DMA based serial driver, the comptible is
	240	* "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
	241	*/
	242	uarta: serial@70006000 {
c3e00a0e PDS	243	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	244	reg = <0x70006000 0x40>;
	245	reg-shift = <2>;
6cecf916	246	interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	247	nvidia,dma-request-selector = <&apbdma 8>;
05849c93	248	clocks = <&tegra_car TEGRA30_CLK_UARTA>;
223ef78d	249	status = "disabled";
c3e00a0e PDS	250	};
c3e00a0e PDS	251
b6551bb9	252	uartb: serial@70006040 {
c3e00a0e PDS	253	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	254	reg = <0x70006040 0x40>;
	255	reg-shift = <2>;
6cecf916	256	interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	257	nvidia,dma-request-selector = <&apbdma 9>;
05849c93	258	clocks = <&tegra_car TEGRA30_CLK_UARTB>;
223ef78d	259	status = "disabled";
c3e00a0e PDS	260	};
c3e00a0e PDS	261
b6551bb9	262	uartc: serial@70006200 {
c3e00a0e PDS	263	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	264	reg = <0x70006200 0x100>;
	265	reg-shift = <2>;
6cecf916	266	interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	267	nvidia,dma-request-selector = <&apbdma 10>;
05849c93	268	clocks = <&tegra_car TEGRA30_CLK_UARTC>;
223ef78d	269	status = "disabled";
c3e00a0e PDS	270	};
c3e00a0e PDS	271
b6551bb9	272	uartd: serial@70006300 {
c3e00a0e PDS	273	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	274	reg = <0x70006300 0x100>;
	275	reg-shift = <2>;
6cecf916	276	interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	277	nvidia,dma-request-selector = <&apbdma 19>;
05849c93	278	clocks = <&tegra_car TEGRA30_CLK_UARTD>;
223ef78d	279	status = "disabled";
c3e00a0e PDS	280	};
c3e00a0e PDS	281
b6551bb9	282	uarte: serial@70006400 {
c3e00a0e PDS	283	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	284	reg = <0x70006400 0x100>;
	285	reg-shift = <2>;
6cecf916	286	interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
b6551bb9	287	nvidia,dma-request-selector = <&apbdma 20>;
05849c93	288	clocks = <&tegra_car TEGRA30_CLK_UARTE>;
223ef78d	289	status = "disabled";
c3e00a0e PDS	290	};
c3e00a0e PDS	291
2b8b15da	292	pwm: pwm {
140fd977 TR	293	compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
	294	reg = <0x7000a000 0x100>;
	295	#pwm-cells = <2>;
05849c93	296	clocks = <&tegra_car TEGRA30_CLK_PWM>;
b69cd984	297	status = "disabled";
140fd977 TR	298	};
140fd977 TR	299
380e04ac SW	300	rtc {
	301	compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
	302	reg = <0x7000e000 0x100>;
6cecf916	303	interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
05849c93	304	clocks = <&tegra_car TEGRA30_CLK_RTC>;
380e04ac SW	305	};
380e04ac SW	306
c04abb3a	307	i2c@7000c000 {
c04abb3a SW	308	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a SW	309	reg = <0x7000c000 0x100>;
6cecf916	310	interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	311	#address-cells = <1>;
2eaab06e SW	312	#size-cells = <0>;
05849c93 HD	313	clocks = <&tegra_car TEGRA30_CLK_I2C1>,
05849c93 HD	314	<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d	315	clock-names = "div-clk", "fast-clk";
223ef78d	316	status = "disabled";
c3e00a0e PDS	317	};
c3e00a0e PDS	318
c04abb3a	319	i2c@7000c400 {
c04abb3a SW	320	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a SW	321	reg = <0x7000c400 0x100>;
6cecf916	322	interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	323	#address-cells = <1>;
2eaab06e SW	324	#size-cells = <0>;
05849c93 HD	325	clocks = <&tegra_car TEGRA30_CLK_I2C2>,
05849c93 HD	326	<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d	327	clock-names = "div-clk", "fast-clk";
223ef78d	328	status = "disabled";
c3e00a0e PDS	329	};
c3e00a0e PDS	330
c04abb3a	331	i2c@7000c500 {
c04abb3a SW	332	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a SW	333	reg = <0x7000c500 0x100>;
6cecf916	334	interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	335	#address-cells = <1>;
2eaab06e SW	336	#size-cells = <0>;
05849c93 HD	337	clocks = <&tegra_car TEGRA30_CLK_I2C3>,
05849c93 HD	338	<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d	339	clock-names = "div-clk", "fast-clk";
223ef78d	340	status = "disabled";
c3e00a0e PDS	341	};
c3e00a0e PDS	342
c04abb3a	343	i2c@7000c700 {
c04abb3a SW	344	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a SW	345	reg = <0x7000c700 0x100>;
6cecf916	346	interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	347	#address-cells = <1>;
2eaab06e SW	348	#size-cells = <0>;
05849c93 HD	349	clocks = <&tegra_car TEGRA30_CLK_I2C4>,
05849c93 HD	350	<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d	351	clock-names = "div-clk", "fast-clk";
223ef78d	352	status = "disabled";
c3e00a0e PDS	353	};
c3e00a0e PDS	354
c04abb3a	355	i2c@7000d000 {
c04abb3a SW	356	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
c04abb3a SW	357	reg = <0x7000d000 0x100>;
6cecf916	358	interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e SW	359	#address-cells = <1>;
2eaab06e SW	360	#size-cells = <0>;
05849c93 HD	361	clocks = <&tegra_car TEGRA30_CLK_I2C5>,
05849c93 HD	362	<&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d	363	clock-names = "div-clk", "fast-clk";
223ef78d	364	status = "disabled";
c04abb3a SW	365	};
c04abb3a SW	366
a86b0db3 LD	367	spi@7000d400 {
	368	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	369	reg = <0x7000d400 0x200>;
6cecf916	370	interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	371	nvidia,dma-request-selector = <&apbdma 15>;
	372	#address-cells = <1>;
	373	#size-cells = <0>;
05849c93	374	clocks = <&tegra_car TEGRA30_CLK_SBC1>;
a86b0db3 LD	375	status = "disabled";
	376	};
	377
	378	spi@7000d600 {
	379	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	380	reg = <0x7000d600 0x200>;
6cecf916	381	interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	382	nvidia,dma-request-selector = <&apbdma 16>;
	383	#address-cells = <1>;
	384	#size-cells = <0>;
05849c93	385	clocks = <&tegra_car TEGRA30_CLK_SBC2>;
a86b0db3 LD	386	status = "disabled";
	387	};
	388
	389	spi@7000d800 {
	390	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
57471c8d	391	reg = <0x7000d800 0x200>;
6cecf916	392	interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	393	nvidia,dma-request-selector = <&apbdma 17>;
	394	#address-cells = <1>;
	395	#size-cells = <0>;
05849c93	396	clocks = <&tegra_car TEGRA30_CLK_SBC3>;
a86b0db3 LD	397	status = "disabled";
	398	};
	399
	400	spi@7000da00 {
	401	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	402	reg = <0x7000da00 0x200>;
6cecf916	403	interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	404	nvidia,dma-request-selector = <&apbdma 18>;
	405	#address-cells = <1>;
	406	#size-cells = <0>;
05849c93	407	clocks = <&tegra_car TEGRA30_CLK_SBC4>;
a86b0db3 LD	408	status = "disabled";
	409	};
	410
	411	spi@7000dc00 {
	412	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	413	reg = <0x7000dc00 0x200>;
6cecf916	414	interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	415	nvidia,dma-request-selector = <&apbdma 27>;
	416	#address-cells = <1>;
	417	#size-cells = <0>;
05849c93	418	clocks = <&tegra_car TEGRA30_CLK_SBC5>;
a86b0db3 LD	419	status = "disabled";
	420	};
	421
	422	spi@7000de00 {
	423	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	424	reg = <0x7000de00 0x200>;
6cecf916	425	interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3 LD	426	nvidia,dma-request-selector = <&apbdma 28>;
	427	#address-cells = <1>;
	428	#size-cells = <0>;
05849c93	429	clocks = <&tegra_car TEGRA30_CLK_SBC6>;
a86b0db3 LD	430	status = "disabled";
	431	};
	432
699ed4b9 LD	433	kbc {
	434	compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
	435	reg = <0x7000e200 0x100>;
6cecf916	436	interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
05849c93	437	clocks = <&tegra_car TEGRA30_CLK_KBC>;
699ed4b9 LD	438	status = "disabled";
	439	};
	440
c04abb3a	441	pmc {
2b84e53b	442	compatible = "nvidia,tegra30-pmc";
c04abb3a	443	reg = <0x7000e400 0x400>;
05849c93	444	clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
7021d122	445	clock-names = "pclk", "clk32k_in";
c04abb3a SW	446	};
c04abb3a SW	447
a9140aa5	448	memory-controller {
c04abb3a SW	449	compatible = "nvidia,tegra30-mc";
	450	reg = <0x7000f000 0x010
	451	0x7000f03c 0x1b4
	452	0x7000f200 0x028
	453	0x7000f284 0x17c>;
6cecf916	454	interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a SW	455	};
c04abb3a SW	456
3fbf07d8	457	iommu {
c04abb3a SW	458	compatible = "nvidia,tegra30-smmu";
	459	reg = <0x7000f010 0x02c
	460	0x7000f1f0 0x010
	461	0x7000f228 0x05c>;
	462	nvidia,#asids = <4>; /* # of ASIDs */
	463	dma-window = <0 0x40000000>; /* IOVA start & length */
	464	nvidia,ahb = <&ahb>;
c3e00a0e	465	};
9ee6a5c4 SW	466
	467	ahub {
	468	compatible = "nvidia,tegra30-ahub";
5ff48887 SW	469	reg = <0x70080000 0x200
5ff48887 SW	470	0x70080200 0x100>;
6cecf916	471	interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
9ee6a5c4	472	nvidia,dma-request-selector = <&apbdma 1>;
05849c93 HD	473	clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
	474	<&tegra_car TEGRA30_CLK_APBIF>,
	475	<&tegra_car TEGRA30_CLK_I2S0>,
	476	<&tegra_car TEGRA30_CLK_I2S1>,
	477	<&tegra_car TEGRA30_CLK_I2S2>,
	478	<&tegra_car TEGRA30_CLK_I2S3>,
	479	<&tegra_car TEGRA30_CLK_I2S4>,
	480	<&tegra_car TEGRA30_CLK_DAM0>,
	481	<&tegra_car TEGRA30_CLK_DAM1>,
	482	<&tegra_car TEGRA30_CLK_DAM2>,
	483	<&tegra_car TEGRA30_CLK_SPDIF_IN>;
1cbc733d PG	484	clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
	485	"i2s3", "i2s4", "dam0", "dam1", "dam2",
	486	"spdif_in";
9ee6a5c4 SW	487	ranges;
	488	#address-cells = <1>;
	489	#size-cells = <1>;
	490
	491	tegra_i2s0: i2s@70080300 {
	492	compatible = "nvidia,tegra30-i2s";
	493	reg = <0x70080300 0x100>;
	494	nvidia,ahub-cif-ids = <4 4>;
05849c93	495	clocks = <&tegra_car TEGRA30_CLK_I2S0>;
223ef78d	496	status = "disabled";
9ee6a5c4 SW	497	};
	498
	499	tegra_i2s1: i2s@70080400 {
	500	compatible = "nvidia,tegra30-i2s";
	501	reg = <0x70080400 0x100>;
	502	nvidia,ahub-cif-ids = <5 5>;
05849c93	503	clocks = <&tegra_car TEGRA30_CLK_I2S1>;
223ef78d	504	status = "disabled";
9ee6a5c4 SW	505	};
	506
	507	tegra_i2s2: i2s@70080500 {
	508	compatible = "nvidia,tegra30-i2s";
	509	reg = <0x70080500 0x100>;
	510	nvidia,ahub-cif-ids = <6 6>;
05849c93	511	clocks = <&tegra_car TEGRA30_CLK_I2S2>;
223ef78d	512	status = "disabled";
9ee6a5c4 SW	513	};
	514
	515	tegra_i2s3: i2s@70080600 {
	516	compatible = "nvidia,tegra30-i2s";
	517	reg = <0x70080600 0x100>;
	518	nvidia,ahub-cif-ids = <7 7>;
05849c93	519	clocks = <&tegra_car TEGRA30_CLK_I2S3>;
223ef78d	520	status = "disabled";
9ee6a5c4 SW	521	};
	522
	523	tegra_i2s4: i2s@70080700 {
	524	compatible = "nvidia,tegra30-i2s";
	525	reg = <0x70080700 0x100>;
	526	nvidia,ahub-cif-ids = <8 8>;
05849c93	527	clocks = <&tegra_car TEGRA30_CLK_I2S4>;
223ef78d	528	status = "disabled";
9ee6a5c4 SW	529	};
9ee6a5c4 SW	530	};
7868a9bc	531
c04abb3a SW	532	sdhci@78000000 {
	533	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	534	reg = <0x78000000 0x200>;
6cecf916	535	interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
05849c93	536	clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
223ef78d	537	status = "disabled";
7868a9bc	538	};
ecf43742	539
c04abb3a SW	540	sdhci@78000200 {
	541	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	542	reg = <0x78000200 0x200>;
6cecf916	543	interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
05849c93	544	clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
223ef78d	545	status = "disabled";
ecf43742	546	};
54174a33	547
c04abb3a SW	548	sdhci@78000400 {
	549	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	550	reg = <0x78000400 0x200>;
6cecf916	551	interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
05849c93	552	clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
223ef78d	553	status = "disabled";
c04abb3a SW	554	};
	555
	556	sdhci@78000600 {
	557	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	558	reg = <0x78000600 0x200>;
6cecf916	559	interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
05849c93	560	clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
223ef78d	561	status = "disabled";
c04abb3a SW	562	};
c04abb3a SW	563
7d19a34a HD	564	cpus {
	565	#address-cells = <1>;
	566	#size-cells = <0>;
	567
	568	cpu@0 {
	569	device_type = "cpu";
	570	compatible = "arm,cortex-a9";
	571	reg = <0>;
	572	};
	573
	574	cpu@1 {
	575	device_type = "cpu";
	576	compatible = "arm,cortex-a9";
	577	reg = <1>;
	578	};
	579
	580	cpu@2 {
	581	device_type = "cpu";
	582	compatible = "arm,cortex-a9";
	583	reg = <2>;
	584	};
	585
	586	cpu@3 {
	587	device_type = "cpu";
	588	compatible = "arm,cortex-a9";
	589	reg = <3>;
	590	};
	591	};
	592
c04abb3a SW	593	pmu {
c04abb3a SW	594	compatible = "arm,cortex-a9-pmu";
6cecf916 SW	595	interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
	596	<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
	597	<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
	598	<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
54174a33	599	};
c3e00a0e	600	};