projects / deliverable / linux.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
ARM: dts: enable PCIe support for Cygnus
[deliverable/linux.git] / arch / arm / boot / dts / tegra30.dtsi
CommitLineData
05849c93 1#include <dt-bindings/clock/tegra30-car.h>
3325f1bc 2#include <dt-bindings/gpio/tegra-gpio.h>
6d9adf6f 3#include <dt-bindings/memory/tegra30-mc.h>
a47c662a 4#include <dt-bindings/pinctrl/pinctrl-tegra.h>
6cecf916 5#include <dt-bindings/interrupt-controller/arm-gic.h>
3325f1bc 6
1bd0bd49 7#include "skeleton.dtsi"
c3e00a0e
PDS		 8
9/ {
10 compatible = "nvidia,tegra30";
11 interrupt-parent = <&intc>;
12
58ecb23f 13 pcie-controller@00003000 {
e07e3dbd
TR		 14 compatible = "nvidia,tegra30-pcie";
15 device_type = "pci";
16 reg = <0x00003000 0x00000800 /* PADS registers */
17 0x00003800 0x00000200 /* AFI registers */
18 0x10000000 0x10000000>; /* configuration space */
19 reg-names = "pads", "afi", "cs";
20 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */
21 GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */
22 interrupt-names = "intr", "msi";
23
97070bd4
LS		 24 #interrupt-cells = <1>;
25 interrupt-map-mask = <0 0 0 0>;
26 interrupt-map = <0 0 0 0 &intc GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
27
e07e3dbd
TR		 28 bus-range = <0x00 0xff>;
29 #address-cells = <3>;
30 #size-cells = <2>;
31
32 ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */
33 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */
34 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */
35 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */
d7283c11
JA		 36 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */
37 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */
e07e3dbd
TR		 38
39 clocks = <&tegra_car TEGRA30_CLK_PCIE>,
40 <&tegra_car TEGRA30_CLK_AFI>,
e07e3dbd
TR		 41 <&tegra_car TEGRA30_CLK_PLL_E>,
42 <&tegra_car TEGRA30_CLK_CML0>;
2bd541ff 43 clock-names = "pex", "afi", "pll_e", "cml";
3393d422
SW		 44 resets = <&tegra_car 70>,
45 <&tegra_car 72>,
46 <&tegra_car 74>;
47 reset-names = "pex", "afi", "pcie_x";
e07e3dbd
TR		 48 status = "disabled";
49
50 pci@1,0 {
51 device_type = "pci";
52 assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>;
53 reg = <0x000800 0 0 0 0>;
54 status = "disabled";
55
56 #address-cells = <3>;
57 #size-cells = <2>;
58 ranges;
59
60 nvidia,num-lanes = <2>;
61 };
62
63 pci@2,0 {
64 device_type = "pci";
65 assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>;
66 reg = <0x001000 0 0 0 0>;
67 status = "disabled";
68
69 #address-cells = <3>;
70 #size-cells = <2>;
71 ranges;
72
73 nvidia,num-lanes = <2>;
74 };
75
76 pci@3,0 {
77 device_type = "pci";
78 assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>;
79 reg = <0x001800 0 0 0 0>;
80 status = "disabled";
81
82 #address-cells = <3>;
83 #size-cells = <2>;
84 ranges;
85
86 nvidia,num-lanes = <2>;
87 };
88 };
89
58ecb23f 90 host1x@50000000 {
ed39097c
TR		 91 compatible = "nvidia,tegra30-host1x", "simple-bus";
92 reg = <0x50000000 0x00024000>;
6cecf916
SW		 93 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */
94 <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */
05849c93 95 clocks = <&tegra_car TEGRA30_CLK_HOST1X>;
3393d422
SW		 96 resets = <&tegra_car 28>;
97 reset-names = "host1x";
ed39097c
TR		 98
99 #address-cells = <1>;
100 #size-cells = <1>;
101
102 ranges = <0x54000000 0x54000000 0x04000000>;
103
58ecb23f 104 mpe@54040000 {
ed39097c
TR		 105 compatible = "nvidia,tegra30-mpe";
106 reg = <0x54040000 0x00040000>;
6cecf916 107 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
05849c93 108 clocks = <&tegra_car TEGRA30_CLK_MPE>;
3393d422
SW		 109 resets = <&tegra_car 60>;
110 reset-names = "mpe";
ed39097c
TR		 111 };
112
58ecb23f 113 vi@54080000 {
ed39097c
TR		 114 compatible = "nvidia,tegra30-vi";
115 reg = <0x54080000 0x00040000>;
6cecf916 116 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
05849c93 117 clocks = <&tegra_car TEGRA30_CLK_VI>;
3393d422
SW		 118 resets = <&tegra_car 20>;
119 reset-names = "vi";
ed39097c
TR		 120 };
121
58ecb23f 122 epp@540c0000 {
ed39097c
TR		 123 compatible = "nvidia,tegra30-epp";
124 reg = <0x540c0000 0x00040000>;
6cecf916 125 interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
05849c93 126 clocks = <&tegra_car TEGRA30_CLK_EPP>;
3393d422
SW		 127 resets = <&tegra_car 19>;
128 reset-names = "epp";
ed39097c
TR		 129 };
130
58ecb23f 131 isp@54100000 {
ed39097c
TR		 132 compatible = "nvidia,tegra30-isp";
133 reg = <0x54100000 0x00040000>;
6cecf916 134 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
05849c93 135 clocks = <&tegra_car TEGRA30_CLK_ISP>;
3393d422
SW		 136 resets = <&tegra_car 23>;
137 reset-names = "isp";
ed39097c
TR		 138 };
139
58ecb23f 140 gr2d@54140000 {
ed39097c
TR		 141 compatible = "nvidia,tegra30-gr2d";
142 reg = <0x54140000 0x00040000>;
6cecf916 143 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
da45d738 144 clocks = <&tegra_car TEGRA30_CLK_GR2D>;
3393d422
SW		 145 resets = <&tegra_car 21>;
146 reset-names = "2d";
ed39097c
TR		 147 };
148
58ecb23f 149 gr3d@54180000 {
ed39097c
TR		 150 compatible = "nvidia,tegra30-gr3d";
151 reg = <0x54180000 0x00040000>;
c71d3909
TR		 152 clocks = <&tegra_car TEGRA30_CLK_GR3D
153 &tegra_car TEGRA30_CLK_GR3D2>;
1cbc733d 154 clock-names = "3d", "3d2";
3393d422
SW		 155 resets = <&tegra_car 24>,
156 <&tegra_car 98>;
157 reset-names = "3d", "3d2";
ed39097c
TR		 158 };
159
160 dc@54200000 {
05465f4e 161 compatible = "nvidia,tegra30-dc", "nvidia,tegra20-dc";
ed39097c 162 reg = <0x54200000 0x00040000>;
6cecf916 163 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 164 clocks = <&tegra_car TEGRA30_CLK_DISP1>,
165 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 166 clock-names = "dc", "parent";
3393d422
SW		 167 resets = <&tegra_car 27>;
168 reset-names = "dc";
ed39097c 169
6d9adf6f
TR		 170 iommus = <&mc TEGRA_SWGROUP_DC>;
171
688b56b4
TR		 172 nvidia,head = <0>;
173
ed39097c
TR		 174 rgb {
175 status = "disabled";
176 };
177 };
178
179 dc@54240000 {
180 compatible = "nvidia,tegra30-dc";
181 reg = <0x54240000 0x00040000>;
6cecf916 182 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 183 clocks = <&tegra_car TEGRA30_CLK_DISP2>,
184 <&tegra_car TEGRA30_CLK_PLL_P>;
d8f64797 185 clock-names = "dc", "parent";
3393d422
SW		 186 resets = <&tegra_car 26>;
187 reset-names = "dc";
ed39097c 188
6d9adf6f
TR		 189 iommus = <&mc TEGRA_SWGROUP_DCB>;
190
688b56b4
TR		 191 nvidia,head = <1>;
192
ed39097c
TR		 193 rgb {
194 status = "disabled";
195 };
196 };
197
58ecb23f 198 hdmi@54280000 {
ed39097c
TR		 199 compatible = "nvidia,tegra30-hdmi";
200 reg = <0x54280000 0x00040000>;
6cecf916 201 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
05849c93
HD		 202 clocks = <&tegra_car TEGRA30_CLK_HDMI>,
203 <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>;
1cbc733d 204 clock-names = "hdmi", "parent";
3393d422
SW		 205 resets = <&tegra_car 51>;
206 reset-names = "hdmi";
ed39097c
TR		 207 status = "disabled";
208 };
209
58ecb23f 210 tvo@542c0000 {
ed39097c
TR		 211 compatible = "nvidia,tegra30-tvo";
212 reg = <0x542c0000 0x00040000>;
6cecf916 213 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
05849c93 214 clocks = <&tegra_car TEGRA30_CLK_TVO>;
ed39097c
TR		 215 status = "disabled";
216 };
217
58ecb23f 218 dsi@54300000 {
ed39097c
TR		 219 compatible = "nvidia,tegra30-dsi";
220 reg = <0x54300000 0x00040000>;
05849c93 221 clocks = <&tegra_car TEGRA30_CLK_DSIA>;
3393d422
SW		 222 resets = <&tegra_car 48>;
223 reset-names = "dsi";
ed39097c
TR		 224 status = "disabled";
225 };
226 };
227
2cda1880 228 timer@50040600 {
73368ba0
SW		 229 compatible = "arm,cortex-a9-twd-timer";
230 reg = <0x50040600 0x20>;
6cecf916
SW		 231 interrupts = <GIC_PPI 13
232 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
05849c93 233 clocks = <&tegra_car TEGRA30_CLK_TWD>;
73368ba0
SW		 234 };
235
58ecb23f 236 intc: interrupt-controller@50041000 {
c3e00a0e 237 compatible = "arm,cortex-a9-gic";
5ff48887
SW		 238 reg = <0x50041000 0x1000
239 0x50040100 0x0100>;
2eaab06e
SW		 240 interrupt-controller;
241 #interrupt-cells = <3>;
c3e00a0e
PDS		 242 };
243
58ecb23f 244 cache-controller@50043000 {
bb2c1de9
SW		 245 compatible = "arm,pl310-cache";
246 reg = <0x50043000 0x1000>;
247 arm,data-latency = <6 6 2>;
248 arm,tag-latency = <5 5 2>;
249 cache-unified;
250 cache-level = <2>;
251 };
252
2f2b7fb2
SW		 253 timer@60005000 {
254 compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
255 reg = <0x60005000 0x400>;
6cecf916
SW		 256 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
257 <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
258 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
259 <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
260 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
261 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
05849c93 262 clocks = <&tegra_car TEGRA30_CLK_TIMER>;
2f2b7fb2
SW		 263 };
264
58ecb23f 265 tegra_car: clock@60006000 {
95985667
PG		 266 compatible = "nvidia,tegra30-car";
267 reg = <0x60006000 0x1000>;
268 #clock-cells = <1>;
3393d422 269 #reset-cells = <1>;
95985667
PG		 270 };
271
b1023134
TR		 272 flow-controller@60007000 {
273 compatible = "nvidia,tegra30-flowctrl";
274 reg = <0x60007000 0x1000>;
275 };
276
58ecb23f 277 apbdma: dma@6000a000 {
8051b75a
SW		 278 compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
279 reg = <0x6000a000 0x1400>;
6cecf916
SW		 280 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
281 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
282 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
283 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
284 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
285 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
286 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
287 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
288 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
289 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
290 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
291 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
292 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
293 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
294 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
295 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
296 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
297 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
298 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
299 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
300 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
301 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>,
302 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
303 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
304 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
305 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
306 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
307 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>,
308 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>,
309 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
310 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
311 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
05849c93 312 clocks = <&tegra_car TEGRA30_CLK_APBDMA>;
3393d422
SW		 313 resets = <&tegra_car 34>;
314 reset-names = "dma";
034d023f 315 #dma-cells = <1>;
8051b75a
SW		 316 };
317
58ecb23f 318 ahb: ahb@6000c004 {
c04abb3a
SW		 319 compatible = "nvidia,tegra30-ahb";
320 reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e
PDS		 321 };
322
58ecb23f 323 gpio: gpio@6000d000 {
35f210ec 324 compatible = "nvidia,tegra30-gpio";
95decf84 325 reg = <0x6000d000 0x1000>;
6cecf916
SW		 326 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
327 <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
328 <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
329 <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
330 <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
331 <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
332 <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
333 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
c3e00a0e
PDS		 334 #gpio-cells = <2>;
335 gpio-controller;
6f74dc9b
SW		 336 #interrupt-cells = <2>;
337 interrupt-controller;
c3e00a0e
PDS		 338 };
339
155dfc7b
PDS		 340 apbmisc@70000800 {
341 compatible = "nvidia,tegra30-apbmisc", "nvidia,tegra20-apbmisc";
342 reg = <0x70000800 0x64 /* Chip revision */
343 0x70000008 0x04>; /* Strapping options */
344 };
345
58ecb23f 346 pinmux: pinmux@70000868 {
c04abb3a 347 compatible = "nvidia,tegra30-pinmux";
322337b8
PR		 348 reg = <0x70000868 0xd4 /* Pad control registers */
349 0x70003000 0x3e4>; /* Mux registers */
c04abb3a
SW		 350 };
351
b6551bb9
LD		 352 /*
353 * There are two serial driver i.e. 8250 based simple serial
354 * driver and APB DMA based serial driver for higher baudrate
355 * and performace. To enable the 8250 based driver, the compatible
356 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
357 * the APB DMA based serial driver, the comptible is
358 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
359 */
360 uarta: serial@70006000 {
c3e00a0e
PDS		 361 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
362 reg = <0x70006000 0x40>;
363 reg-shift = <2>;
6cecf916 364 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
05849c93 365 clocks = <&tegra_car TEGRA30_CLK_UARTA>;
3393d422
SW		 366 resets = <&tegra_car 6>;
367 reset-names = "serial";
034d023f
SW		 368 dmas = <&apbdma 8>, <&apbdma 8>;
369 dma-names = "rx", "tx";
223ef78d 370 status = "disabled";
c3e00a0e
PDS		 371 };
372
b6551bb9 373 uartb: serial@70006040 {
c3e00a0e
PDS		 374 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
375 reg = <0x70006040 0x40>;
376 reg-shift = <2>;
6cecf916 377 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
05849c93 378 clocks = <&tegra_car TEGRA30_CLK_UARTB>;
3393d422
SW		 379 resets = <&tegra_car 7>;
380 reset-names = "serial";
034d023f
SW		 381 dmas = <&apbdma 9>, <&apbdma 9>;
382 dma-names = "rx", "tx";
223ef78d 383 status = "disabled";
c3e00a0e
PDS		 384 };
385
b6551bb9 386 uartc: serial@70006200 {
c3e00a0e
PDS		 387 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
388 reg = <0x70006200 0x100>;
389 reg-shift = <2>;
6cecf916 390 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
05849c93 391 clocks = <&tegra_car TEGRA30_CLK_UARTC>;
3393d422
SW		 392 resets = <&tegra_car 55>;
393 reset-names = "serial";
034d023f
SW		 394 dmas = <&apbdma 10>, <&apbdma 10>;
395 dma-names = "rx", "tx";
223ef78d 396 status = "disabled";
c3e00a0e
PDS		 397 };
398
b6551bb9 399 uartd: serial@70006300 {
c3e00a0e
PDS		 400 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
401 reg = <0x70006300 0x100>;
402 reg-shift = <2>;
6cecf916 403 interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
05849c93 404 clocks = <&tegra_car TEGRA30_CLK_UARTD>;
3393d422
SW		 405 resets = <&tegra_car 65>;
406 reset-names = "serial";
034d023f
SW		 407 dmas = <&apbdma 19>, <&apbdma 19>;
408 dma-names = "rx", "tx";
223ef78d 409 status = "disabled";
c3e00a0e
PDS		 410 };
411
b6551bb9 412 uarte: serial@70006400 {
c3e00a0e
PDS		 413 compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
414 reg = <0x70006400 0x100>;
415 reg-shift = <2>;
6cecf916 416 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>;
05849c93 417 clocks = <&tegra_car TEGRA30_CLK_UARTE>;
3393d422
SW		 418 resets = <&tegra_car 66>;
419 reset-names = "serial";
034d023f
SW		 420 dmas = <&apbdma 20>, <&apbdma 20>;
421 dma-names = "rx", "tx";
223ef78d 422 status = "disabled";
c3e00a0e
PDS		 423 };
424
58ecb23f 425 pwm: pwm@7000a000 {
140fd977
TR		 426 compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
427 reg = <0x7000a000 0x100>;
428 #pwm-cells = <2>;
05849c93 429 clocks = <&tegra_car TEGRA30_CLK_PWM>;
3393d422
SW		 430 resets = <&tegra_car 17>;
431 reset-names = "pwm";
b69cd984 432 status = "disabled";
140fd977
TR		 433 };
434
58ecb23f 435 rtc@7000e000 {
380e04ac
SW		 436 compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
437 reg = <0x7000e000 0x100>;
6cecf916 438 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
05849c93 439 clocks = <&tegra_car TEGRA30_CLK_RTC>;
380e04ac
SW		 440 };
441
c04abb3a 442 i2c@7000c000 {
c04abb3a
SW		 443 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
444 reg = <0x7000c000 0x100>;
6cecf916 445 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 446 #address-cells = <1>;
447 #size-cells = <0>;
05849c93
HD		 448 clocks = <&tegra_car TEGRA30_CLK_I2C1>,
449 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 450 clock-names = "div-clk", "fast-clk";
3393d422
SW		 451 resets = <&tegra_car 12>;
452 reset-names = "i2c";
034d023f
SW		 453 dmas = <&apbdma 21>, <&apbdma 21>;
454 dma-names = "rx", "tx";
223ef78d 455 status = "disabled";
c3e00a0e
PDS		 456 };
457
c04abb3a 458 i2c@7000c400 {
c04abb3a
SW		 459 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
460 reg = <0x7000c400 0x100>;
6cecf916 461 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 462 #address-cells = <1>;
463 #size-cells = <0>;
05849c93
HD		 464 clocks = <&tegra_car TEGRA30_CLK_I2C2>,
465 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 466 clock-names = "div-clk", "fast-clk";
3393d422
SW		 467 resets = <&tegra_car 54>;
468 reset-names = "i2c";
034d023f
SW		 469 dmas = <&apbdma 22>, <&apbdma 22>;
470 dma-names = "rx", "tx";
223ef78d 471 status = "disabled";
c3e00a0e
PDS		 472 };
473
c04abb3a 474 i2c@7000c500 {
c04abb3a
SW		 475 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
476 reg = <0x7000c500 0x100>;
6cecf916 477 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 478 #address-cells = <1>;
479 #size-cells = <0>;
05849c93
HD		 480 clocks = <&tegra_car TEGRA30_CLK_I2C3>,
481 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 482 clock-names = "div-clk", "fast-clk";
3393d422
SW		 483 resets = <&tegra_car 67>;
484 reset-names = "i2c";
034d023f
SW		 485 dmas = <&apbdma 23>, <&apbdma 23>;
486 dma-names = "rx", "tx";
223ef78d 487 status = "disabled";
c3e00a0e
PDS		 488 };
489
c04abb3a 490 i2c@7000c700 {
c04abb3a
SW		 491 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
492 reg = <0x7000c700 0x100>;
6cecf916 493 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 494 #address-cells = <1>;
495 #size-cells = <0>;
05849c93
HD		 496 clocks = <&tegra_car TEGRA30_CLK_I2C4>,
497 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
3393d422
SW		 498 resets = <&tegra_car 103>;
499 reset-names = "i2c";
1cbc733d 500 clock-names = "div-clk", "fast-clk";
034d023f
SW		 501 dmas = <&apbdma 26>, <&apbdma 26>;
502 dma-names = "rx", "tx";
223ef78d 503 status = "disabled";
c3e00a0e
PDS		 504 };
505
c04abb3a 506 i2c@7000d000 {
c04abb3a
SW		 507 compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
508 reg = <0x7000d000 0x100>;
6cecf916 509 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
2eaab06e
SW		 510 #address-cells = <1>;
511 #size-cells = <0>;
05849c93
HD		 512 clocks = <&tegra_car TEGRA30_CLK_I2C5>,
513 <&tegra_car TEGRA30_CLK_PLL_P_OUT3>;
1cbc733d 514 clock-names = "div-clk", "fast-clk";
3393d422
SW		 515 resets = <&tegra_car 47>;
516 reset-names = "i2c";
034d023f
SW		 517 dmas = <&apbdma 24>, <&apbdma 24>;
518 dma-names = "rx", "tx";
223ef78d 519 status = "disabled";
c04abb3a
SW		 520 };
521
a86b0db3
LD		 522 spi@7000d400 {
523 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
524 reg = <0x7000d400 0x200>;
6cecf916 525 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 526 #address-cells = <1>;
527 #size-cells = <0>;
05849c93 528 clocks = <&tegra_car TEGRA30_CLK_SBC1>;
3393d422
SW		 529 resets = <&tegra_car 41>;
530 reset-names = "spi";
034d023f
SW		 531 dmas = <&apbdma 15>, <&apbdma 15>;
532 dma-names = "rx", "tx";
a86b0db3
LD		 533 status = "disabled";
534 };
535
536 spi@7000d600 {
537 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
538 reg = <0x7000d600 0x200>;
6cecf916 539 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 540 #address-cells = <1>;
541 #size-cells = <0>;
05849c93 542 clocks = <&tegra_car TEGRA30_CLK_SBC2>;
3393d422
SW		 543 resets = <&tegra_car 44>;
544 reset-names = "spi";
034d023f
SW		 545 dmas = <&apbdma 16>, <&apbdma 16>;
546 dma-names = "rx", "tx";
a86b0db3
LD		 547 status = "disabled";
548 };
549
550 spi@7000d800 {
551 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
57471c8d 552 reg = <0x7000d800 0x200>;
6cecf916 553 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 554 #address-cells = <1>;
555 #size-cells = <0>;
05849c93 556 clocks = <&tegra_car TEGRA30_CLK_SBC3>;
3393d422
SW		 557 resets = <&tegra_car 46>;
558 reset-names = "spi";
034d023f
SW		 559 dmas = <&apbdma 17>, <&apbdma 17>;
560 dma-names = "rx", "tx";
a86b0db3
LD		 561 status = "disabled";
562 };
563
564 spi@7000da00 {
565 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
566 reg = <0x7000da00 0x200>;
6cecf916 567 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 568 #address-cells = <1>;
569 #size-cells = <0>;
05849c93 570 clocks = <&tegra_car TEGRA30_CLK_SBC4>;
3393d422
SW		 571 resets = <&tegra_car 68>;
572 reset-names = "spi";
034d023f
SW		 573 dmas = <&apbdma 18>, <&apbdma 18>;
574 dma-names = "rx", "tx";
a86b0db3
LD		 575 status = "disabled";
576 };
577
578 spi@7000dc00 {
579 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
580 reg = <0x7000dc00 0x200>;
6cecf916 581 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 582 #address-cells = <1>;
583 #size-cells = <0>;
05849c93 584 clocks = <&tegra_car TEGRA30_CLK_SBC5>;
3393d422
SW		 585 resets = <&tegra_car 104>;
586 reset-names = "spi";
034d023f
SW		 587 dmas = <&apbdma 27>, <&apbdma 27>;
588 dma-names = "rx", "tx";
a86b0db3
LD		 589 status = "disabled";
590 };
591
592 spi@7000de00 {
593 compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
594 reg = <0x7000de00 0x200>;
6cecf916 595 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
a86b0db3
LD		 596 #address-cells = <1>;
597 #size-cells = <0>;
05849c93 598 clocks = <&tegra_car TEGRA30_CLK_SBC6>;
3393d422
SW		 599 resets = <&tegra_car 106>;
600 reset-names = "spi";
034d023f
SW		 601 dmas = <&apbdma 28>, <&apbdma 28>;
602 dma-names = "rx", "tx";
a86b0db3
LD		 603 status = "disabled";
604 };
605
58ecb23f 606 kbc@7000e200 {
699ed4b9
LD		 607 compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
608 reg = <0x7000e200 0x100>;
6cecf916 609 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
05849c93 610 clocks = <&tegra_car TEGRA30_CLK_KBC>;
3393d422
SW		 611 resets = <&tegra_car 36>;
612 reset-names = "kbc";
699ed4b9
LD		 613 status = "disabled";
614 };
615
58ecb23f 616 pmc@7000e400 {
2b84e53b 617 compatible = "nvidia,tegra30-pmc";
c04abb3a 618 reg = <0x7000e400 0x400>;
05849c93 619 clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>;
7021d122 620 clock-names = "pclk", "clk32k_in";
c04abb3a
SW		 621 };
622
a9fe468f 623 mc: memory-controller@7000f000 {
c04abb3a 624 compatible = "nvidia,tegra30-mc";
a9fe468f
TR		 625 reg = <0x7000f000 0x400>;
626 clocks = <&tegra_car TEGRA30_CLK_MC>;
627 clock-names = "mc";
628
6cecf916 629 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
c04abb3a 630
a9fe468f 631 #iommu-cells = <1>;
c3e00a0e 632 };
9ee6a5c4 633
155dfc7b
PDS		 634 fuse@7000f800 {
635 compatible = "nvidia,tegra30-efuse";
636 reg = <0x7000f800 0x400>;
637 clocks = <&tegra_car TEGRA30_CLK_FUSE>;
638 clock-names = "fuse";
639 resets = <&tegra_car 39>;
640 reset-names = "fuse";
641 };
642
58ecb23f 643 ahub@70080000 {
9ee6a5c4 644 compatible = "nvidia,tegra30-ahub";
5ff48887
SW		 645 reg = <0x70080000 0x200
646 0x70080200 0x100>;
6cecf916 647 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
05849c93 648 clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>,
2bd541ff
SW		 649 <&tegra_car TEGRA30_CLK_APBIF>;
650 clock-names = "d_audio", "apbif";
3393d422
SW		 651 resets = <&tegra_car 106>, /* d_audio */
652 <&tegra_car 107>, /* apbif */
653 <&tegra_car 30>, /* i2s0 */
654 <&tegra_car 11>, /* i2s1 */
655 <&tegra_car 18>, /* i2s2 */
656 <&tegra_car 101>, /* i2s3 */
657 <&tegra_car 102>, /* i2s4 */
658 <&tegra_car 108>, /* dam0 */
659 <&tegra_car 109>, /* dam1 */
660 <&tegra_car 110>, /* dam2 */
661 <&tegra_car 10>; /* spdif */
662 reset-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
663 "i2s3", "i2s4", "dam0", "dam1", "dam2",
664 "spdif";
034d023f
SW		 665 dmas = <&apbdma 1>, <&apbdma 1>,
666 <&apbdma 2>, <&apbdma 2>,
667 <&apbdma 3>, <&apbdma 3>,
668 <&apbdma 4>, <&apbdma 4>;
669 dma-names = "rx0", "tx0", "rx1", "tx1", "rx2", "tx2",
670 "rx3", "tx3";
9ee6a5c4
SW		 671 ranges;
672 #address-cells = <1>;
673 #size-cells = <1>;
674
675 tegra_i2s0: i2s@70080300 {
676 compatible = "nvidia,tegra30-i2s";
677 reg = <0x70080300 0x100>;
678 nvidia,ahub-cif-ids = <4 4>;
05849c93 679 clocks = <&tegra_car TEGRA30_CLK_I2S0>;
3393d422
SW		 680 resets = <&tegra_car 30>;
681 reset-names = "i2s";
223ef78d 682 status = "disabled";
9ee6a5c4
SW		 683 };
684
685 tegra_i2s1: i2s@70080400 {
686 compatible = "nvidia,tegra30-i2s";
687 reg = <0x70080400 0x100>;
688 nvidia,ahub-cif-ids = <5 5>;
05849c93 689 clocks = <&tegra_car TEGRA30_CLK_I2S1>;
3393d422
SW		 690 resets = <&tegra_car 11>;
691 reset-names = "i2s";
223ef78d 692 status = "disabled";
9ee6a5c4
SW		 693 };
694
695 tegra_i2s2: i2s@70080500 {
696 compatible = "nvidia,tegra30-i2s";
697 reg = <0x70080500 0x100>;
698 nvidia,ahub-cif-ids = <6 6>;
05849c93 699 clocks = <&tegra_car TEGRA30_CLK_I2S2>;
3393d422
SW		 700 resets = <&tegra_car 18>;
701 reset-names = "i2s";
223ef78d 702 status = "disabled";
9ee6a5c4
SW		 703 };
704
705 tegra_i2s3: i2s@70080600 {
706 compatible = "nvidia,tegra30-i2s";
707 reg = <0x70080600 0x100>;
708 nvidia,ahub-cif-ids = <7 7>;
05849c93 709 clocks = <&tegra_car TEGRA30_CLK_I2S3>;
3393d422
SW		 710 resets = <&tegra_car 101>;
711 reset-names = "i2s";
223ef78d 712 status = "disabled";
9ee6a5c4
SW		 713 };
714
715 tegra_i2s4: i2s@70080700 {
716 compatible = "nvidia,tegra30-i2s";
717 reg = <0x70080700 0x100>;
718 nvidia,ahub-cif-ids = <8 8>;
05849c93 719 clocks = <&tegra_car TEGRA30_CLK_I2S4>;
3393d422
SW		 720 resets = <&tegra_car 102>;
721 reset-names = "i2s";
223ef78d 722 status = "disabled";
9ee6a5c4
SW		 723 };
724 };
7868a9bc 725
c04abb3a
SW		 726 sdhci@78000000 {
727 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
728 reg = <0x78000000 0x200>;
6cecf916 729 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
05849c93 730 clocks = <&tegra_car TEGRA30_CLK_SDMMC1>;
3393d422
SW		 731 resets = <&tegra_car 14>;
732 reset-names = "sdhci";
223ef78d 733 status = "disabled";
7868a9bc 734 };
ecf43742 735
c04abb3a
SW		 736 sdhci@78000200 {
737 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
738 reg = <0x78000200 0x200>;
6cecf916 739 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
05849c93 740 clocks = <&tegra_car TEGRA30_CLK_SDMMC2>;
3393d422
SW		 741 resets = <&tegra_car 9>;
742 reset-names = "sdhci";
223ef78d 743 status = "disabled";
ecf43742 744 };
54174a33 745
c04abb3a
SW		 746 sdhci@78000400 {
747 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
748 reg = <0x78000400 0x200>;
6cecf916 749 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
05849c93 750 clocks = <&tegra_car TEGRA30_CLK_SDMMC3>;
3393d422
SW		 751 resets = <&tegra_car 69>;
752 reset-names = "sdhci";
223ef78d 753 status = "disabled";
c04abb3a
SW		 754 };
755
756 sdhci@78000600 {
757 compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
758 reg = <0x78000600 0x200>;
6cecf916 759 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
05849c93 760 clocks = <&tegra_car TEGRA30_CLK_SDMMC4>;
3393d422
SW		 761 resets = <&tegra_car 15>;
762 reset-names = "sdhci";
223ef78d 763 status = "disabled";
c04abb3a
SW		 764 };
765
cc34c9f7
TT		 766 usb@7d000000 {
767 compatible = "nvidia,tegra30-ehci", "usb-ehci";
768 reg = <0x7d000000 0x4000>;
769 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
770 phy_type = "utmi";
771 clocks = <&tegra_car TEGRA30_CLK_USBD>;
3393d422
SW		 772 resets = <&tegra_car 22>;
773 reset-names = "usb";
cc34c9f7
TT		 774 nvidia,needs-double-reset;
775 nvidia,phy = <&phy1>;
776 status = "disabled";
777 };
778
779 phy1: usb-phy@7d000000 {
780 compatible = "nvidia,tegra30-usb-phy";
781 reg = <0x7d000000 0x4000 0x7d000000 0x4000>;
782 phy_type = "utmi";
783 clocks = <&tegra_car TEGRA30_CLK_USBD>,
784 <&tegra_car TEGRA30_CLK_PLL_U>,
785 <&tegra_car TEGRA30_CLK_USBD>;
786 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 787 resets = <&tegra_car 22>, <&tegra_car 22>;
788 reset-names = "usb", "utmi-pads";
cc34c9f7
TT		 789 nvidia,hssync-start-delay = <9>;
790 nvidia,idle-wait-delay = <17>;
791 nvidia,elastic-limit = <16>;
792 nvidia,term-range-adj = <6>;
793 nvidia,xcvr-setup = <51>;
794 nvidia.xcvr-setup-use-fuses;
795 nvidia,xcvr-lsfslew = <1>;
796 nvidia,xcvr-lsrslew = <1>;
797 nvidia,xcvr-hsslew = <32>;
798 nvidia,hssquelch-level = <2>;
799 nvidia,hsdiscon-level = <5>;
308efde2 800 nvidia,has-utmi-pad-registers;
cc34c9f7
TT		 801 status = "disabled";
802 };
803
804 usb@7d004000 {
805 compatible = "nvidia,tegra30-ehci", "usb-ehci";
806 reg = <0x7d004000 0x4000>;
807 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
fd6441ec 808 phy_type = "utmi";
cc34c9f7 809 clocks = <&tegra_car TEGRA30_CLK_USB2>;
3393d422
SW		 810 resets = <&tegra_car 58>;
811 reset-names = "usb";
cc34c9f7
TT		 812 nvidia,phy = <&phy2>;
813 status = "disabled";
814 };
815
816 phy2: usb-phy@7d004000 {
817 compatible = "nvidia,tegra30-usb-phy";
fd6441ec
EB		 818 reg = <0x7d004000 0x4000 0x7d000000 0x4000>;
819 phy_type = "utmi";
cc34c9f7
TT		 820 clocks = <&tegra_car TEGRA30_CLK_USB2>,
821 <&tegra_car TEGRA30_CLK_PLL_U>,
fd6441ec
EB		 822 <&tegra_car TEGRA30_CLK_USBD>;
823 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 824 resets = <&tegra_car 58>, <&tegra_car 22>;
825 reset-names = "usb", "utmi-pads";
fd6441ec
EB		 826 nvidia,hssync-start-delay = <9>;
827 nvidia,idle-wait-delay = <17>;
828 nvidia,elastic-limit = <16>;
829 nvidia,term-range-adj = <6>;
830 nvidia,xcvr-setup = <51>;
831 nvidia.xcvr-setup-use-fuses;
832 nvidia,xcvr-lsfslew = <2>;
833 nvidia,xcvr-lsrslew = <2>;
834 nvidia,xcvr-hsslew = <32>;
835 nvidia,hssquelch-level = <2>;
836 nvidia,hsdiscon-level = <5>;
cc34c9f7
TT		 837 status = "disabled";
838 };
839
840 usb@7d008000 {
841 compatible = "nvidia,tegra30-ehci", "usb-ehci";
842 reg = <0x7d008000 0x4000>;
843 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
844 phy_type = "utmi";
845 clocks = <&tegra_car TEGRA30_CLK_USB3>;
3393d422
SW		 846 resets = <&tegra_car 59>;
847 reset-names = "usb";
cc34c9f7
TT		 848 nvidia,phy = <&phy3>;
849 status = "disabled";
850 };
851
852 phy3: usb-phy@7d008000 {
853 compatible = "nvidia,tegra30-usb-phy";
854 reg = <0x7d008000 0x4000 0x7d000000 0x4000>;
855 phy_type = "utmi";
856 clocks = <&tegra_car TEGRA30_CLK_USB3>,
857 <&tegra_car TEGRA30_CLK_PLL_U>,
858 <&tegra_car TEGRA30_CLK_USBD>;
859 clock-names = "reg", "pll_u", "utmi-pads";
308efde2
TT		 860 resets = <&tegra_car 59>, <&tegra_car 22>;
861 reset-names = "usb", "utmi-pads";
cc34c9f7
TT		 862 nvidia,hssync-start-delay = <0>;
863 nvidia,idle-wait-delay = <17>;
864 nvidia,elastic-limit = <16>;
865 nvidia,term-range-adj = <6>;
866 nvidia,xcvr-setup = <51>;
867 nvidia.xcvr-setup-use-fuses;
868 nvidia,xcvr-lsfslew = <2>;
869 nvidia,xcvr-lsrslew = <2>;
870 nvidia,xcvr-hsslew = <32>;
871 nvidia,hssquelch-level = <2>;
872 nvidia,hsdiscon-level = <5>;
873 status = "disabled";
874 };
875
7d19a34a
HD		 876 cpus {
877 #address-cells = <1>;
878 #size-cells = <0>;
879
880 cpu@0 {
881 device_type = "cpu";
882 compatible = "arm,cortex-a9";
883 reg = <0>;
884 };
885
886 cpu@1 {
887 device_type = "cpu";
888 compatible = "arm,cortex-a9";
889 reg = <1>;
890 };
891
892 cpu@2 {
893 device_type = "cpu";
894 compatible = "arm,cortex-a9";
895 reg = <2>;
896 };
897
898 cpu@3 {
899 device_type = "cpu";
900 compatible = "arm,cortex-a9";
901 reg = <3>;
902 };
903 };
904
c04abb3a
SW		 905 pmu {
906 compatible = "arm,cortex-a9-pmu";
6cecf916
SW		 907 interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
908 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
909 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
910 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>;
54174a33 911 };
c3e00a0e 912};
Linux kernel - Deliverables
This page took 0.37206 seconds and 5 git commands to generate.