Commit | Line | Data |
---|---|---|
05849c93 | 1 | #include <dt-bindings/clock/tegra30-car.h> |
3325f1bc | 2 | #include <dt-bindings/gpio/tegra-gpio.h> |
6cecf916 | 3 | #include <dt-bindings/interrupt-controller/arm-gic.h> |
3325f1bc | 4 | |
1bd0bd49 | 5 | #include "skeleton.dtsi" |
c3e00a0e PDS |
6 | |
7 | / { | |
8 | compatible = "nvidia,tegra30"; | |
9 | interrupt-parent = <&intc>; | |
10 | ||
b6551bb9 LD |
11 | aliases { |
12 | serial0 = &uarta; | |
13 | serial1 = &uartb; | |
14 | serial2 = &uartc; | |
15 | serial3 = &uartd; | |
16 | serial4 = &uarte; | |
17 | }; | |
18 | ||
e07e3dbd TR |
19 | pcie-controller { |
20 | compatible = "nvidia,tegra30-pcie"; | |
21 | device_type = "pci"; | |
22 | reg = <0x00003000 0x00000800 /* PADS registers */ | |
23 | 0x00003800 0x00000200 /* AFI registers */ | |
24 | 0x10000000 0x10000000>; /* configuration space */ | |
25 | reg-names = "pads", "afi", "cs"; | |
26 | interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH /* controller interrupt */ | |
27 | GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ | |
28 | interrupt-names = "intr", "msi"; | |
29 | ||
30 | bus-range = <0x00 0xff>; | |
31 | #address-cells = <3>; | |
32 | #size-cells = <2>; | |
33 | ||
34 | ranges = <0x82000000 0 0x00000000 0x00000000 0 0x00001000 /* port 0 configuration space */ | |
35 | 0x82000000 0 0x00001000 0x00001000 0 0x00001000 /* port 1 configuration space */ | |
36 | 0x82000000 0 0x00004000 0x00004000 0 0x00001000 /* port 2 configuration space */ | |
37 | 0x81000000 0 0 0x02000000 0 0x00010000 /* downstream I/O */ | |
d7283c11 JA |
38 | 0x82000000 0 0x20000000 0x20000000 0 0x08000000 /* non-prefetchable memory */ |
39 | 0xc2000000 0 0x28000000 0x28000000 0 0x18000000>; /* prefetchable memory */ | |
e07e3dbd TR |
40 | |
41 | clocks = <&tegra_car TEGRA30_CLK_PCIE>, | |
42 | <&tegra_car TEGRA30_CLK_AFI>, | |
43 | <&tegra_car TEGRA30_CLK_PCIEX>, | |
44 | <&tegra_car TEGRA30_CLK_PLL_E>, | |
45 | <&tegra_car TEGRA30_CLK_CML0>; | |
46 | clock-names = "pex", "afi", "pcie_xclk", "pll_e", "cml"; | |
47 | status = "disabled"; | |
48 | ||
49 | pci@1,0 { | |
50 | device_type = "pci"; | |
51 | assigned-addresses = <0x82000800 0 0x00000000 0 0x1000>; | |
52 | reg = <0x000800 0 0 0 0>; | |
53 | status = "disabled"; | |
54 | ||
55 | #address-cells = <3>; | |
56 | #size-cells = <2>; | |
57 | ranges; | |
58 | ||
59 | nvidia,num-lanes = <2>; | |
60 | }; | |
61 | ||
62 | pci@2,0 { | |
63 | device_type = "pci"; | |
64 | assigned-addresses = <0x82001000 0 0x00001000 0 0x1000>; | |
65 | reg = <0x001000 0 0 0 0>; | |
66 | status = "disabled"; | |
67 | ||
68 | #address-cells = <3>; | |
69 | #size-cells = <2>; | |
70 | ranges; | |
71 | ||
72 | nvidia,num-lanes = <2>; | |
73 | }; | |
74 | ||
75 | pci@3,0 { | |
76 | device_type = "pci"; | |
77 | assigned-addresses = <0x82001800 0 0x00004000 0 0x1000>; | |
78 | reg = <0x001800 0 0 0 0>; | |
79 | status = "disabled"; | |
80 | ||
81 | #address-cells = <3>; | |
82 | #size-cells = <2>; | |
83 | ranges; | |
84 | ||
85 | nvidia,num-lanes = <2>; | |
86 | }; | |
87 | }; | |
88 | ||
ed39097c TR |
89 | host1x { |
90 | compatible = "nvidia,tegra30-host1x", "simple-bus"; | |
91 | reg = <0x50000000 0x00024000>; | |
6cecf916 SW |
92 | interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, /* syncpt */ |
93 | <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; /* general */ | |
05849c93 | 94 | clocks = <&tegra_car TEGRA30_CLK_HOST1X>; |
ed39097c TR |
95 | |
96 | #address-cells = <1>; | |
97 | #size-cells = <1>; | |
98 | ||
99 | ranges = <0x54000000 0x54000000 0x04000000>; | |
100 | ||
101 | mpe { | |
102 | compatible = "nvidia,tegra30-mpe"; | |
103 | reg = <0x54040000 0x00040000>; | |
6cecf916 | 104 | interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 105 | clocks = <&tegra_car TEGRA30_CLK_MPE>; |
ed39097c TR |
106 | }; |
107 | ||
108 | vi { | |
109 | compatible = "nvidia,tegra30-vi"; | |
110 | reg = <0x54080000 0x00040000>; | |
6cecf916 | 111 | interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 112 | clocks = <&tegra_car TEGRA30_CLK_VI>; |
ed39097c TR |
113 | }; |
114 | ||
115 | epp { | |
116 | compatible = "nvidia,tegra30-epp"; | |
117 | reg = <0x540c0000 0x00040000>; | |
6cecf916 | 118 | interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 119 | clocks = <&tegra_car TEGRA30_CLK_EPP>; |
ed39097c TR |
120 | }; |
121 | ||
122 | isp { | |
123 | compatible = "nvidia,tegra30-isp"; | |
124 | reg = <0x54100000 0x00040000>; | |
6cecf916 | 125 | interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 126 | clocks = <&tegra_car TEGRA30_CLK_ISP>; |
ed39097c TR |
127 | }; |
128 | ||
129 | gr2d { | |
130 | compatible = "nvidia,tegra30-gr2d"; | |
131 | reg = <0x54140000 0x00040000>; | |
6cecf916 | 132 | interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 133 | clocks = <&tegra_car TEGRA30_CLK_GR2D>; |
ed39097c TR |
134 | }; |
135 | ||
136 | gr3d { | |
137 | compatible = "nvidia,tegra30-gr3d"; | |
138 | reg = <0x54180000 0x00040000>; | |
1cbc733d PG |
139 | clocks = <&tegra_car 24 &tegra_car 98>; |
140 | clock-names = "3d", "3d2"; | |
ed39097c TR |
141 | }; |
142 | ||
143 | dc@54200000 { | |
144 | compatible = "nvidia,tegra30-dc"; | |
145 | reg = <0x54200000 0x00040000>; | |
6cecf916 | 146 | interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 HD |
147 | clocks = <&tegra_car TEGRA30_CLK_DISP1>, |
148 | <&tegra_car TEGRA30_CLK_PLL_P>; | |
1cbc733d | 149 | clock-names = "disp1", "parent"; |
ed39097c TR |
150 | |
151 | rgb { | |
152 | status = "disabled"; | |
153 | }; | |
154 | }; | |
155 | ||
156 | dc@54240000 { | |
157 | compatible = "nvidia,tegra30-dc"; | |
158 | reg = <0x54240000 0x00040000>; | |
6cecf916 | 159 | interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 HD |
160 | clocks = <&tegra_car TEGRA30_CLK_DISP2>, |
161 | <&tegra_car TEGRA30_CLK_PLL_P>; | |
1cbc733d | 162 | clock-names = "disp2", "parent"; |
ed39097c TR |
163 | |
164 | rgb { | |
165 | status = "disabled"; | |
166 | }; | |
167 | }; | |
168 | ||
169 | hdmi { | |
170 | compatible = "nvidia,tegra30-hdmi"; | |
171 | reg = <0x54280000 0x00040000>; | |
6cecf916 | 172 | interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 HD |
173 | clocks = <&tegra_car TEGRA30_CLK_HDMI>, |
174 | <&tegra_car TEGRA30_CLK_PLL_D2_OUT0>; | |
1cbc733d | 175 | clock-names = "hdmi", "parent"; |
ed39097c TR |
176 | status = "disabled"; |
177 | }; | |
178 | ||
179 | tvo { | |
180 | compatible = "nvidia,tegra30-tvo"; | |
181 | reg = <0x542c0000 0x00040000>; | |
6cecf916 | 182 | interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 183 | clocks = <&tegra_car TEGRA30_CLK_TVO>; |
ed39097c TR |
184 | status = "disabled"; |
185 | }; | |
186 | ||
187 | dsi { | |
188 | compatible = "nvidia,tegra30-dsi"; | |
189 | reg = <0x54300000 0x00040000>; | |
05849c93 | 190 | clocks = <&tegra_car TEGRA30_CLK_DSIA>; |
ed39097c TR |
191 | status = "disabled"; |
192 | }; | |
193 | }; | |
194 | ||
73368ba0 SW |
195 | timer@50004600 { |
196 | compatible = "arm,cortex-a9-twd-timer"; | |
197 | reg = <0x50040600 0x20>; | |
6cecf916 SW |
198 | interrupts = <GIC_PPI 13 |
199 | (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
05849c93 | 200 | clocks = <&tegra_car TEGRA30_CLK_TWD>; |
73368ba0 SW |
201 | }; |
202 | ||
f9eb26a4 | 203 | intc: interrupt-controller { |
c3e00a0e | 204 | compatible = "arm,cortex-a9-gic"; |
5ff48887 SW |
205 | reg = <0x50041000 0x1000 |
206 | 0x50040100 0x0100>; | |
2eaab06e SW |
207 | interrupt-controller; |
208 | #interrupt-cells = <3>; | |
c3e00a0e PDS |
209 | }; |
210 | ||
bb2c1de9 SW |
211 | cache-controller { |
212 | compatible = "arm,pl310-cache"; | |
213 | reg = <0x50043000 0x1000>; | |
214 | arm,data-latency = <6 6 2>; | |
215 | arm,tag-latency = <5 5 2>; | |
216 | cache-unified; | |
217 | cache-level = <2>; | |
218 | }; | |
219 | ||
2f2b7fb2 SW |
220 | timer@60005000 { |
221 | compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer"; | |
222 | reg = <0x60005000 0x400>; | |
6cecf916 SW |
223 | interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
224 | <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, | |
225 | <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, | |
226 | <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, | |
227 | <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, | |
228 | <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; | |
05849c93 | 229 | clocks = <&tegra_car TEGRA30_CLK_TIMER>; |
2f2b7fb2 SW |
230 | }; |
231 | ||
95985667 PG |
232 | tegra_car: clock { |
233 | compatible = "nvidia,tegra30-car"; | |
234 | reg = <0x60006000 0x1000>; | |
235 | #clock-cells = <1>; | |
236 | }; | |
237 | ||
f9eb26a4 | 238 | apbdma: dma { |
8051b75a SW |
239 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
240 | reg = <0x6000a000 0x1400>; | |
6cecf916 SW |
241 | interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, |
242 | <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, | |
243 | <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, | |
244 | <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, | |
245 | <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, | |
246 | <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, | |
247 | <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, | |
248 | <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, | |
249 | <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, | |
250 | <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, | |
251 | <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, | |
252 | <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, | |
253 | <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, | |
254 | <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, | |
255 | <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
256 | <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, | |
257 | <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, | |
258 | <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, | |
259 | <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, | |
260 | <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, | |
261 | <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, | |
262 | <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, | |
263 | <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, | |
264 | <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, | |
265 | <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, | |
266 | <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, | |
267 | <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, | |
268 | <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, | |
269 | <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, | |
270 | <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, | |
271 | <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, | |
272 | <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; | |
05849c93 | 273 | clocks = <&tegra_car TEGRA30_CLK_APBDMA>; |
8051b75a SW |
274 | }; |
275 | ||
c04abb3a SW |
276 | ahb: ahb { |
277 | compatible = "nvidia,tegra30-ahb"; | |
278 | reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ | |
c3e00a0e PDS |
279 | }; |
280 | ||
f9eb26a4 | 281 | gpio: gpio { |
35f210ec | 282 | compatible = "nvidia,tegra30-gpio"; |
95decf84 | 283 | reg = <0x6000d000 0x1000>; |
6cecf916 SW |
284 | interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>, |
285 | <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>, | |
286 | <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>, | |
287 | <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>, | |
288 | <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, | |
289 | <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
290 | <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>, | |
291 | <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; | |
c3e00a0e PDS |
292 | #gpio-cells = <2>; |
293 | gpio-controller; | |
6f74dc9b SW |
294 | #interrupt-cells = <2>; |
295 | interrupt-controller; | |
c3e00a0e PDS |
296 | }; |
297 | ||
c04abb3a SW |
298 | pinmux: pinmux { |
299 | compatible = "nvidia,tegra30-pinmux"; | |
322337b8 PR |
300 | reg = <0x70000868 0xd4 /* Pad control registers */ |
301 | 0x70003000 0x3e4>; /* Mux registers */ | |
c04abb3a SW |
302 | }; |
303 | ||
b6551bb9 LD |
304 | /* |
305 | * There are two serial driver i.e. 8250 based simple serial | |
306 | * driver and APB DMA based serial driver for higher baudrate | |
307 | * and performace. To enable the 8250 based driver, the compatible | |
308 | * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable | |
309 | * the APB DMA based serial driver, the comptible is | |
310 | * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart". | |
311 | */ | |
312 | uarta: serial@70006000 { | |
c3e00a0e PDS |
313 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
314 | reg = <0x70006000 0x40>; | |
315 | reg-shift = <2>; | |
6cecf916 | 316 | interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; |
b6551bb9 | 317 | nvidia,dma-request-selector = <&apbdma 8>; |
05849c93 | 318 | clocks = <&tegra_car TEGRA30_CLK_UARTA>; |
223ef78d | 319 | status = "disabled"; |
c3e00a0e PDS |
320 | }; |
321 | ||
b6551bb9 | 322 | uartb: serial@70006040 { |
c3e00a0e PDS |
323 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
324 | reg = <0x70006040 0x40>; | |
325 | reg-shift = <2>; | |
6cecf916 | 326 | interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; |
b6551bb9 | 327 | nvidia,dma-request-selector = <&apbdma 9>; |
05849c93 | 328 | clocks = <&tegra_car TEGRA30_CLK_UARTB>; |
223ef78d | 329 | status = "disabled"; |
c3e00a0e PDS |
330 | }; |
331 | ||
b6551bb9 | 332 | uartc: serial@70006200 { |
c3e00a0e PDS |
333 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
334 | reg = <0x70006200 0x100>; | |
335 | reg-shift = <2>; | |
6cecf916 | 336 | interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
b6551bb9 | 337 | nvidia,dma-request-selector = <&apbdma 10>; |
05849c93 | 338 | clocks = <&tegra_car TEGRA30_CLK_UARTC>; |
223ef78d | 339 | status = "disabled"; |
c3e00a0e PDS |
340 | }; |
341 | ||
b6551bb9 | 342 | uartd: serial@70006300 { |
c3e00a0e PDS |
343 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
344 | reg = <0x70006300 0x100>; | |
345 | reg-shift = <2>; | |
6cecf916 | 346 | interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; |
b6551bb9 | 347 | nvidia,dma-request-selector = <&apbdma 19>; |
05849c93 | 348 | clocks = <&tegra_car TEGRA30_CLK_UARTD>; |
223ef78d | 349 | status = "disabled"; |
c3e00a0e PDS |
350 | }; |
351 | ||
b6551bb9 | 352 | uarte: serial@70006400 { |
c3e00a0e PDS |
353 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; |
354 | reg = <0x70006400 0x100>; | |
355 | reg-shift = <2>; | |
6cecf916 | 356 | interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; |
b6551bb9 | 357 | nvidia,dma-request-selector = <&apbdma 20>; |
05849c93 | 358 | clocks = <&tegra_car TEGRA30_CLK_UARTE>; |
223ef78d | 359 | status = "disabled"; |
c3e00a0e PDS |
360 | }; |
361 | ||
2b8b15da | 362 | pwm: pwm { |
140fd977 TR |
363 | compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm"; |
364 | reg = <0x7000a000 0x100>; | |
365 | #pwm-cells = <2>; | |
05849c93 | 366 | clocks = <&tegra_car TEGRA30_CLK_PWM>; |
b69cd984 | 367 | status = "disabled"; |
140fd977 TR |
368 | }; |
369 | ||
380e04ac SW |
370 | rtc { |
371 | compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc"; | |
372 | reg = <0x7000e000 0x100>; | |
6cecf916 | 373 | interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 374 | clocks = <&tegra_car TEGRA30_CLK_RTC>; |
380e04ac SW |
375 | }; |
376 | ||
c04abb3a | 377 | i2c@7000c000 { |
c04abb3a SW |
378 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
379 | reg = <0x7000c000 0x100>; | |
6cecf916 | 380 | interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
381 | #address-cells = <1>; |
382 | #size-cells = <0>; | |
05849c93 HD |
383 | clocks = <&tegra_car TEGRA30_CLK_I2C1>, |
384 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 385 | clock-names = "div-clk", "fast-clk"; |
223ef78d | 386 | status = "disabled"; |
c3e00a0e PDS |
387 | }; |
388 | ||
c04abb3a | 389 | i2c@7000c400 { |
c04abb3a SW |
390 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
391 | reg = <0x7000c400 0x100>; | |
6cecf916 | 392 | interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
393 | #address-cells = <1>; |
394 | #size-cells = <0>; | |
05849c93 HD |
395 | clocks = <&tegra_car TEGRA30_CLK_I2C2>, |
396 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 397 | clock-names = "div-clk", "fast-clk"; |
223ef78d | 398 | status = "disabled"; |
c3e00a0e PDS |
399 | }; |
400 | ||
c04abb3a | 401 | i2c@7000c500 { |
c04abb3a SW |
402 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
403 | reg = <0x7000c500 0x100>; | |
6cecf916 | 404 | interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
405 | #address-cells = <1>; |
406 | #size-cells = <0>; | |
05849c93 HD |
407 | clocks = <&tegra_car TEGRA30_CLK_I2C3>, |
408 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 409 | clock-names = "div-clk", "fast-clk"; |
223ef78d | 410 | status = "disabled"; |
c3e00a0e PDS |
411 | }; |
412 | ||
c04abb3a | 413 | i2c@7000c700 { |
c04abb3a SW |
414 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
415 | reg = <0x7000c700 0x100>; | |
6cecf916 | 416 | interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
417 | #address-cells = <1>; |
418 | #size-cells = <0>; | |
05849c93 HD |
419 | clocks = <&tegra_car TEGRA30_CLK_I2C4>, |
420 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 421 | clock-names = "div-clk", "fast-clk"; |
223ef78d | 422 | status = "disabled"; |
c3e00a0e PDS |
423 | }; |
424 | ||
c04abb3a | 425 | i2c@7000d000 { |
c04abb3a SW |
426 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
427 | reg = <0x7000d000 0x100>; | |
6cecf916 | 428 | interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; |
2eaab06e SW |
429 | #address-cells = <1>; |
430 | #size-cells = <0>; | |
05849c93 HD |
431 | clocks = <&tegra_car TEGRA30_CLK_I2C5>, |
432 | <&tegra_car TEGRA30_CLK_PLL_P_OUT3>; | |
1cbc733d | 433 | clock-names = "div-clk", "fast-clk"; |
223ef78d | 434 | status = "disabled"; |
c04abb3a SW |
435 | }; |
436 | ||
a86b0db3 LD |
437 | spi@7000d400 { |
438 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
439 | reg = <0x7000d400 0x200>; | |
6cecf916 | 440 | interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
441 | nvidia,dma-request-selector = <&apbdma 15>; |
442 | #address-cells = <1>; | |
443 | #size-cells = <0>; | |
05849c93 | 444 | clocks = <&tegra_car TEGRA30_CLK_SBC1>; |
a86b0db3 LD |
445 | status = "disabled"; |
446 | }; | |
447 | ||
448 | spi@7000d600 { | |
449 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
450 | reg = <0x7000d600 0x200>; | |
6cecf916 | 451 | interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
452 | nvidia,dma-request-selector = <&apbdma 16>; |
453 | #address-cells = <1>; | |
454 | #size-cells = <0>; | |
05849c93 | 455 | clocks = <&tegra_car TEGRA30_CLK_SBC2>; |
a86b0db3 LD |
456 | status = "disabled"; |
457 | }; | |
458 | ||
459 | spi@7000d800 { | |
460 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
57471c8d | 461 | reg = <0x7000d800 0x200>; |
6cecf916 | 462 | interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
463 | nvidia,dma-request-selector = <&apbdma 17>; |
464 | #address-cells = <1>; | |
465 | #size-cells = <0>; | |
05849c93 | 466 | clocks = <&tegra_car TEGRA30_CLK_SBC3>; |
a86b0db3 LD |
467 | status = "disabled"; |
468 | }; | |
469 | ||
470 | spi@7000da00 { | |
471 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
472 | reg = <0x7000da00 0x200>; | |
6cecf916 | 473 | interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
474 | nvidia,dma-request-selector = <&apbdma 18>; |
475 | #address-cells = <1>; | |
476 | #size-cells = <0>; | |
05849c93 | 477 | clocks = <&tegra_car TEGRA30_CLK_SBC4>; |
a86b0db3 LD |
478 | status = "disabled"; |
479 | }; | |
480 | ||
481 | spi@7000dc00 { | |
482 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
483 | reg = <0x7000dc00 0x200>; | |
6cecf916 | 484 | interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
485 | nvidia,dma-request-selector = <&apbdma 27>; |
486 | #address-cells = <1>; | |
487 | #size-cells = <0>; | |
05849c93 | 488 | clocks = <&tegra_car TEGRA30_CLK_SBC5>; |
a86b0db3 LD |
489 | status = "disabled"; |
490 | }; | |
491 | ||
492 | spi@7000de00 { | |
493 | compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink"; | |
494 | reg = <0x7000de00 0x200>; | |
6cecf916 | 495 | interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; |
a86b0db3 LD |
496 | nvidia,dma-request-selector = <&apbdma 28>; |
497 | #address-cells = <1>; | |
498 | #size-cells = <0>; | |
05849c93 | 499 | clocks = <&tegra_car TEGRA30_CLK_SBC6>; |
a86b0db3 LD |
500 | status = "disabled"; |
501 | }; | |
502 | ||
699ed4b9 LD |
503 | kbc { |
504 | compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc"; | |
505 | reg = <0x7000e200 0x100>; | |
6cecf916 | 506 | interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 507 | clocks = <&tegra_car TEGRA30_CLK_KBC>; |
699ed4b9 LD |
508 | status = "disabled"; |
509 | }; | |
510 | ||
c04abb3a | 511 | pmc { |
2b84e53b | 512 | compatible = "nvidia,tegra30-pmc"; |
c04abb3a | 513 | reg = <0x7000e400 0x400>; |
05849c93 | 514 | clocks = <&tegra_car TEGRA30_CLK_PCLK>, <&clk32k_in>; |
7021d122 | 515 | clock-names = "pclk", "clk32k_in"; |
c04abb3a SW |
516 | }; |
517 | ||
a9140aa5 | 518 | memory-controller { |
c04abb3a SW |
519 | compatible = "nvidia,tegra30-mc"; |
520 | reg = <0x7000f000 0x010 | |
521 | 0x7000f03c 0x1b4 | |
522 | 0x7000f200 0x028 | |
523 | 0x7000f284 0x17c>; | |
6cecf916 | 524 | interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; |
c04abb3a SW |
525 | }; |
526 | ||
3fbf07d8 | 527 | iommu { |
c04abb3a SW |
528 | compatible = "nvidia,tegra30-smmu"; |
529 | reg = <0x7000f010 0x02c | |
530 | 0x7000f1f0 0x010 | |
531 | 0x7000f228 0x05c>; | |
532 | nvidia,#asids = <4>; /* # of ASIDs */ | |
533 | dma-window = <0 0x40000000>; /* IOVA start & length */ | |
534 | nvidia,ahb = <&ahb>; | |
c3e00a0e | 535 | }; |
9ee6a5c4 SW |
536 | |
537 | ahub { | |
538 | compatible = "nvidia,tegra30-ahub"; | |
5ff48887 SW |
539 | reg = <0x70080000 0x200 |
540 | 0x70080200 0x100>; | |
6cecf916 | 541 | interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; |
9ee6a5c4 | 542 | nvidia,dma-request-selector = <&apbdma 1>; |
05849c93 HD |
543 | clocks = <&tegra_car TEGRA30_CLK_D_AUDIO>, |
544 | <&tegra_car TEGRA30_CLK_APBIF>, | |
545 | <&tegra_car TEGRA30_CLK_I2S0>, | |
546 | <&tegra_car TEGRA30_CLK_I2S1>, | |
547 | <&tegra_car TEGRA30_CLK_I2S2>, | |
548 | <&tegra_car TEGRA30_CLK_I2S3>, | |
549 | <&tegra_car TEGRA30_CLK_I2S4>, | |
550 | <&tegra_car TEGRA30_CLK_DAM0>, | |
551 | <&tegra_car TEGRA30_CLK_DAM1>, | |
552 | <&tegra_car TEGRA30_CLK_DAM2>, | |
553 | <&tegra_car TEGRA30_CLK_SPDIF_IN>; | |
1cbc733d PG |
554 | clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2", |
555 | "i2s3", "i2s4", "dam0", "dam1", "dam2", | |
556 | "spdif_in"; | |
9ee6a5c4 SW |
557 | ranges; |
558 | #address-cells = <1>; | |
559 | #size-cells = <1>; | |
560 | ||
561 | tegra_i2s0: i2s@70080300 { | |
562 | compatible = "nvidia,tegra30-i2s"; | |
563 | reg = <0x70080300 0x100>; | |
564 | nvidia,ahub-cif-ids = <4 4>; | |
05849c93 | 565 | clocks = <&tegra_car TEGRA30_CLK_I2S0>; |
223ef78d | 566 | status = "disabled"; |
9ee6a5c4 SW |
567 | }; |
568 | ||
569 | tegra_i2s1: i2s@70080400 { | |
570 | compatible = "nvidia,tegra30-i2s"; | |
571 | reg = <0x70080400 0x100>; | |
572 | nvidia,ahub-cif-ids = <5 5>; | |
05849c93 | 573 | clocks = <&tegra_car TEGRA30_CLK_I2S1>; |
223ef78d | 574 | status = "disabled"; |
9ee6a5c4 SW |
575 | }; |
576 | ||
577 | tegra_i2s2: i2s@70080500 { | |
578 | compatible = "nvidia,tegra30-i2s"; | |
579 | reg = <0x70080500 0x100>; | |
580 | nvidia,ahub-cif-ids = <6 6>; | |
05849c93 | 581 | clocks = <&tegra_car TEGRA30_CLK_I2S2>; |
223ef78d | 582 | status = "disabled"; |
9ee6a5c4 SW |
583 | }; |
584 | ||
585 | tegra_i2s3: i2s@70080600 { | |
586 | compatible = "nvidia,tegra30-i2s"; | |
587 | reg = <0x70080600 0x100>; | |
588 | nvidia,ahub-cif-ids = <7 7>; | |
05849c93 | 589 | clocks = <&tegra_car TEGRA30_CLK_I2S3>; |
223ef78d | 590 | status = "disabled"; |
9ee6a5c4 SW |
591 | }; |
592 | ||
593 | tegra_i2s4: i2s@70080700 { | |
594 | compatible = "nvidia,tegra30-i2s"; | |
595 | reg = <0x70080700 0x100>; | |
596 | nvidia,ahub-cif-ids = <8 8>; | |
05849c93 | 597 | clocks = <&tegra_car TEGRA30_CLK_I2S4>; |
223ef78d | 598 | status = "disabled"; |
9ee6a5c4 SW |
599 | }; |
600 | }; | |
7868a9bc | 601 | |
c04abb3a SW |
602 | sdhci@78000000 { |
603 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
604 | reg = <0x78000000 0x200>; | |
6cecf916 | 605 | interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 606 | clocks = <&tegra_car TEGRA30_CLK_SDMMC1>; |
223ef78d | 607 | status = "disabled"; |
7868a9bc | 608 | }; |
ecf43742 | 609 | |
c04abb3a SW |
610 | sdhci@78000200 { |
611 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
612 | reg = <0x78000200 0x200>; | |
6cecf916 | 613 | interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 614 | clocks = <&tegra_car TEGRA30_CLK_SDMMC2>; |
223ef78d | 615 | status = "disabled"; |
ecf43742 | 616 | }; |
54174a33 | 617 | |
c04abb3a SW |
618 | sdhci@78000400 { |
619 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
620 | reg = <0x78000400 0x200>; | |
6cecf916 | 621 | interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 622 | clocks = <&tegra_car TEGRA30_CLK_SDMMC3>; |
223ef78d | 623 | status = "disabled"; |
c04abb3a SW |
624 | }; |
625 | ||
626 | sdhci@78000600 { | |
627 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
628 | reg = <0x78000600 0x200>; | |
6cecf916 | 629 | interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
05849c93 | 630 | clocks = <&tegra_car TEGRA30_CLK_SDMMC4>; |
223ef78d | 631 | status = "disabled"; |
c04abb3a SW |
632 | }; |
633 | ||
cc34c9f7 TT |
634 | usb@7d000000 { |
635 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
636 | reg = <0x7d000000 0x4000>; | |
637 | interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
638 | phy_type = "utmi"; | |
639 | clocks = <&tegra_car TEGRA30_CLK_USBD>; | |
640 | nvidia,needs-double-reset; | |
641 | nvidia,phy = <&phy1>; | |
642 | status = "disabled"; | |
643 | }; | |
644 | ||
645 | phy1: usb-phy@7d000000 { | |
646 | compatible = "nvidia,tegra30-usb-phy"; | |
647 | reg = <0x7d000000 0x4000 0x7d000000 0x4000>; | |
648 | phy_type = "utmi"; | |
649 | clocks = <&tegra_car TEGRA30_CLK_USBD>, | |
650 | <&tegra_car TEGRA30_CLK_PLL_U>, | |
651 | <&tegra_car TEGRA30_CLK_USBD>; | |
652 | clock-names = "reg", "pll_u", "utmi-pads"; | |
653 | nvidia,hssync-start-delay = <9>; | |
654 | nvidia,idle-wait-delay = <17>; | |
655 | nvidia,elastic-limit = <16>; | |
656 | nvidia,term-range-adj = <6>; | |
657 | nvidia,xcvr-setup = <51>; | |
658 | nvidia.xcvr-setup-use-fuses; | |
659 | nvidia,xcvr-lsfslew = <1>; | |
660 | nvidia,xcvr-lsrslew = <1>; | |
661 | nvidia,xcvr-hsslew = <32>; | |
662 | nvidia,hssquelch-level = <2>; | |
663 | nvidia,hsdiscon-level = <5>; | |
664 | status = "disabled"; | |
665 | }; | |
666 | ||
667 | usb@7d004000 { | |
668 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
669 | reg = <0x7d004000 0x4000>; | |
670 | interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; | |
671 | phy_type = "ulpi"; | |
672 | clocks = <&tegra_car TEGRA30_CLK_USB2>; | |
673 | nvidia,phy = <&phy2>; | |
674 | status = "disabled"; | |
675 | }; | |
676 | ||
677 | phy2: usb-phy@7d004000 { | |
678 | compatible = "nvidia,tegra30-usb-phy"; | |
679 | reg = <0x7d004000 0x4000>; | |
680 | phy_type = "ulpi"; | |
681 | clocks = <&tegra_car TEGRA30_CLK_USB2>, | |
682 | <&tegra_car TEGRA30_CLK_PLL_U>, | |
683 | <&tegra_car TEGRA30_CLK_CDEV2>; | |
684 | clock-names = "reg", "pll_u", "ulpi-link"; | |
685 | status = "disabled"; | |
686 | }; | |
687 | ||
688 | usb@7d008000 { | |
689 | compatible = "nvidia,tegra30-ehci", "usb-ehci"; | |
690 | reg = <0x7d008000 0x4000>; | |
691 | interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
692 | phy_type = "utmi"; | |
693 | clocks = <&tegra_car TEGRA30_CLK_USB3>; | |
694 | nvidia,phy = <&phy3>; | |
695 | status = "disabled"; | |
696 | }; | |
697 | ||
698 | phy3: usb-phy@7d008000 { | |
699 | compatible = "nvidia,tegra30-usb-phy"; | |
700 | reg = <0x7d008000 0x4000 0x7d000000 0x4000>; | |
701 | phy_type = "utmi"; | |
702 | clocks = <&tegra_car TEGRA30_CLK_USB3>, | |
703 | <&tegra_car TEGRA30_CLK_PLL_U>, | |
704 | <&tegra_car TEGRA30_CLK_USBD>; | |
705 | clock-names = "reg", "pll_u", "utmi-pads"; | |
706 | nvidia,hssync-start-delay = <0>; | |
707 | nvidia,idle-wait-delay = <17>; | |
708 | nvidia,elastic-limit = <16>; | |
709 | nvidia,term-range-adj = <6>; | |
710 | nvidia,xcvr-setup = <51>; | |
711 | nvidia.xcvr-setup-use-fuses; | |
712 | nvidia,xcvr-lsfslew = <2>; | |
713 | nvidia,xcvr-lsrslew = <2>; | |
714 | nvidia,xcvr-hsslew = <32>; | |
715 | nvidia,hssquelch-level = <2>; | |
716 | nvidia,hsdiscon-level = <5>; | |
717 | status = "disabled"; | |
718 | }; | |
719 | ||
7d19a34a HD |
720 | cpus { |
721 | #address-cells = <1>; | |
722 | #size-cells = <0>; | |
723 | ||
724 | cpu@0 { | |
725 | device_type = "cpu"; | |
726 | compatible = "arm,cortex-a9"; | |
727 | reg = <0>; | |
728 | }; | |
729 | ||
730 | cpu@1 { | |
731 | device_type = "cpu"; | |
732 | compatible = "arm,cortex-a9"; | |
733 | reg = <1>; | |
734 | }; | |
735 | ||
736 | cpu@2 { | |
737 | device_type = "cpu"; | |
738 | compatible = "arm,cortex-a9"; | |
739 | reg = <2>; | |
740 | }; | |
741 | ||
742 | cpu@3 { | |
743 | device_type = "cpu"; | |
744 | compatible = "arm,cortex-a9"; | |
745 | reg = <3>; | |
746 | }; | |
747 | }; | |
748 | ||
c04abb3a SW |
749 | pmu { |
750 | compatible = "arm,cortex-a9-pmu"; | |
6cecf916 SW |
751 | interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, |
752 | <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, | |
753 | <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, | |
754 | <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>; | |
54174a33 | 755 | }; |
c3e00a0e | 756 | }; |