Commit | Line | Data |
---|---|---|
c3e00a0e PDS |
1 | /include/ "skeleton.dtsi" |
2 | ||
3 | / { | |
4 | compatible = "nvidia,tegra30"; | |
5 | interrupt-parent = <&intc>; | |
6 | ||
f9eb26a4 | 7 | intc: interrupt-controller { |
c3e00a0e | 8 | compatible = "arm,cortex-a9-gic"; |
5ff48887 SW |
9 | reg = <0x50041000 0x1000 |
10 | 0x50040100 0x0100>; | |
2eaab06e SW |
11 | interrupt-controller; |
12 | #interrupt-cells = <3>; | |
c3e00a0e PDS |
13 | }; |
14 | ||
f9eb26a4 | 15 | apbdma: dma { |
8051b75a SW |
16 | compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma"; |
17 | reg = <0x6000a000 0x1400>; | |
95decf84 SW |
18 | interrupts = <0 104 0x04 |
19 | 0 105 0x04 | |
20 | 0 106 0x04 | |
21 | 0 107 0x04 | |
22 | 0 108 0x04 | |
23 | 0 109 0x04 | |
24 | 0 110 0x04 | |
25 | 0 111 0x04 | |
26 | 0 112 0x04 | |
27 | 0 113 0x04 | |
28 | 0 114 0x04 | |
29 | 0 115 0x04 | |
30 | 0 116 0x04 | |
31 | 0 117 0x04 | |
32 | 0 118 0x04 | |
33 | 0 119 0x04 | |
34 | 0 128 0x04 | |
35 | 0 129 0x04 | |
36 | 0 130 0x04 | |
37 | 0 131 0x04 | |
38 | 0 132 0x04 | |
39 | 0 133 0x04 | |
40 | 0 134 0x04 | |
41 | 0 135 0x04 | |
42 | 0 136 0x04 | |
43 | 0 137 0x04 | |
44 | 0 138 0x04 | |
45 | 0 139 0x04 | |
46 | 0 140 0x04 | |
47 | 0 141 0x04 | |
48 | 0 142 0x04 | |
49 | 0 143 0x04>; | |
8051b75a SW |
50 | }; |
51 | ||
c04abb3a SW |
52 | ahb: ahb { |
53 | compatible = "nvidia,tegra30-ahb"; | |
54 | reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */ | |
c3e00a0e PDS |
55 | }; |
56 | ||
f9eb26a4 | 57 | gpio: gpio { |
c3e00a0e | 58 | compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio"; |
95decf84 SW |
59 | reg = <0x6000d000 0x1000>; |
60 | interrupts = <0 32 0x04 | |
61 | 0 33 0x04 | |
62 | 0 34 0x04 | |
63 | 0 35 0x04 | |
64 | 0 55 0x04 | |
65 | 0 87 0x04 | |
66 | 0 89 0x04 | |
67 | 0 125 0x04>; | |
c3e00a0e PDS |
68 | #gpio-cells = <2>; |
69 | gpio-controller; | |
6f74dc9b SW |
70 | #interrupt-cells = <2>; |
71 | interrupt-controller; | |
c3e00a0e PDS |
72 | }; |
73 | ||
c04abb3a SW |
74 | pinmux: pinmux { |
75 | compatible = "nvidia,tegra30-pinmux"; | |
76 | reg = <0x70000868 0xd0 /* Pad control registers */ | |
77 | 0x70003000 0x3e0>; /* Mux registers */ | |
78 | }; | |
79 | ||
c3e00a0e PDS |
80 | serial@70006000 { |
81 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | |
82 | reg = <0x70006000 0x40>; | |
83 | reg-shift = <2>; | |
95decf84 | 84 | interrupts = <0 36 0x04>; |
223ef78d | 85 | status = "disabled"; |
c3e00a0e PDS |
86 | }; |
87 | ||
88 | serial@70006040 { | |
89 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | |
90 | reg = <0x70006040 0x40>; | |
91 | reg-shift = <2>; | |
95decf84 | 92 | interrupts = <0 37 0x04>; |
223ef78d | 93 | status = "disabled"; |
c3e00a0e PDS |
94 | }; |
95 | ||
96 | serial@70006200 { | |
97 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | |
98 | reg = <0x70006200 0x100>; | |
99 | reg-shift = <2>; | |
95decf84 | 100 | interrupts = <0 46 0x04>; |
223ef78d | 101 | status = "disabled"; |
c3e00a0e PDS |
102 | }; |
103 | ||
104 | serial@70006300 { | |
105 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | |
106 | reg = <0x70006300 0x100>; | |
107 | reg-shift = <2>; | |
95decf84 | 108 | interrupts = <0 90 0x04>; |
223ef78d | 109 | status = "disabled"; |
c3e00a0e PDS |
110 | }; |
111 | ||
112 | serial@70006400 { | |
113 | compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart"; | |
114 | reg = <0x70006400 0x100>; | |
115 | reg-shift = <2>; | |
95decf84 | 116 | interrupts = <0 91 0x04>; |
223ef78d | 117 | status = "disabled"; |
c3e00a0e PDS |
118 | }; |
119 | ||
c04abb3a | 120 | i2c@7000c000 { |
c04abb3a SW |
121 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
122 | reg = <0x7000c000 0x100>; | |
123 | interrupts = <0 38 0x04>; | |
2eaab06e SW |
124 | #address-cells = <1>; |
125 | #size-cells = <0>; | |
223ef78d | 126 | status = "disabled"; |
c3e00a0e PDS |
127 | }; |
128 | ||
c04abb3a | 129 | i2c@7000c400 { |
c04abb3a SW |
130 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
131 | reg = <0x7000c400 0x100>; | |
132 | interrupts = <0 84 0x04>; | |
2eaab06e SW |
133 | #address-cells = <1>; |
134 | #size-cells = <0>; | |
223ef78d | 135 | status = "disabled"; |
c3e00a0e PDS |
136 | }; |
137 | ||
c04abb3a | 138 | i2c@7000c500 { |
c04abb3a SW |
139 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
140 | reg = <0x7000c500 0x100>; | |
141 | interrupts = <0 92 0x04>; | |
2eaab06e SW |
142 | #address-cells = <1>; |
143 | #size-cells = <0>; | |
223ef78d | 144 | status = "disabled"; |
c3e00a0e PDS |
145 | }; |
146 | ||
c04abb3a | 147 | i2c@7000c700 { |
c04abb3a SW |
148 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
149 | reg = <0x7000c700 0x100>; | |
150 | interrupts = <0 120 0x04>; | |
2eaab06e SW |
151 | #address-cells = <1>; |
152 | #size-cells = <0>; | |
223ef78d | 153 | status = "disabled"; |
c3e00a0e PDS |
154 | }; |
155 | ||
c04abb3a | 156 | i2c@7000d000 { |
c04abb3a SW |
157 | compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c"; |
158 | reg = <0x7000d000 0x100>; | |
159 | interrupts = <0 53 0x04>; | |
2eaab06e SW |
160 | #address-cells = <1>; |
161 | #size-cells = <0>; | |
223ef78d | 162 | status = "disabled"; |
c04abb3a SW |
163 | }; |
164 | ||
165 | pmc { | |
166 | compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc"; | |
167 | reg = <0x7000e400 0x400>; | |
168 | }; | |
169 | ||
a9140aa5 | 170 | memory-controller { |
c04abb3a SW |
171 | compatible = "nvidia,tegra30-mc"; |
172 | reg = <0x7000f000 0x010 | |
173 | 0x7000f03c 0x1b4 | |
174 | 0x7000f200 0x028 | |
175 | 0x7000f284 0x17c>; | |
176 | interrupts = <0 77 0x04>; | |
177 | }; | |
178 | ||
179 | smmu { | |
180 | compatible = "nvidia,tegra30-smmu"; | |
181 | reg = <0x7000f010 0x02c | |
182 | 0x7000f1f0 0x010 | |
183 | 0x7000f228 0x05c>; | |
184 | nvidia,#asids = <4>; /* # of ASIDs */ | |
185 | dma-window = <0 0x40000000>; /* IOVA start & length */ | |
186 | nvidia,ahb = <&ahb>; | |
c3e00a0e | 187 | }; |
9ee6a5c4 SW |
188 | |
189 | ahub { | |
190 | compatible = "nvidia,tegra30-ahub"; | |
5ff48887 SW |
191 | reg = <0x70080000 0x200 |
192 | 0x70080200 0x100>; | |
95decf84 | 193 | interrupts = <0 103 0x04>; |
9ee6a5c4 SW |
194 | nvidia,dma-request-selector = <&apbdma 1>; |
195 | ||
196 | ranges; | |
197 | #address-cells = <1>; | |
198 | #size-cells = <1>; | |
199 | ||
200 | tegra_i2s0: i2s@70080300 { | |
201 | compatible = "nvidia,tegra30-i2s"; | |
202 | reg = <0x70080300 0x100>; | |
203 | nvidia,ahub-cif-ids = <4 4>; | |
223ef78d | 204 | status = "disabled"; |
9ee6a5c4 SW |
205 | }; |
206 | ||
207 | tegra_i2s1: i2s@70080400 { | |
208 | compatible = "nvidia,tegra30-i2s"; | |
209 | reg = <0x70080400 0x100>; | |
210 | nvidia,ahub-cif-ids = <5 5>; | |
223ef78d | 211 | status = "disabled"; |
9ee6a5c4 SW |
212 | }; |
213 | ||
214 | tegra_i2s2: i2s@70080500 { | |
215 | compatible = "nvidia,tegra30-i2s"; | |
216 | reg = <0x70080500 0x100>; | |
217 | nvidia,ahub-cif-ids = <6 6>; | |
223ef78d | 218 | status = "disabled"; |
9ee6a5c4 SW |
219 | }; |
220 | ||
221 | tegra_i2s3: i2s@70080600 { | |
222 | compatible = "nvidia,tegra30-i2s"; | |
223 | reg = <0x70080600 0x100>; | |
224 | nvidia,ahub-cif-ids = <7 7>; | |
223ef78d | 225 | status = "disabled"; |
9ee6a5c4 SW |
226 | }; |
227 | ||
228 | tegra_i2s4: i2s@70080700 { | |
229 | compatible = "nvidia,tegra30-i2s"; | |
230 | reg = <0x70080700 0x100>; | |
231 | nvidia,ahub-cif-ids = <8 8>; | |
223ef78d | 232 | status = "disabled"; |
9ee6a5c4 SW |
233 | }; |
234 | }; | |
7868a9bc | 235 | |
c04abb3a SW |
236 | sdhci@78000000 { |
237 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
238 | reg = <0x78000000 0x200>; | |
239 | interrupts = <0 14 0x04>; | |
223ef78d | 240 | status = "disabled"; |
7868a9bc | 241 | }; |
ecf43742 | 242 | |
c04abb3a SW |
243 | sdhci@78000200 { |
244 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
245 | reg = <0x78000200 0x200>; | |
246 | interrupts = <0 15 0x04>; | |
223ef78d | 247 | status = "disabled"; |
ecf43742 | 248 | }; |
54174a33 | 249 | |
c04abb3a SW |
250 | sdhci@78000400 { |
251 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
252 | reg = <0x78000400 0x200>; | |
253 | interrupts = <0 19 0x04>; | |
223ef78d | 254 | status = "disabled"; |
c04abb3a SW |
255 | }; |
256 | ||
257 | sdhci@78000600 { | |
258 | compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci"; | |
259 | reg = <0x78000600 0x200>; | |
260 | interrupts = <0 31 0x04>; | |
223ef78d | 261 | status = "disabled"; |
c04abb3a SW |
262 | }; |
263 | ||
264 | pmu { | |
265 | compatible = "arm,cortex-a9-pmu"; | |
266 | interrupts = <0 144 0x04 | |
267 | 0 145 0x04 | |
268 | 0 146 0x04 | |
269 | 0 147 0x04>; | |
54174a33 | 270 | }; |
c3e00a0e | 271 | }; |