[deliverable/linux.git] / arch / arm / boot / dts / tegra30.dtsi

#include <dt-bindings/gpio/tegra-gpio.h>

#include "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra30";
	interrupt-parent = <&intc>;

	aliases {
		serial0 = &uarta;
		serial1 = &uartb;
		serial2 = &uartc;
		serial3 = &uartd;
		serial4 = &uarte;
	};

	host1x {
		compatible = "nvidia,tegra30-host1x", "simple-bus";
		reg = <0x50000000 0x00024000>;
		interrupts = <0 65 0x04   /* mpcore syncpt */
			      0 67 0x04>; /* mpcore general */
		clocks = <&tegra_car 28>;

		#address-cells = <1>;
		#size-cells = <1>;

		ranges = <0x54000000 0x54000000 0x04000000>;

		mpe {
			compatible = "nvidia,tegra30-mpe";
			reg = <0x54040000 0x00040000>;
			interrupts = <0 68 0x04>;
			clocks = <&tegra_car 60>;
		};

		vi {
			compatible = "nvidia,tegra30-vi";
			reg = <0x54080000 0x00040000>;
			interrupts = <0 69 0x04>;
			clocks = <&tegra_car 164>;
		};

		epp {
			compatible = "nvidia,tegra30-epp";
			reg = <0x540c0000 0x00040000>;
			interrupts = <0 70 0x04>;
			clocks = <&tegra_car 19>;
		};

		isp {
			compatible = "nvidia,tegra30-isp";
			reg = <0x54100000 0x00040000>;
			interrupts = <0 71 0x04>;
			clocks = <&tegra_car 23>;
		};

		gr2d {
			compatible = "nvidia,tegra30-gr2d";
			reg = <0x54140000 0x00040000>;
			interrupts = <0 72 0x04>;
			clocks = <&tegra_car 21>;
		};

		gr3d {
			compatible = "nvidia,tegra30-gr3d";
			reg = <0x54180000 0x00040000>;
			clocks = <&tegra_car 24 &tegra_car 98>;
			clock-names = "3d", "3d2";
		};

		dc@54200000 {
			compatible = "nvidia,tegra30-dc";
			reg = <0x54200000 0x00040000>;
			interrupts = <0 73 0x04>;
			clocks = <&tegra_car 27>, <&tegra_car 179>;
			clock-names = "disp1", "parent";

			rgb {
				status = "disabled";
			};
		};

		dc@54240000 {
			compatible = "nvidia,tegra30-dc";
			reg = <0x54240000 0x00040000>;
			interrupts = <0 74 0x04>;
			clocks = <&tegra_car 26>, <&tegra_car 179>;
			clock-names = "disp2", "parent";

			rgb {
				status = "disabled";
			};
		};

		hdmi {
			compatible = "nvidia,tegra30-hdmi";
			reg = <0x54280000 0x00040000>;
			interrupts = <0 75 0x04>;
			clocks = <&tegra_car 51>, <&tegra_car 189>;
			clock-names = "hdmi", "parent";
			status = "disabled";
		};

		tvo {
			compatible = "nvidia,tegra30-tvo";
			reg = <0x542c0000 0x00040000>;
			interrupts = <0 76 0x04>;
			clocks = <&tegra_car 169>;
			status = "disabled";
		};

		dsi {
			compatible = "nvidia,tegra30-dsi";
			reg = <0x54300000 0x00040000>;
			clocks = <&tegra_car 48>;
			status = "disabled";
		};
	};

	timer@50004600 {
		compatible = "arm,cortex-a9-twd-timer";
		reg = <0x50040600 0x20>;
		interrupts = <1 13 0xf04>;
		clocks = <&tegra_car 214>;
	};

	intc: interrupt-controller {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	cache-controller {
		compatible = "arm,pl310-cache";
		reg = <0x50043000 0x1000>;
		arm,data-latency = <6 6 2>;
		arm,tag-latency = <5 5 2>;
		cache-unified;
		cache-level = <2>;
	};

	timer@60005000 {
		compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
		reg = <0x60005000 0x400>;
		interrupts = <0 0 0x04
			      0 1 0x04
			      0 41 0x04
			      0 42 0x04
			      0 121 0x04
			      0 122 0x04>;
		clocks = <&tegra_car 5>;
	};

	tegra_car: clock {
		compatible = "nvidia,tegra30-car";
		reg = <0x60006000 0x1000>;
		#clock-cells = <1>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1400>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04
			      0 128 0x04
			      0 129 0x04
			      0 130 0x04
			      0 131 0x04
			      0 132 0x04
			      0 133 0x04
			      0 134 0x04
			      0 135 0x04
			      0 136 0x04
			      0 137 0x04
			      0 138 0x04
			      0 139 0x04
			      0 140 0x04
			      0 141 0x04
			      0 142 0x04
			      0 143 0x04>;
		clocks = <&tegra_car 34>;
	};

	ahb: ahb {
		compatible = "nvidia,tegra30-ahb";
		reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio {
		compatible = "nvidia,tegra30-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <0 32 0x04
			      0 33 0x04
			      0 34 0x04
			      0 35 0x04
			      0 55 0x04
			      0 87 0x04
			      0 89 0x04
			      0 125 0x04>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra30-pinmux";
		reg = <0x70000868 0xd4    /* Pad control registers */
		       0x70003000 0x3e4>; /* Mux registers */
	};

	/*
	 * There are two serial driver i.e. 8250 based simple serial
	 * driver and APB DMA based serial driver for higher baudrate
	 * and performace. To enable the 8250 based driver, the compatible
	 * is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
	 * the APB DMA based serial driver, the comptible is
	 * "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
	 */
	uarta: serial@70006000 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <0 36 0x04>;
		nvidia,dma-request-selector = <&apbdma 8>;
		clocks = <&tegra_car 6>;
		status = "disabled";
	};

	uartb: serial@70006040 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <0 37 0x04>;
		nvidia,dma-request-selector = <&apbdma 9>;
		clocks = <&tegra_car 160>;
		status = "disabled";
	};

	uartc: serial@70006200 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <0 46 0x04>;
		nvidia,dma-request-selector = <&apbdma 10>;
		clocks = <&tegra_car 55>;
		status = "disabled";
	};

	uartd: serial@70006300 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <0 90 0x04>;
		nvidia,dma-request-selector = <&apbdma 19>;
		clocks = <&tegra_car 65>;
		status = "disabled";
	};

	uarte: serial@70006400 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <0 91 0x04>;
		nvidia,dma-request-selector = <&apbdma 20>;
		clocks = <&tegra_car 66>;
		status = "disabled";
	};

	pwm: pwm {
		compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
		clocks = <&tegra_car 17>;
		status = "disabled";
	};

	rtc {
		compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
		reg = <0x7000e000 0x100>;
		interrupts = <0 2 0x04>;
		clocks = <&tegra_car 4>;
	};

	i2c@7000c000 {
		compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <0 38 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 12>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <0 84 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 54>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <0 92 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 67>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000c700 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c700 0x100>;
		interrupts = <0 120 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 103>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000d000 0x100>;
		interrupts = <0 53 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 47>, <&tegra_car 182>;
		clock-names = "div-clk", "fast-clk";
		status = "disabled";
	};

	spi@7000d400 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d400 0x200>;
		interrupts = <0 59 0x04>;
		nvidia,dma-request-selector = <&apbdma 15>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 41>;
		status = "disabled";
	};

	spi@7000d600 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d600 0x200>;
		interrupts = <0 82 0x04>;
		nvidia,dma-request-selector = <&apbdma 16>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 44>;
		status = "disabled";
	};

	spi@7000d800 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000d800 0x200>;
		interrupts = <0 83 0x04>;
		nvidia,dma-request-selector = <&apbdma 17>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 46>;
		status = "disabled";
	};

	spi@7000da00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000da00 0x200>;
		interrupts = <0 93 0x04>;
		nvidia,dma-request-selector = <&apbdma 18>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 68>;
		status = "disabled";
	};

	spi@7000dc00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000dc00 0x200>;
		interrupts = <0 94 0x04>;
		nvidia,dma-request-selector = <&apbdma 27>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 104>;
		status = "disabled";
	};

	spi@7000de00 {
		compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
		reg = <0x7000de00 0x200>;
		interrupts = <0 79 0x04>;
		nvidia,dma-request-selector = <&apbdma 28>;
		#address-cells = <1>;
		#size-cells = <0>;
		clocks = <&tegra_car 105>;
		status = "disabled";
	};

	kbc {
		compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
		reg = <0x7000e200 0x100>;
		interrupts = <0 85 0x04>;
		clocks = <&tegra_car 36>;
		status = "disabled";
	};

	pmc {
		compatible = "nvidia,tegra30-pmc";
		reg = <0x7000e400 0x400>;
		clocks = <&tegra_car 218>, <&clk32k_in>;
		clock-names = "pclk", "clk32k_in";
	};

	memory-controller {
		compatible = "nvidia,tegra30-mc";
		reg = <0x7000f000 0x010
		       0x7000f03c 0x1b4
		       0x7000f200 0x028
		       0x7000f284 0x17c>;
		interrupts = <0 77 0x04>;
	};

	iommu {
		compatible = "nvidia,tegra30-smmu";
		reg = <0x7000f010 0x02c
		       0x7000f1f0 0x010
		       0x7000f228 0x05c>;
		nvidia,#asids = <4>;		/* # of ASIDs */
		dma-window = <0 0x40000000>;	/* IOVA start & length */
		nvidia,ahb = <&ahb>;
	};

	ahub {
		compatible = "nvidia,tegra30-ahub";
		reg = <0x70080000 0x200
		       0x70080200 0x100>;
		interrupts = <0 103 0x04>;
		nvidia,dma-request-selector = <&apbdma 1>;
		clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
			 <&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
			 <&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
			 <&tegra_car 110>, <&tegra_car 162>;
		clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
			      "i2s3", "i2s4", "dam0", "dam1", "dam2",
			      "spdif_in";
		ranges;
		#address-cells = <1>;
		#size-cells = <1>;

		tegra_i2s0: i2s@70080300 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080300 0x100>;
			nvidia,ahub-cif-ids = <4 4>;
			clocks = <&tegra_car 30>;
			status = "disabled";
		};

		tegra_i2s1: i2s@70080400 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080400 0x100>;
			nvidia,ahub-cif-ids = <5 5>;
			clocks = <&tegra_car 11>;
			status = "disabled";
		};

		tegra_i2s2: i2s@70080500 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080500 0x100>;
			nvidia,ahub-cif-ids = <6 6>;
			clocks = <&tegra_car 18>;
			status = "disabled";
		};

		tegra_i2s3: i2s@70080600 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080600 0x100>;
			nvidia,ahub-cif-ids = <7 7>;
			clocks = <&tegra_car 101>;
			status = "disabled";
		};

		tegra_i2s4: i2s@70080700 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080700 0x100>;
			nvidia,ahub-cif-ids = <8 8>;
			clocks = <&tegra_car 102>;
			status = "disabled";
		};
	};

	sdhci@78000000 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000000 0x200>;
		interrupts = <0 14 0x04>;
		clocks = <&tegra_car 14>;
		status = "disabled";
	};

	sdhci@78000200 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000200 0x200>;
		interrupts = <0 15 0x04>;
		clocks = <&tegra_car 9>;
		status = "disabled";
	};

	sdhci@78000400 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000400 0x200>;
		interrupts = <0 19 0x04>;
		clocks = <&tegra_car 69>;
		status = "disabled";
	};

	sdhci@78000600 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000600 0x200>;
		interrupts = <0 31 0x04>;
		clocks = <&tegra_car 15>;
		status = "disabled";
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
		};

		cpu@2 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <2>;
		};

		cpu@3 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <3>;
		};
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 144 0x04
			      0 145 0x04
			      0 146 0x04
			      0 147 0x04>;
	};
};
Commit	Line	Data
3325f1bc SW	1	#include <dt-bindings/gpio/tegra-gpio.h>
3325f1bc SW	2
1bd0bd49	3	#include "skeleton.dtsi"
c3e00a0e PDS	4
	5	/ {
	6	compatible = "nvidia,tegra30";
	7	interrupt-parent = <&intc>;
	8
b6551bb9 LD	9	aliases {
	10	serial0 = &uarta;
	11	serial1 = &uartb;
	12	serial2 = &uartc;
	13	serial3 = &uartd;
	14	serial4 = &uarte;
	15	};
	16
ed39097c TR	17	host1x {
	18	compatible = "nvidia,tegra30-host1x", "simple-bus";
	19	reg = <0x50000000 0x00024000>;
	20	interrupts = <0 65 0x04 /* mpcore syncpt */
	21	0 67 0x04>; /* mpcore general */
1cbc733d	22	clocks = <&tegra_car 28>;
ed39097c TR	23
	24	#address-cells = <1>;
	25	#size-cells = <1>;
	26
	27	ranges = <0x54000000 0x54000000 0x04000000>;
	28
	29	mpe {
	30	compatible = "nvidia,tegra30-mpe";
	31	reg = <0x54040000 0x00040000>;
	32	interrupts = <0 68 0x04>;
1cbc733d	33	clocks = <&tegra_car 60>;
ed39097c TR	34	};
	35
	36	vi {
	37	compatible = "nvidia,tegra30-vi";
	38	reg = <0x54080000 0x00040000>;
	39	interrupts = <0 69 0x04>;
1cbc733d	40	clocks = <&tegra_car 164>;
ed39097c TR	41	};
	42
	43	epp {
	44	compatible = "nvidia,tegra30-epp";
	45	reg = <0x540c0000 0x00040000>;
	46	interrupts = <0 70 0x04>;
1cbc733d	47	clocks = <&tegra_car 19>;
ed39097c TR	48	};
	49
	50	isp {
	51	compatible = "nvidia,tegra30-isp";
	52	reg = <0x54100000 0x00040000>;
	53	interrupts = <0 71 0x04>;
1cbc733d	54	clocks = <&tegra_car 23>;
ed39097c TR	55	};
	56
	57	gr2d {
	58	compatible = "nvidia,tegra30-gr2d";
	59	reg = <0x54140000 0x00040000>;
	60	interrupts = <0 72 0x04>;
1cbc733d	61	clocks = <&tegra_car 21>;
ed39097c TR	62	};
	63
	64	gr3d {
	65	compatible = "nvidia,tegra30-gr3d";
	66	reg = <0x54180000 0x00040000>;
1cbc733d PG	67	clocks = <&tegra_car 24 &tegra_car 98>;
1cbc733d PG	68	clock-names = "3d", "3d2";
ed39097c TR	69	};
	70
	71	dc@54200000 {
	72	compatible = "nvidia,tegra30-dc";
	73	reg = <0x54200000 0x00040000>;
	74	interrupts = <0 73 0x04>;
1cbc733d PG	75	clocks = <&tegra_car 27>, <&tegra_car 179>;
1cbc733d PG	76	clock-names = "disp1", "parent";
ed39097c TR	77
	78	rgb {
	79	status = "disabled";
	80	};
	81	};
	82
	83	dc@54240000 {
	84	compatible = "nvidia,tegra30-dc";
	85	reg = <0x54240000 0x00040000>;
	86	interrupts = <0 74 0x04>;
1cbc733d PG	87	clocks = <&tegra_car 26>, <&tegra_car 179>;
1cbc733d PG	88	clock-names = "disp2", "parent";
ed39097c TR	89
	90	rgb {
	91	status = "disabled";
	92	};
	93	};
	94
	95	hdmi {
	96	compatible = "nvidia,tegra30-hdmi";
	97	reg = <0x54280000 0x00040000>;
	98	interrupts = <0 75 0x04>;
1cbc733d PG	99	clocks = <&tegra_car 51>, <&tegra_car 189>;
1cbc733d PG	100	clock-names = "hdmi", "parent";
ed39097c TR	101	status = "disabled";
	102	};
	103
	104	tvo {
	105	compatible = "nvidia,tegra30-tvo";
	106	reg = <0x542c0000 0x00040000>;
	107	interrupts = <0 76 0x04>;
1cbc733d	108	clocks = <&tegra_car 169>;
ed39097c TR	109	status = "disabled";
	110	};
	111
	112	dsi {
	113	compatible = "nvidia,tegra30-dsi";
	114	reg = <0x54300000 0x00040000>;
1cbc733d	115	clocks = <&tegra_car 48>;
ed39097c TR	116	status = "disabled";
	117	};
	118	};
	119
73368ba0 SW	120	timer@50004600 {
	121	compatible = "arm,cortex-a9-twd-timer";
	122	reg = <0x50040600 0x20>;
	123	interrupts = <1 13 0xf04>;
ed3ced37	124	clocks = <&tegra_car 214>;
73368ba0 SW	125	};
73368ba0 SW	126
f9eb26a4	127	intc: interrupt-controller {
c3e00a0e	128	compatible = "arm,cortex-a9-gic";
5ff48887 SW	129	reg = <0x50041000 0x1000
5ff48887 SW	130	0x50040100 0x0100>;
2eaab06e SW	131	interrupt-controller;
2eaab06e SW	132	#interrupt-cells = <3>;
c3e00a0e PDS	133	};
c3e00a0e PDS	134
bb2c1de9 SW	135	cache-controller {
	136	compatible = "arm,pl310-cache";
	137	reg = <0x50043000 0x1000>;
	138	arm,data-latency = <6 6 2>;
	139	arm,tag-latency = <5 5 2>;
	140	cache-unified;
	141	cache-level = <2>;
	142	};
	143
2f2b7fb2 SW	144	timer@60005000 {
	145	compatible = "nvidia,tegra30-timer", "nvidia,tegra20-timer";
	146	reg = <0x60005000 0x400>;
	147	interrupts = <0 0 0x04
	148	0 1 0x04
	149	0 41 0x04
	150	0 42 0x04
	151	0 121 0x04
	152	0 122 0x04>;
6f88fb8a	153	clocks = <&tegra_car 5>;
2f2b7fb2 SW	154	};
2f2b7fb2 SW	155
95985667 PG	156	tegra_car: clock {
	157	compatible = "nvidia,tegra30-car";
	158	reg = <0x60006000 0x1000>;
	159	#clock-cells = <1>;
	160	};
	161
f9eb26a4	162	apbdma: dma {
8051b75a SW	163	compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
8051b75a SW	164	reg = <0x6000a000 0x1400>;
95decf84 SW	165	interrupts = <0 104 0x04
	166	0 105 0x04
	167	0 106 0x04
	168	0 107 0x04
	169	0 108 0x04
	170	0 109 0x04
	171	0 110 0x04
	172	0 111 0x04
	173	0 112 0x04
	174	0 113 0x04
	175	0 114 0x04
	176	0 115 0x04
	177	0 116 0x04
	178	0 117 0x04
	179	0 118 0x04
	180	0 119 0x04
	181	0 128 0x04
	182	0 129 0x04
	183	0 130 0x04
	184	0 131 0x04
	185	0 132 0x04
	186	0 133 0x04
	187	0 134 0x04
	188	0 135 0x04
	189	0 136 0x04
	190	0 137 0x04
	191	0 138 0x04
	192	0 139 0x04
	193	0 140 0x04
	194	0 141 0x04
	195	0 142 0x04
	196	0 143 0x04>;
1cbc733d	197	clocks = <&tegra_car 34>;
8051b75a SW	198	};
8051b75a SW	199
c04abb3a SW	200	ahb: ahb {
	201	compatible = "nvidia,tegra30-ahb";
	202	reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e PDS	203	};
c3e00a0e PDS	204
f9eb26a4	205	gpio: gpio {
35f210ec	206	compatible = "nvidia,tegra30-gpio";
95decf84 SW	207	reg = <0x6000d000 0x1000>;
	208	interrupts = <0 32 0x04
	209	0 33 0x04
	210	0 34 0x04
	211	0 35 0x04
	212	0 55 0x04
	213	0 87 0x04
	214	0 89 0x04
	215	0 125 0x04>;
c3e00a0e PDS	216	#gpio-cells = <2>;
c3e00a0e PDS	217	gpio-controller;
6f74dc9b SW	218	#interrupt-cells = <2>;
6f74dc9b SW	219	interrupt-controller;
c3e00a0e PDS	220	};
c3e00a0e PDS	221
c04abb3a SW	222	pinmux: pinmux {
c04abb3a SW	223	compatible = "nvidia,tegra30-pinmux";
322337b8 PR	224	reg = <0x70000868 0xd4 /* Pad control registers */
322337b8 PR	225	0x70003000 0x3e4>; /* Mux registers */
c04abb3a SW	226	};
c04abb3a SW	227
b6551bb9 LD	228	/*
	229	* There are two serial driver i.e. 8250 based simple serial
	230	* driver and APB DMA based serial driver for higher baudrate
	231	* and performace. To enable the 8250 based driver, the compatible
	232	* is "nvidia,tegra30-uart", "nvidia,tegra20-uart" and to enable
	233	* the APB DMA based serial driver, the comptible is
	234	* "nvidia,tegra30-hsuart", "nvidia,tegra20-hsuart".
	235	*/
	236	uarta: serial@70006000 {
c3e00a0e PDS	237	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	238	reg = <0x70006000 0x40>;
	239	reg-shift = <2>;
95decf84	240	interrupts = <0 36 0x04>;
b6551bb9	241	nvidia,dma-request-selector = <&apbdma 8>;
1cbc733d	242	clocks = <&tegra_car 6>;
223ef78d	243	status = "disabled";
c3e00a0e PDS	244	};
c3e00a0e PDS	245
b6551bb9	246	uartb: serial@70006040 {
c3e00a0e PDS	247	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	248	reg = <0x70006040 0x40>;
	249	reg-shift = <2>;
95decf84	250	interrupts = <0 37 0x04>;
b6551bb9	251	nvidia,dma-request-selector = <&apbdma 9>;
1cbc733d	252	clocks = <&tegra_car 160>;
223ef78d	253	status = "disabled";
c3e00a0e PDS	254	};
c3e00a0e PDS	255
b6551bb9	256	uartc: serial@70006200 {
c3e00a0e PDS	257	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	258	reg = <0x70006200 0x100>;
	259	reg-shift = <2>;
95decf84	260	interrupts = <0 46 0x04>;
b6551bb9	261	nvidia,dma-request-selector = <&apbdma 10>;
1cbc733d	262	clocks = <&tegra_car 55>;
223ef78d	263	status = "disabled";
c3e00a0e PDS	264	};
c3e00a0e PDS	265
b6551bb9	266	uartd: serial@70006300 {
c3e00a0e PDS	267	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	268	reg = <0x70006300 0x100>;
	269	reg-shift = <2>;
95decf84	270	interrupts = <0 90 0x04>;
b6551bb9	271	nvidia,dma-request-selector = <&apbdma 19>;
1cbc733d	272	clocks = <&tegra_car 65>;
223ef78d	273	status = "disabled";
c3e00a0e PDS	274	};
c3e00a0e PDS	275
b6551bb9	276	uarte: serial@70006400 {
c3e00a0e PDS	277	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	278	reg = <0x70006400 0x100>;
	279	reg-shift = <2>;
95decf84	280	interrupts = <0 91 0x04>;
b6551bb9	281	nvidia,dma-request-selector = <&apbdma 20>;
1cbc733d	282	clocks = <&tegra_car 66>;
223ef78d	283	status = "disabled";
c3e00a0e PDS	284	};
c3e00a0e PDS	285
2b8b15da	286	pwm: pwm {
140fd977 TR	287	compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
	288	reg = <0x7000a000 0x100>;
	289	#pwm-cells = <2>;
1cbc733d	290	clocks = <&tegra_car 17>;
b69cd984	291	status = "disabled";
140fd977 TR	292	};
140fd977 TR	293
380e04ac SW	294	rtc {
	295	compatible = "nvidia,tegra30-rtc", "nvidia,tegra20-rtc";
	296	reg = <0x7000e000 0x100>;
	297	interrupts = <0 2 0x04>;
6f88fb8a	298	clocks = <&tegra_car 4>;
380e04ac SW	299	};
380e04ac SW	300
c04abb3a	301	i2c@7000c000 {
c04abb3a SW	302	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	303	reg = <0x7000c000 0x100>;
	304	interrupts = <0 38 0x04>;
2eaab06e SW	305	#address-cells = <1>;
2eaab06e SW	306	#size-cells = <0>;
1cbc733d PG	307	clocks = <&tegra_car 12>, <&tegra_car 182>;
1cbc733d PG	308	clock-names = "div-clk", "fast-clk";
223ef78d	309	status = "disabled";
c3e00a0e PDS	310	};
c3e00a0e PDS	311
c04abb3a	312	i2c@7000c400 {
c04abb3a SW	313	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	314	reg = <0x7000c400 0x100>;
	315	interrupts = <0 84 0x04>;
2eaab06e SW	316	#address-cells = <1>;
2eaab06e SW	317	#size-cells = <0>;
1cbc733d PG	318	clocks = <&tegra_car 54>, <&tegra_car 182>;
1cbc733d PG	319	clock-names = "div-clk", "fast-clk";
223ef78d	320	status = "disabled";
c3e00a0e PDS	321	};
c3e00a0e PDS	322
c04abb3a	323	i2c@7000c500 {
c04abb3a SW	324	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	325	reg = <0x7000c500 0x100>;
	326	interrupts = <0 92 0x04>;
2eaab06e SW	327	#address-cells = <1>;
2eaab06e SW	328	#size-cells = <0>;
1cbc733d PG	329	clocks = <&tegra_car 67>, <&tegra_car 182>;
1cbc733d PG	330	clock-names = "div-clk", "fast-clk";
223ef78d	331	status = "disabled";
c3e00a0e PDS	332	};
c3e00a0e PDS	333
c04abb3a	334	i2c@7000c700 {
c04abb3a SW	335	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	336	reg = <0x7000c700 0x100>;
	337	interrupts = <0 120 0x04>;
2eaab06e SW	338	#address-cells = <1>;
2eaab06e SW	339	#size-cells = <0>;
1cbc733d PG	340	clocks = <&tegra_car 103>, <&tegra_car 182>;
1cbc733d PG	341	clock-names = "div-clk", "fast-clk";
223ef78d	342	status = "disabled";
c3e00a0e PDS	343	};
c3e00a0e PDS	344
c04abb3a	345	i2c@7000d000 {
c04abb3a SW	346	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	347	reg = <0x7000d000 0x100>;
	348	interrupts = <0 53 0x04>;
2eaab06e SW	349	#address-cells = <1>;
2eaab06e SW	350	#size-cells = <0>;
1cbc733d PG	351	clocks = <&tegra_car 47>, <&tegra_car 182>;
1cbc733d PG	352	clock-names = "div-clk", "fast-clk";
223ef78d	353	status = "disabled";
c04abb3a SW	354	};
c04abb3a SW	355
a86b0db3 LD	356	spi@7000d400 {
	357	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	358	reg = <0x7000d400 0x200>;
	359	interrupts = <0 59 0x04>;
	360	nvidia,dma-request-selector = <&apbdma 15>;
	361	#address-cells = <1>;
	362	#size-cells = <0>;
1cbc733d	363	clocks = <&tegra_car 41>;
a86b0db3 LD	364	status = "disabled";
	365	};
	366
	367	spi@7000d600 {
	368	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	369	reg = <0x7000d600 0x200>;
	370	interrupts = <0 82 0x04>;
	371	nvidia,dma-request-selector = <&apbdma 16>;
	372	#address-cells = <1>;
	373	#size-cells = <0>;
1cbc733d	374	clocks = <&tegra_car 44>;
a86b0db3 LD	375	status = "disabled";
	376	};
	377
	378	spi@7000d800 {
	379	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
57471c8d	380	reg = <0x7000d800 0x200>;
a86b0db3 LD	381	interrupts = <0 83 0x04>;
	382	nvidia,dma-request-selector = <&apbdma 17>;
	383	#address-cells = <1>;
	384	#size-cells = <0>;
1cbc733d	385	clocks = <&tegra_car 46>;
a86b0db3 LD	386	status = "disabled";
	387	};
	388
	389	spi@7000da00 {
	390	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	391	reg = <0x7000da00 0x200>;
	392	interrupts = <0 93 0x04>;
	393	nvidia,dma-request-selector = <&apbdma 18>;
	394	#address-cells = <1>;
	395	#size-cells = <0>;
1cbc733d	396	clocks = <&tegra_car 68>;
a86b0db3 LD	397	status = "disabled";
	398	};
	399
	400	spi@7000dc00 {
	401	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	402	reg = <0x7000dc00 0x200>;
	403	interrupts = <0 94 0x04>;
	404	nvidia,dma-request-selector = <&apbdma 27>;
	405	#address-cells = <1>;
	406	#size-cells = <0>;
1cbc733d	407	clocks = <&tegra_car 104>;
a86b0db3 LD	408	status = "disabled";
	409	};
	410
	411	spi@7000de00 {
	412	compatible = "nvidia,tegra30-slink", "nvidia,tegra20-slink";
	413	reg = <0x7000de00 0x200>;
	414	interrupts = <0 79 0x04>;
	415	nvidia,dma-request-selector = <&apbdma 28>;
	416	#address-cells = <1>;
	417	#size-cells = <0>;
1cbc733d	418	clocks = <&tegra_car 105>;
a86b0db3 LD	419	status = "disabled";
	420	};
	421
699ed4b9 LD	422	kbc {
	423	compatible = "nvidia,tegra30-kbc", "nvidia,tegra20-kbc";
	424	reg = <0x7000e200 0x100>;
	425	interrupts = <0 85 0x04>;
	426	clocks = <&tegra_car 36>;
	427	status = "disabled";
	428	};
	429
c04abb3a	430	pmc {
2b84e53b	431	compatible = "nvidia,tegra30-pmc";
c04abb3a	432	reg = <0x7000e400 0x400>;
7021d122 JL	433	clocks = <&tegra_car 218>, <&clk32k_in>;
7021d122 JL	434	clock-names = "pclk", "clk32k_in";
c04abb3a SW	435	};
c04abb3a SW	436
a9140aa5	437	memory-controller {
c04abb3a SW	438	compatible = "nvidia,tegra30-mc";
	439	reg = <0x7000f000 0x010
	440	0x7000f03c 0x1b4
	441	0x7000f200 0x028
	442	0x7000f284 0x17c>;
	443	interrupts = <0 77 0x04>;
	444	};
	445
3fbf07d8	446	iommu {
c04abb3a SW	447	compatible = "nvidia,tegra30-smmu";
	448	reg = <0x7000f010 0x02c
	449	0x7000f1f0 0x010
	450	0x7000f228 0x05c>;
	451	nvidia,#asids = <4>; /* # of ASIDs */
	452	dma-window = <0 0x40000000>; /* IOVA start & length */
	453	nvidia,ahb = <&ahb>;
c3e00a0e	454	};
9ee6a5c4 SW	455
	456	ahub {
	457	compatible = "nvidia,tegra30-ahub";
5ff48887 SW	458	reg = <0x70080000 0x200
5ff48887 SW	459	0x70080200 0x100>;
95decf84	460	interrupts = <0 103 0x04>;
9ee6a5c4	461	nvidia,dma-request-selector = <&apbdma 1>;
1cbc733d PG	462	clocks = <&tegra_car 106>, <&tegra_car 107>, <&tegra_car 30>,
	463	<&tegra_car 11>, <&tegra_car 18>, <&tegra_car 101>,
	464	<&tegra_car 102>, <&tegra_car 108>, <&tegra_car 109>,
	465	<&tegra_car 110>, <&tegra_car 162>;
	466	clock-names = "d_audio", "apbif", "i2s0", "i2s1", "i2s2",
	467	"i2s3", "i2s4", "dam0", "dam1", "dam2",
	468	"spdif_in";
9ee6a5c4 SW	469	ranges;
	470	#address-cells = <1>;
	471	#size-cells = <1>;
	472
	473	tegra_i2s0: i2s@70080300 {
	474	compatible = "nvidia,tegra30-i2s";
	475	reg = <0x70080300 0x100>;
	476	nvidia,ahub-cif-ids = <4 4>;
1cbc733d	477	clocks = <&tegra_car 30>;
223ef78d	478	status = "disabled";
9ee6a5c4 SW	479	};
	480
	481	tegra_i2s1: i2s@70080400 {
	482	compatible = "nvidia,tegra30-i2s";
	483	reg = <0x70080400 0x100>;
	484	nvidia,ahub-cif-ids = <5 5>;
1cbc733d	485	clocks = <&tegra_car 11>;
223ef78d	486	status = "disabled";
9ee6a5c4 SW	487	};
	488
	489	tegra_i2s2: i2s@70080500 {
	490	compatible = "nvidia,tegra30-i2s";
	491	reg = <0x70080500 0x100>;
	492	nvidia,ahub-cif-ids = <6 6>;
1cbc733d	493	clocks = <&tegra_car 18>;
223ef78d	494	status = "disabled";
9ee6a5c4 SW	495	};
	496
	497	tegra_i2s3: i2s@70080600 {
	498	compatible = "nvidia,tegra30-i2s";
	499	reg = <0x70080600 0x100>;
	500	nvidia,ahub-cif-ids = <7 7>;
1cbc733d	501	clocks = <&tegra_car 101>;
223ef78d	502	status = "disabled";
9ee6a5c4 SW	503	};
	504
	505	tegra_i2s4: i2s@70080700 {
	506	compatible = "nvidia,tegra30-i2s";
	507	reg = <0x70080700 0x100>;
	508	nvidia,ahub-cif-ids = <8 8>;
1cbc733d	509	clocks = <&tegra_car 102>;
223ef78d	510	status = "disabled";
9ee6a5c4 SW	511	};
9ee6a5c4 SW	512	};
7868a9bc	513
c04abb3a SW	514	sdhci@78000000 {
	515	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	516	reg = <0x78000000 0x200>;
	517	interrupts = <0 14 0x04>;
1cbc733d	518	clocks = <&tegra_car 14>;
223ef78d	519	status = "disabled";
7868a9bc	520	};
ecf43742	521
c04abb3a SW	522	sdhci@78000200 {
	523	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	524	reg = <0x78000200 0x200>;
	525	interrupts = <0 15 0x04>;
1cbc733d	526	clocks = <&tegra_car 9>;
223ef78d	527	status = "disabled";
ecf43742	528	};
54174a33	529
c04abb3a SW	530	sdhci@78000400 {
	531	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	532	reg = <0x78000400 0x200>;
	533	interrupts = <0 19 0x04>;
1cbc733d	534	clocks = <&tegra_car 69>;
223ef78d	535	status = "disabled";
c04abb3a SW	536	};
	537
	538	sdhci@78000600 {
	539	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	540	reg = <0x78000600 0x200>;
	541	interrupts = <0 31 0x04>;
1cbc733d	542	clocks = <&tegra_car 15>;
223ef78d	543	status = "disabled";
c04abb3a SW	544	};
c04abb3a SW	545
7d19a34a HD	546	cpus {
	547	#address-cells = <1>;
	548	#size-cells = <0>;
	549
	550	cpu@0 {
	551	device_type = "cpu";
	552	compatible = "arm,cortex-a9";
	553	reg = <0>;
	554	};
	555
	556	cpu@1 {
	557	device_type = "cpu";
	558	compatible = "arm,cortex-a9";
	559	reg = <1>;
	560	};
	561
	562	cpu@2 {
	563	device_type = "cpu";
	564	compatible = "arm,cortex-a9";
	565	reg = <2>;
	566	};
	567
	568	cpu@3 {
	569	device_type = "cpu";
	570	compatible = "arm,cortex-a9";
	571	reg = <3>;
	572	};
	573	};
	574
c04abb3a SW	575	pmu {
	576	compatible = "arm,cortex-a9-pmu";
	577	interrupts = <0 144 0x04
	578	0 145 0x04
	579	0 146 0x04
	580	0 147 0x04>;
54174a33	581	};
c3e00a0e	582	};