[deliverable/linux.git] / arch / arm / boot / dts / tegra30.dtsi

/include/ "skeleton.dtsi"

/ {
	compatible = "nvidia,tegra30";
	interrupt-parent = <&intc>;

	intc: interrupt-controller {
		compatible = "arm,cortex-a9-gic";
		reg = <0x50041000 0x1000
		       0x50040100 0x0100>;
		interrupt-controller;
		#interrupt-cells = <3>;
	};

	apbdma: dma {
		compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
		reg = <0x6000a000 0x1400>;
		interrupts = <0 104 0x04
			      0 105 0x04
			      0 106 0x04
			      0 107 0x04
			      0 108 0x04
			      0 109 0x04
			      0 110 0x04
			      0 111 0x04
			      0 112 0x04
			      0 113 0x04
			      0 114 0x04
			      0 115 0x04
			      0 116 0x04
			      0 117 0x04
			      0 118 0x04
			      0 119 0x04
			      0 128 0x04
			      0 129 0x04
			      0 130 0x04
			      0 131 0x04
			      0 132 0x04
			      0 133 0x04
			      0 134 0x04
			      0 135 0x04
			      0 136 0x04
			      0 137 0x04
			      0 138 0x04
			      0 139 0x04
			      0 140 0x04
			      0 141 0x04
			      0 142 0x04
			      0 143 0x04>;
	};

	ahb: ahb {
		compatible = "nvidia,tegra30-ahb";
		reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
	};

	gpio: gpio {
		compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
		reg = <0x6000d000 0x1000>;
		interrupts = <0 32 0x04
			      0 33 0x04
			      0 34 0x04
			      0 35 0x04
			      0 55 0x04
			      0 87 0x04
			      0 89 0x04
			      0 125 0x04>;
		#gpio-cells = <2>;
		gpio-controller;
		#interrupt-cells = <2>;
		interrupt-controller;
	};

	pinmux: pinmux {
		compatible = "nvidia,tegra30-pinmux";
		reg = <0x70000868 0xd0    /* Pad control registers */
		       0x70003000 0x3e0>; /* Mux registers */
	};

	serial@70006000 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006000 0x40>;
		reg-shift = <2>;
		interrupts = <0 36 0x04>;
		status = "disabled";
	};

	serial@70006040 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006040 0x40>;
		reg-shift = <2>;
		interrupts = <0 37 0x04>;
		status = "disabled";
	};

	serial@70006200 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006200 0x100>;
		reg-shift = <2>;
		interrupts = <0 46 0x04>;
		status = "disabled";
	};

	serial@70006300 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006300 0x100>;
		reg-shift = <2>;
		interrupts = <0 90 0x04>;
		status = "disabled";
	};

	serial@70006400 {
		compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
		reg = <0x70006400 0x100>;
		reg-shift = <2>;
		interrupts = <0 91 0x04>;
		status = "disabled";
	};

	pwm: pwm {
		compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
		reg = <0x7000a000 0x100>;
		#pwm-cells = <2>;
	};

	i2c@7000c000 {
		compatible =  "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c000 0x100>;
		interrupts = <0 38 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c@7000c400 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c400 0x100>;
		interrupts = <0 84 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c@7000c500 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c500 0x100>;
		interrupts = <0 92 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c@7000c700 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000c700 0x100>;
		interrupts = <0 120 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	i2c@7000d000 {
		compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
		reg = <0x7000d000 0x100>;
		interrupts = <0 53 0x04>;
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";
	};

	pmc {
		compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
		reg = <0x7000e400 0x400>;
	};

	memory-controller {
		compatible = "nvidia,tegra30-mc";
		reg = <0x7000f000 0x010
		       0x7000f03c 0x1b4
		       0x7000f200 0x028
		       0x7000f284 0x17c>;
		interrupts = <0 77 0x04>;
	};

	smmu {
		compatible = "nvidia,tegra30-smmu";
		reg = <0x7000f010 0x02c
		       0x7000f1f0 0x010
		       0x7000f228 0x05c>;
		nvidia,#asids = <4>;		/* # of ASIDs */
		dma-window = <0 0x40000000>;	/* IOVA start & length */
		nvidia,ahb = <&ahb>;
	};

	ahub {
		compatible = "nvidia,tegra30-ahub";
		reg = <0x70080000 0x200
		       0x70080200 0x100>;
		interrupts = <0 103 0x04>;
		nvidia,dma-request-selector = <&apbdma 1>;

		ranges;
		#address-cells = <1>;
		#size-cells = <1>;

		tegra_i2s0: i2s@70080300 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080300 0x100>;
			nvidia,ahub-cif-ids = <4 4>;
			status = "disabled";
		};

		tegra_i2s1: i2s@70080400 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080400 0x100>;
			nvidia,ahub-cif-ids = <5 5>;
			status = "disabled";
		};

		tegra_i2s2: i2s@70080500 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080500 0x100>;
			nvidia,ahub-cif-ids = <6 6>;
			status = "disabled";
		};

		tegra_i2s3: i2s@70080600 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080600 0x100>;
			nvidia,ahub-cif-ids = <7 7>;
			status = "disabled";
		};

		tegra_i2s4: i2s@70080700 {
			compatible = "nvidia,tegra30-i2s";
			reg = <0x70080700 0x100>;
			nvidia,ahub-cif-ids = <8 8>;
			status = "disabled";
		};
	};

	sdhci@78000000 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000000 0x200>;
		interrupts = <0 14 0x04>;
		status = "disabled";
	};

	sdhci@78000200 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000200 0x200>;
		interrupts = <0 15 0x04>;
		status = "disabled";
	};

	sdhci@78000400 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000400 0x200>;
		interrupts = <0 19 0x04>;
		status = "disabled";
	};

	sdhci@78000600 {
		compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
		reg = <0x78000600 0x200>;
		interrupts = <0 31 0x04>;
		status = "disabled";
	};

	pmu {
		compatible = "arm,cortex-a9-pmu";
		interrupts = <0 144 0x04
			      0 145 0x04
			      0 146 0x04
			      0 147 0x04>;
	};
};
Commit	Line	Data
c3e00a0e PDS	1	/include/ "skeleton.dtsi"
	2
	3	/ {
	4	compatible = "nvidia,tegra30";
	5	interrupt-parent = <&intc>;
	6
f9eb26a4	7	intc: interrupt-controller {
c3e00a0e	8	compatible = "arm,cortex-a9-gic";
5ff48887 SW	9	reg = <0x50041000 0x1000
5ff48887 SW	10	0x50040100 0x0100>;
2eaab06e SW	11	interrupt-controller;
2eaab06e SW	12	#interrupt-cells = <3>;
c3e00a0e PDS	13	};
c3e00a0e PDS	14
f9eb26a4	15	apbdma: dma {
8051b75a SW	16	compatible = "nvidia,tegra30-apbdma", "nvidia,tegra20-apbdma";
8051b75a SW	17	reg = <0x6000a000 0x1400>;
95decf84 SW	18	interrupts = <0 104 0x04
	19	0 105 0x04
	20	0 106 0x04
	21	0 107 0x04
	22	0 108 0x04
	23	0 109 0x04
	24	0 110 0x04
	25	0 111 0x04
	26	0 112 0x04
	27	0 113 0x04
	28	0 114 0x04
	29	0 115 0x04
	30	0 116 0x04
	31	0 117 0x04
	32	0 118 0x04
	33	0 119 0x04
	34	0 128 0x04
	35	0 129 0x04
	36	0 130 0x04
	37	0 131 0x04
	38	0 132 0x04
	39	0 133 0x04
	40	0 134 0x04
	41	0 135 0x04
	42	0 136 0x04
	43	0 137 0x04
	44	0 138 0x04
	45	0 139 0x04
	46	0 140 0x04
	47	0 141 0x04
	48	0 142 0x04
	49	0 143 0x04>;
8051b75a SW	50	};
8051b75a SW	51
c04abb3a SW	52	ahb: ahb {
	53	compatible = "nvidia,tegra30-ahb";
	54	reg = <0x6000c004 0x14c>; /* AHB Arbitration + Gizmo Controller */
c3e00a0e PDS	55	};
c3e00a0e PDS	56
f9eb26a4	57	gpio: gpio {
c3e00a0e	58	compatible = "nvidia,tegra30-gpio", "nvidia,tegra20-gpio";
95decf84 SW	59	reg = <0x6000d000 0x1000>;
	60	interrupts = <0 32 0x04
	61	0 33 0x04
	62	0 34 0x04
	63	0 35 0x04
	64	0 55 0x04
	65	0 87 0x04
	66	0 89 0x04
	67	0 125 0x04>;
c3e00a0e PDS	68	#gpio-cells = <2>;
c3e00a0e PDS	69	gpio-controller;
6f74dc9b SW	70	#interrupt-cells = <2>;
6f74dc9b SW	71	interrupt-controller;
c3e00a0e PDS	72	};
c3e00a0e PDS	73
c04abb3a SW	74	pinmux: pinmux {
	75	compatible = "nvidia,tegra30-pinmux";
	76	reg = <0x70000868 0xd0 /* Pad control registers */
	77	0x70003000 0x3e0>; /* Mux registers */
	78	};
	79
c3e00a0e PDS	80	serial@70006000 {
	81	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	82	reg = <0x70006000 0x40>;
	83	reg-shift = <2>;
95decf84	84	interrupts = <0 36 0x04>;
223ef78d	85	status = "disabled";
c3e00a0e PDS	86	};
	87
	88	serial@70006040 {
	89	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	90	reg = <0x70006040 0x40>;
	91	reg-shift = <2>;
95decf84	92	interrupts = <0 37 0x04>;
223ef78d	93	status = "disabled";
c3e00a0e PDS	94	};
	95
	96	serial@70006200 {
	97	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	98	reg = <0x70006200 0x100>;
	99	reg-shift = <2>;
95decf84	100	interrupts = <0 46 0x04>;
223ef78d	101	status = "disabled";
c3e00a0e PDS	102	};
	103
	104	serial@70006300 {
	105	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	106	reg = <0x70006300 0x100>;
	107	reg-shift = <2>;
95decf84	108	interrupts = <0 90 0x04>;
223ef78d	109	status = "disabled";
c3e00a0e PDS	110	};
	111
	112	serial@70006400 {
	113	compatible = "nvidia,tegra30-uart", "nvidia,tegra20-uart";
	114	reg = <0x70006400 0x100>;
	115	reg-shift = <2>;
95decf84	116	interrupts = <0 91 0x04>;
223ef78d	117	status = "disabled";
c3e00a0e PDS	118	};
c3e00a0e PDS	119
2b8b15da	120	pwm: pwm {
140fd977 TR	121	compatible = "nvidia,tegra30-pwm", "nvidia,tegra20-pwm";
	122	reg = <0x7000a000 0x100>;
	123	#pwm-cells = <2>;
	124	};
	125
c04abb3a	126	i2c@7000c000 {
c04abb3a SW	127	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	128	reg = <0x7000c000 0x100>;
	129	interrupts = <0 38 0x04>;
2eaab06e SW	130	#address-cells = <1>;
2eaab06e SW	131	#size-cells = <0>;
223ef78d	132	status = "disabled";
c3e00a0e PDS	133	};
c3e00a0e PDS	134
c04abb3a	135	i2c@7000c400 {
c04abb3a SW	136	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	137	reg = <0x7000c400 0x100>;
	138	interrupts = <0 84 0x04>;
2eaab06e SW	139	#address-cells = <1>;
2eaab06e SW	140	#size-cells = <0>;
223ef78d	141	status = "disabled";
c3e00a0e PDS	142	};
c3e00a0e PDS	143
c04abb3a	144	i2c@7000c500 {
c04abb3a SW	145	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	146	reg = <0x7000c500 0x100>;
	147	interrupts = <0 92 0x04>;
2eaab06e SW	148	#address-cells = <1>;
2eaab06e SW	149	#size-cells = <0>;
223ef78d	150	status = "disabled";
c3e00a0e PDS	151	};
c3e00a0e PDS	152
c04abb3a	153	i2c@7000c700 {
c04abb3a SW	154	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	155	reg = <0x7000c700 0x100>;
	156	interrupts = <0 120 0x04>;
2eaab06e SW	157	#address-cells = <1>;
2eaab06e SW	158	#size-cells = <0>;
223ef78d	159	status = "disabled";
c3e00a0e PDS	160	};
c3e00a0e PDS	161
c04abb3a	162	i2c@7000d000 {
c04abb3a SW	163	compatible = "nvidia,tegra30-i2c", "nvidia,tegra20-i2c";
	164	reg = <0x7000d000 0x100>;
	165	interrupts = <0 53 0x04>;
2eaab06e SW	166	#address-cells = <1>;
2eaab06e SW	167	#size-cells = <0>;
223ef78d	168	status = "disabled";
c04abb3a SW	169	};
	170
	171	pmc {
	172	compatible = "nvidia,tegra20-pmc", "nvidia,tegra30-pmc";
	173	reg = <0x7000e400 0x400>;
	174	};
	175
a9140aa5	176	memory-controller {
c04abb3a SW	177	compatible = "nvidia,tegra30-mc";
	178	reg = <0x7000f000 0x010
	179	0x7000f03c 0x1b4
	180	0x7000f200 0x028
	181	0x7000f284 0x17c>;
	182	interrupts = <0 77 0x04>;
	183	};
	184
	185	smmu {
	186	compatible = "nvidia,tegra30-smmu";
	187	reg = <0x7000f010 0x02c
	188	0x7000f1f0 0x010
	189	0x7000f228 0x05c>;
	190	nvidia,#asids = <4>; /* # of ASIDs */
	191	dma-window = <0 0x40000000>; /* IOVA start & length */
	192	nvidia,ahb = <&ahb>;
c3e00a0e	193	};
9ee6a5c4 SW	194
	195	ahub {
	196	compatible = "nvidia,tegra30-ahub";
5ff48887 SW	197	reg = <0x70080000 0x200
5ff48887 SW	198	0x70080200 0x100>;
95decf84	199	interrupts = <0 103 0x04>;
9ee6a5c4 SW	200	nvidia,dma-request-selector = <&apbdma 1>;
	201
	202	ranges;
	203	#address-cells = <1>;
	204	#size-cells = <1>;
	205
	206	tegra_i2s0: i2s@70080300 {
	207	compatible = "nvidia,tegra30-i2s";
	208	reg = <0x70080300 0x100>;
	209	nvidia,ahub-cif-ids = <4 4>;
223ef78d	210	status = "disabled";
9ee6a5c4 SW	211	};
	212
	213	tegra_i2s1: i2s@70080400 {
	214	compatible = "nvidia,tegra30-i2s";
	215	reg = <0x70080400 0x100>;
	216	nvidia,ahub-cif-ids = <5 5>;
223ef78d	217	status = "disabled";
9ee6a5c4 SW	218	};
	219
	220	tegra_i2s2: i2s@70080500 {
	221	compatible = "nvidia,tegra30-i2s";
	222	reg = <0x70080500 0x100>;
	223	nvidia,ahub-cif-ids = <6 6>;
223ef78d	224	status = "disabled";
9ee6a5c4 SW	225	};
	226
	227	tegra_i2s3: i2s@70080600 {
	228	compatible = "nvidia,tegra30-i2s";
	229	reg = <0x70080600 0x100>;
	230	nvidia,ahub-cif-ids = <7 7>;
223ef78d	231	status = "disabled";
9ee6a5c4 SW	232	};
	233
	234	tegra_i2s4: i2s@70080700 {
	235	compatible = "nvidia,tegra30-i2s";
	236	reg = <0x70080700 0x100>;
	237	nvidia,ahub-cif-ids = <8 8>;
223ef78d	238	status = "disabled";
9ee6a5c4 SW	239	};
9ee6a5c4 SW	240	};
7868a9bc	241
c04abb3a SW	242	sdhci@78000000 {
	243	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	244	reg = <0x78000000 0x200>;
	245	interrupts = <0 14 0x04>;
223ef78d	246	status = "disabled";
7868a9bc	247	};
ecf43742	248
c04abb3a SW	249	sdhci@78000200 {
	250	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	251	reg = <0x78000200 0x200>;
	252	interrupts = <0 15 0x04>;
223ef78d	253	status = "disabled";
ecf43742	254	};
54174a33	255
c04abb3a SW	256	sdhci@78000400 {
	257	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	258	reg = <0x78000400 0x200>;
	259	interrupts = <0 19 0x04>;
223ef78d	260	status = "disabled";
c04abb3a SW	261	};
	262
	263	sdhci@78000600 {
	264	compatible = "nvidia,tegra30-sdhci", "nvidia,tegra20-sdhci";
	265	reg = <0x78000600 0x200>;
	266	interrupts = <0 31 0x04>;
223ef78d	267	status = "disabled";
c04abb3a SW	268	};
	269
	270	pmu {
	271	compatible = "arm,cortex-a9-pmu";
	272	interrupts = <0 144 0x04
	273	0 145 0x04
	274	0 146 0x04
	275	0 147 0x04>;
54174a33	276	};
c3e00a0e	277	};