projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 629b557a MY |
1 | /* |
| 2 | * Device Tree Source commonly used by UniPhier ARM SoCs | |
| 3 | * | |
| 4 | * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> | |
| 5 | * | |
| 6 | * This file is dual-licensed: you can use it either under the terms | |
| 7 | * of the GPL or the X11 license, at your option. Note that this dual | |
| 8 | * licensing only applies to this file, and not this project as a | |
| 9 | * whole. | |
| 10 | * | |
| 11 | * a) This file is free software; you can redistribute it and/or | |
| 12 | * modify it under the terms of the GNU General Public License as | |
| 13 | * published by the Free Software Foundation; either version 2 of the | |
| 14 | * License, or (at your option) any later version. | |
| 15 | * | |
| 16 | * This file is distributed in the hope that it will be useful, | |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 19 | * GNU General Public License for more details. | |
| 20 | * | |
| 21 | * Or, alternatively, | |
| 22 | * | |
| 23 | * b) Permission is hereby granted, free of charge, to any person | |
| 24 | * obtaining a copy of this software and associated documentation | |
| 25 | * files (the "Software"), to deal in the Software without | |
| 26 | * restriction, including without limitation the rights to use, | |
| 27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
| 28 | * sell copies of the Software, and to permit persons to whom the | |
| 29 | * Software is furnished to do so, subject to the following | |
| 30 | * conditions: | |
| 31 | * | |
| 32 | * The above copyright notice and this permission notice shall be | |
| 33 | * included in all copies or substantial portions of the Software. | |
| 34 | * | |
| 35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
| 36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
| 37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
| 38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
| 39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
| 40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
| 41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
| 42 | * OTHER DEALINGS IN THE SOFTWARE. | |
| 43 | */ | |
| 44 | ||
| 45 | /include/ "skeleton.dtsi" | |
| 46 | ||
| 47 | / { | |
| 48 | soc: soc { | |
| 49 | compatible = "simple-bus"; | |
| 50 | #address-cells = <1>; | |
| 51 | #size-cells = <1>; | |
| 52 | ranges; | |
| 53 | interrupt-parent = <&intc>; | |
| 54 | ||
| 55 | extbus: extbus { | |
| 56 | compatible = "simple-bus"; | |
| 57 | #address-cells = <2>; | |
| 58 | #size-cells = <1>; | |
| 59 | }; | |
| 60 | ||
| 61 | serial0: serial@54006800 { | |
| 62 | compatible = "socionext,uniphier-uart"; | |
| 63 | status = "disabled"; | |
| 64 | reg = <0x54006800 0x40>; | |
| 65 | interrupts = <0 33 4>; | |
| 66 | pinctrl-names = "default"; | |
| 67 | pinctrl-0 = <&pinctrl_uart0>; | |
| 68 | clocks = <&uart_clk>; | |
| 69 | }; | |
| 70 | ||
| 71 | serial1: serial@54006900 { | |
| 72 | compatible = "socionext,uniphier-uart"; | |
| 73 | status = "disabled"; | |
| 74 | reg = <0x54006900 0x40>; | |
| 75 | interrupts = <0 35 4>; | |
| 76 | pinctrl-names = "default"; | |
| 77 | pinctrl-0 = <&pinctrl_uart1>; | |
| 78 | clocks = <&uart_clk>; | |
| 79 | }; | |
| 80 | ||
| 81 | serial2: serial@54006a00 { | |
| 82 | compatible = "socionext,uniphier-uart"; | |
| 83 | status = "disabled"; | |
| 84 | reg = <0x54006a00 0x40>; | |
| 85 | interrupts = <0 37 4>; | |
| 86 | pinctrl-names = "default"; | |
| 87 | pinctrl-0 = <&pinctrl_uart2>; | |
| 88 | clocks = <&uart_clk>; | |
| 89 | }; | |
| 90 | ||
| 91 | serial3: serial@54006b00 { | |
| 92 | compatible = "socionext,uniphier-uart"; | |
| 93 | status = "disabled"; | |
| 94 | reg = <0x54006b00 0x40>; | |
| 95 | interrupts = <0 177 4>; | |
| 96 | pinctrl-names = "default"; | |
| 97 | pinctrl-0 = <&pinctrl_uart3>; | |
| 98 | clocks = <&uart_clk>; | |
| 99 | }; | |
| 100 | ||
| 101 | system-bus-controller@58c00000 { | |
| 102 | compatible = "socionext,uniphier-system-bus-controller"; | |
| 103 | reg = <0x58c00000 0x400>, <0x59800000 0x2000>; | |
| 104 | }; | |
| 105 | ||
| 106 | timer@60000200 { | |
| 107 | compatible = "arm,cortex-a9-global-timer"; | |
| 108 | reg = <0x60000200 0x20>; | |
| 109 | interrupts = <1 11 0x104>; | |
| 110 | clocks = <&arm_timer_clk>; | |
| 111 | }; | |
| 112 | ||
| 113 | timer@60000600 { | |
| 114 | compatible = "arm,cortex-a9-twd-timer"; | |
| 115 | reg = <0x60000600 0x20>; | |
| 116 | interrupts = <1 13 0x104>; | |
| 117 | clocks = <&arm_timer_clk>; | |
| 118 | }; | |
| 119 | ||
| 120 | intc: interrupt-controller@60001000 { | |
| 121 | compatible = "arm,cortex-a9-gic"; | |
| 122 | reg = <0x60001000 0x1000>, | |
| 123 | <0x60000100 0x100>; | |
| 124 | #interrupt-cells = <3>; | |
| 125 | interrupt-controller; | |
| 126 | }; | |
| 127 | ||
| 128 | pinctrl: pinctrl@5f801000 { | |
| 129 | /* specify compatible in each SoC DTSI */ | |
| 130 | reg = <0x5f801000 0xe00>; | |
| 131 | }; | |
| 132 | }; | |
| 133 | }; | |
| 134 | ||
| 135 | /include/ "uniphier-pinctrl.dtsi" |