[deliverable/linux.git] / arch / arm / boot / dts / uniphier-ph1-sld3.dtsi

/*
 * Device Tree Source for UniPhier PH1-sLD3 SoC
 *
 * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License as
 *     published by the Free Software Foundation; either version 2 of the
 *     License, or (at your option) any later version.
 *
 *     This file is distributed in the hope that it will be useful,
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively,
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use,
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/include/ "skeleton.dtsi"

/ {
	compatible = "socionext,ph1-sld3";

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;
		enable-method = "socionext,uniphier-smp";

		cpu@0 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <0>;
			next-level-cache = <&l2>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arm,cortex-a9";
			reg = <1>;
			next-level-cache = <&l2>;
		};
	};

	clocks {
		arm_timer_clk: arm_timer_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};

		uart_clk: uart_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <36864000>;
		};

		iobus_clk: iobus_clk {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <100000000>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		interrupt-parent = <&intc>;

		timer@20000200 {
			compatible = "arm,cortex-a9-global-timer";
			reg = <0x20000200 0x20>;
			interrupts = <1 11 0x304>;
			clocks = <&arm_timer_clk>;
		};

		timer@20000600 {
			compatible = "arm,cortex-a9-twd-timer";
			reg = <0x20000600 0x20>;
			interrupts = <1 13 0x304>;
			clocks = <&arm_timer_clk>;
		};

		intc: interrupt-controller@20001000 {
			compatible = "arm,cortex-a9-gic";
			#interrupt-cells = <3>;
			interrupt-controller;
			reg = <0x20001000 0x1000>,
			      <0x20000100 0x100>;
		};

		l2: l2-cache@500c0000 {
			compatible = "socionext,uniphier-system-cache";
			reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
			      <0x506c0000 0x400>;
			interrupts = <0 174 4>, <0 175 4>;
			cache-unified;
			cache-size = <(512 * 1024)>;
			cache-sets = <256>;
			cache-line-size = <128>;
			cache-level = <2>;
		};

		serial0: serial@54006800 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006800 0x40>;
			interrupts = <0 33 4>;
			clocks = <&uart_clk>;
			fifo-size = <64>;
		};

		serial1: serial@54006900 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006900 0x40>;
			interrupts = <0 35 4>;
			clocks = <&uart_clk>;
			fifo-size = <64>;
		};

		serial2: serial@54006a00 {
			compatible = "socionext,uniphier-uart";
			status = "disabled";
			reg = <0x54006a00 0x40>;
			interrupts = <0 37 4>;
			clocks = <&uart_clk>;
			fifo-size = <64>;
		};

		i2c0: i2c@58400000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58400000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 41 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <100000>;
		};

		i2c1: i2c@58480000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58480000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 42 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <100000>;
		};

		i2c2: i2c@58500000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58500000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 43 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <100000>;
		};

		i2c3: i2c@58580000 {
			compatible = "socionext,uniphier-i2c";
			status = "disabled";
			reg = <0x58580000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 44 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <100000>;
		};

		/* chip-internal connection for DMD */
		i2c4: i2c@58600000 {
			compatible = "socionext,uniphier-i2c";
			reg = <0x58600000 0x40>;
			#address-cells = <1>;
			#size-cells = <0>;
			interrupts = <0 45 1>;
			clocks = <&iobus_clk>;
			clock-frequency = <400000>;
		};

		system_bus: system-bus@58c00000 {
			compatible = "socionext,uniphier-system-bus";
			status = "disabled";
			reg = <0x58c00000 0x400>;
			#address-cells = <2>;
			#size-cells = <1>;
		};

		smpctrl@59800000 {
			compatible = "socionext,uniphier-smpctrl";
			reg = <0x59801000 0x400>;
		};

		usb0: usb@5a800100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a800100 0x100>;
			interrupts = <0 80 4>;
		};

		usb1: usb@5a810100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a810100 0x100>;
			interrupts = <0 81 4>;
		};

		usb2: usb@5a820100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a820100 0x100>;
			interrupts = <0 82 4>;
		};

		usb3: usb@5a830100 {
			compatible = "socionext,uniphier-ehci", "generic-ehci";
			status = "disabled";
			reg = <0x5a830100 0x100>;
			interrupts = <0 83 4>;
		};
	};
};
Commit	Line	Data
8e678e06 MY	1	/*
	2	* Device Tree Source for UniPhier PH1-sLD3 SoC
	3	*
	4	* Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com>
	5	*
	6	* This file is dual-licensed: you can use it either under the terms
	7	* of the GPL or the X11 license, at your option. Note that this dual
	8	* licensing only applies to this file, and not this project as a
	9	* whole.
	10	*
	11	* a) This file is free software; you can redistribute it and/or
	12	* modify it under the terms of the GNU General Public License as
	13	* published by the Free Software Foundation; either version 2 of the
	14	* License, or (at your option) any later version.
	15	*
	16	* This file is distributed in the hope that it will be useful,
	17	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	18	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	19	* GNU General Public License for more details.
	20	*
	21	* Or, alternatively,
	22	*
	23	* b) Permission is hereby granted, free of charge, to any person
	24	* obtaining a copy of this software and associated documentation
	25	* files (the "Software"), to deal in the Software without
	26	* restriction, including without limitation the rights to use,
	27	* copy, modify, merge, publish, distribute, sublicense, and/or
	28	* sell copies of the Software, and to permit persons to whom the
	29	* Software is furnished to do so, subject to the following
	30	* conditions:
	31	*
	32	* The above copyright notice and this permission notice shall be
	33	* included in all copies or substantial portions of the Software.
	34	*
	35	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
	36	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	37	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	38	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	39	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
	40	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	41	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	42	* OTHER DEALINGS IN THE SOFTWARE.
	43	*/
	44
	45	/include/ "skeleton.dtsi"
	46
	47	/ {
	48	compatible = "socionext,ph1-sld3";
	49
	50	cpus {
	51	#address-cells = <1>;
	52	#size-cells = <0>;
	53	enable-method = "socionext,uniphier-smp";
	54
	55	cpu@0 {
	56	device_type = "cpu";
	57	compatible = "arm,cortex-a9";
	58	reg = <0>;
7c62f299	59	next-level-cache = <&l2>;
8e678e06 MY	60	};
	61
	62	cpu@1 {
	63	device_type = "cpu";
	64	compatible = "arm,cortex-a9";
	65	reg = <1>;
7c62f299	66	next-level-cache = <&l2>;
8e678e06 MY	67	};
	68	};
	69
	70	clocks {
	71	arm_timer_clk: arm_timer_clk {
	72	#clock-cells = <0>;
	73	compatible = "fixed-clock";
	74	clock-frequency = <50000000>;
	75	};
1bf42507 MY	76
	77	uart_clk: uart_clk {
	78	#clock-cells = <0>;
	79	compatible = "fixed-clock";
	80	clock-frequency = <36864000>;
	81	};
68f46897 MY	82
	83	iobus_clk: iobus_clk {
	84	#clock-cells = <0>;
	85	compatible = "fixed-clock";
	86	clock-frequency = <100000000>;
	87	};
8e678e06 MY	88	};
	89
	90	soc {
	91	compatible = "simple-bus";
	92	#address-cells = <1>;
	93	#size-cells = <1>;
	94	ranges;
	95	interrupt-parent = <&intc>;
	96
8e678e06 MY	97	timer@20000200 {
	98	compatible = "arm,cortex-a9-global-timer";
	99	reg = <0x20000200 0x20>;
	100	interrupts = <1 11 0x304>;
	101	clocks = <&arm_timer_clk>;
	102	};
	103
	104	timer@20000600 {
	105	compatible = "arm,cortex-a9-twd-timer";
	106	reg = <0x20000600 0x20>;
	107	interrupts = <1 13 0x304>;
	108	clocks = <&arm_timer_clk>;
	109	};
	110
	111	intc: interrupt-controller@20001000 {
	112	compatible = "arm,cortex-a9-gic";
	113	#interrupt-cells = <3>;
	114	interrupt-controller;
	115	reg = <0x20001000 0x1000>,
	116	<0x20000100 0x100>;
	117	};
	118
7c62f299 MY	119	l2: l2-cache@500c0000 {
	120	compatible = "socionext,uniphier-system-cache";
	121	reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
	122	<0x506c0000 0x400>;
	123	interrupts = <0 174 4>, <0 175 4>;
	124	cache-unified;
	125	cache-size = <(512 * 1024)>;
	126	cache-sets = <256>;
	127	cache-line-size = <128>;
	128	cache-level = <2>;
	129	};
	130
1bf42507 MY	131	serial0: serial@54006800 {
	132	compatible = "socionext,uniphier-uart";
	133	status = "disabled";
	134	reg = <0x54006800 0x40>;
	135	interrupts = <0 33 4>;
	136	clocks = <&uart_clk>;
	137	fifo-size = <64>;
	138	};
	139
	140	serial1: serial@54006900 {
	141	compatible = "socionext,uniphier-uart";
	142	status = "disabled";
	143	reg = <0x54006900 0x40>;
	144	interrupts = <0 35 4>;
	145	clocks = <&uart_clk>;
	146	fifo-size = <64>;
	147	};
	148
	149	serial2: serial@54006a00 {
	150	compatible = "socionext,uniphier-uart";
	151	status = "disabled";
	152	reg = <0x54006a00 0x40>;
	153	interrupts = <0 37 4>;
	154	clocks = <&uart_clk>;
	155	fifo-size = <64>;
	156	};
	157
68f46897 MY	158	i2c0: i2c@58400000 {
	159	compatible = "socionext,uniphier-i2c";
	160	status = "disabled";
	161	reg = <0x58400000 0x40>;
	162	#address-cells = <1>;
	163	#size-cells = <0>;
	164	interrupts = <0 41 1>;
	165	clocks = <&iobus_clk>;
	166	clock-frequency = <100000>;
	167	};
	168
	169	i2c1: i2c@58480000 {
	170	compatible = "socionext,uniphier-i2c";
	171	status = "disabled";
	172	reg = <0x58480000 0x40>;
	173	#address-cells = <1>;
	174	#size-cells = <0>;
	175	interrupts = <0 42 1>;
	176	clocks = <&iobus_clk>;
	177	clock-frequency = <100000>;
	178	};
	179
	180	i2c2: i2c@58500000 {
	181	compatible = "socionext,uniphier-i2c";
	182	status = "disabled";
	183	reg = <0x58500000 0x40>;
	184	#address-cells = <1>;
	185	#size-cells = <0>;
	186	interrupts = <0 43 1>;
	187	clocks = <&iobus_clk>;
	188	clock-frequency = <100000>;
	189	};
	190
	191	i2c3: i2c@58580000 {
	192	compatible = "socionext,uniphier-i2c";
	193	status = "disabled";
	194	reg = <0x58580000 0x40>;
	195	#address-cells = <1>;
	196	#size-cells = <0>;
	197	interrupts = <0 44 1>;
	198	clocks = <&iobus_clk>;
	199	clock-frequency = <100000>;
	200	};
	201
	202	/* chip-internal connection for DMD */
	203	i2c4: i2c@58600000 {
	204	compatible = "socionext,uniphier-i2c";
	205	reg = <0x58600000 0x40>;
	206	#address-cells = <1>;
	207	#size-cells = <0>;
	208	interrupts = <0 45 1>;
	209	clocks = <&iobus_clk>;
	210	clock-frequency = <400000>;
	211	};
	212
14bae133 MY	213	system_bus: system-bus@58c00000 {
	214	compatible = "socionext,uniphier-system-bus";
	215	status = "disabled";
	216	reg = <0x58c00000 0x400>;
	217	#address-cells = <2>;
	218	#size-cells = <1>;
	219	};
	220
	221	smpctrl@59800000 {
	222	compatible = "socionext,uniphier-smpctrl";
	223	reg = <0x59801000 0x400>;
8e678e06	224	};
3fbf02a8 MY	225
	226	usb0: usb@5a800100 {
	227	compatible = "socionext,uniphier-ehci", "generic-ehci";
	228	status = "disabled";
	229	reg = <0x5a800100 0x100>;
	230	interrupts = <0 80 4>;
	231	};
	232
	233	usb1: usb@5a810100 {
	234	compatible = "socionext,uniphier-ehci", "generic-ehci";
	235	status = "disabled";
	236	reg = <0x5a810100 0x100>;
	237	interrupts = <0 81 4>;
	238	};
	239
	240	usb2: usb@5a820100 {
	241	compatible = "socionext,uniphier-ehci", "generic-ehci";
	242	status = "disabled";
	243	reg = <0x5a820100 0x100>;
	244	interrupts = <0 82 4>;
	245	};
	246
	247	usb3: usb@5a830100 {
	248	compatible = "socionext,uniphier-ehci", "generic-ehci";
	249	status = "disabled";
	250	reg = <0x5a830100 0x100>;
	251	interrupts = <0 83 4>;
	252	};
8e678e06 MY	253	};
8e678e06 MY	254	};