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a5e921b4 MY |
1 | /* |
2 | * Device Tree Source for UniPhier ProXstream2 SoC | |
3 | * | |
4 | * Copyright (C) 2015 Masahiro Yamada <yamada.masahiro@socionext.com> | |
5 | * | |
6 | * This file is dual-licensed: you can use it either under the terms | |
7 | * of the GPL or the X11 license, at your option. Note that this dual | |
8 | * licensing only applies to this file, and not this project as a | |
9 | * whole. | |
10 | * | |
11 | * a) This file is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of the | |
14 | * License, or (at your option) any later version. | |
15 | * | |
16 | * This file is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * Or, alternatively, | |
22 | * | |
23 | * b) Permission is hereby granted, free of charge, to any person | |
24 | * obtaining a copy of this software and associated documentation | |
25 | * files (the "Software"), to deal in the Software without | |
26 | * restriction, including without limitation the rights to use, | |
27 | * copy, modify, merge, publish, distribute, sublicense, and/or | |
28 | * sell copies of the Software, and to permit persons to whom the | |
29 | * Software is furnished to do so, subject to the following | |
30 | * conditions: | |
31 | * | |
32 | * The above copyright notice and this permission notice shall be | |
33 | * included in all copies or substantial portions of the Software. | |
34 | * | |
35 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, | |
36 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES | |
37 | * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND | |
38 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT | |
39 | * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, | |
40 | * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
41 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR | |
42 | * OTHER DEALINGS IN THE SOFTWARE. | |
43 | */ | |
44 | ||
45 | /include/ "skeleton.dtsi" | |
46 | ||
47 | / { | |
48 | compatible = "socionext,proxstream2"; | |
49 | ||
50 | cpus { | |
51 | #address-cells = <1>; | |
52 | #size-cells = <0>; | |
53 | enable-method = "socionext,uniphier-smp"; | |
54 | ||
55 | cpu@0 { | |
56 | device_type = "cpu"; | |
57 | compatible = "arm,cortex-a9"; | |
58 | reg = <0>; | |
7c62f299 | 59 | next-level-cache = <&l2>; |
a5e921b4 MY |
60 | }; |
61 | ||
62 | cpu@1 { | |
63 | device_type = "cpu"; | |
64 | compatible = "arm,cortex-a9"; | |
65 | reg = <1>; | |
7c62f299 | 66 | next-level-cache = <&l2>; |
a5e921b4 MY |
67 | }; |
68 | ||
69 | cpu@2 { | |
70 | device_type = "cpu"; | |
71 | compatible = "arm,cortex-a9"; | |
72 | reg = <2>; | |
7c62f299 | 73 | next-level-cache = <&l2>; |
a5e921b4 MY |
74 | }; |
75 | ||
76 | cpu@3 { | |
77 | device_type = "cpu"; | |
78 | compatible = "arm,cortex-a9"; | |
79 | reg = <3>; | |
7c62f299 | 80 | next-level-cache = <&l2>; |
a5e921b4 MY |
81 | }; |
82 | }; | |
83 | ||
84 | clocks { | |
85 | arm_timer_clk: arm_timer_clk { | |
86 | #clock-cells = <0>; | |
87 | compatible = "fixed-clock"; | |
88 | clock-frequency = <50000000>; | |
89 | }; | |
90 | ||
91 | uart_clk: uart_clk { | |
92 | #clock-cells = <0>; | |
93 | compatible = "fixed-clock"; | |
94 | clock-frequency = <88900000>; | |
95 | }; | |
96 | ||
97 | i2c_clk: i2c_clk { | |
98 | #clock-cells = <0>; | |
99 | compatible = "fixed-clock"; | |
100 | clock-frequency = <50000000>; | |
101 | }; | |
102 | }; | |
103 | ||
104 | soc { | |
105 | compatible = "simple-bus"; | |
106 | #address-cells = <1>; | |
107 | #size-cells = <1>; | |
108 | ranges; | |
109 | interrupt-parent = <&intc>; | |
110 | ||
111 | extbus: extbus { | |
112 | compatible = "simple-bus"; | |
113 | #address-cells = <2>; | |
114 | #size-cells = <1>; | |
115 | }; | |
116 | ||
7c62f299 MY |
117 | l2: l2-cache@500c0000 { |
118 | compatible = "socionext,uniphier-system-cache"; | |
119 | reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, | |
120 | <0x506c0000 0x400>; | |
121 | interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>; | |
122 | cache-unified; | |
123 | cache-size = <(1280 * 1024)>; | |
124 | cache-sets = <512>; | |
125 | cache-line-size = <128>; | |
126 | cache-level = <2>; | |
127 | }; | |
128 | ||
a5e921b4 MY |
129 | serial0: serial@54006800 { |
130 | compatible = "socionext,uniphier-uart"; | |
131 | status = "disabled"; | |
132 | reg = <0x54006800 0x40>; | |
133 | pinctrl-names = "default"; | |
134 | pinctrl-0 = <&pinctrl_uart0>; | |
135 | interrupts = <0 33 4>; | |
136 | clocks = <&uart_clk>; | |
137 | }; | |
138 | ||
139 | serial1: serial@54006900 { | |
140 | compatible = "socionext,uniphier-uart"; | |
141 | status = "disabled"; | |
142 | reg = <0x54006900 0x40>; | |
143 | pinctrl-names = "default"; | |
144 | pinctrl-0 = <&pinctrl_uart1>; | |
145 | interrupts = <0 35 4>; | |
146 | clocks = <&uart_clk>; | |
147 | }; | |
148 | ||
149 | serial2: serial@54006a00 { | |
150 | compatible = "socionext,uniphier-uart"; | |
151 | status = "disabled"; | |
152 | reg = <0x54006a00 0x40>; | |
153 | pinctrl-names = "default"; | |
154 | pinctrl-0 = <&pinctrl_uart2>; | |
155 | interrupts = <0 37 4>; | |
156 | clocks = <&uart_clk>; | |
157 | }; | |
158 | ||
159 | serial3: serial@54006b00 { | |
160 | compatible = "socionext,uniphier-uart"; | |
161 | status = "disabled"; | |
162 | reg = <0x54006b00 0x40>; | |
163 | pinctrl-names = "default"; | |
164 | pinctrl-0 = <&pinctrl_uart3>; | |
165 | interrupts = <0 177 4>; | |
166 | clocks = <&uart_clk>; | |
167 | }; | |
168 | ||
169 | i2c0: i2c@58780000 { | |
170 | compatible = "socionext,uniphier-fi2c"; | |
171 | status = "disabled"; | |
172 | reg = <0x58780000 0x80>; | |
173 | #address-cells = <1>; | |
174 | #size-cells = <0>; | |
175 | pinctrl-names = "default"; | |
176 | pinctrl-0 = <&pinctrl_i2c0>; | |
177 | interrupts = <0 41 4>; | |
178 | clocks = <&i2c_clk>; | |
179 | clock-frequency = <100000>; | |
180 | }; | |
181 | ||
182 | i2c1: i2c@58781000 { | |
183 | compatible = "socionext,uniphier-fi2c"; | |
184 | status = "disabled"; | |
185 | reg = <0x58781000 0x80>; | |
186 | #address-cells = <1>; | |
187 | #size-cells = <0>; | |
188 | pinctrl-names = "default"; | |
189 | pinctrl-0 = <&pinctrl_i2c1>; | |
190 | interrupts = <0 42 4>; | |
191 | clocks = <&i2c_clk>; | |
192 | clock-frequency = <100000>; | |
193 | }; | |
194 | ||
195 | i2c2: i2c@58782000 { | |
196 | compatible = "socionext,uniphier-fi2c"; | |
197 | status = "disabled"; | |
198 | reg = <0x58782000 0x80>; | |
199 | #address-cells = <1>; | |
200 | #size-cells = <0>; | |
201 | pinctrl-names = "default"; | |
202 | pinctrl-0 = <&pinctrl_i2c2>; | |
203 | interrupts = <0 43 4>; | |
204 | clocks = <&i2c_clk>; | |
205 | clock-frequency = <100000>; | |
206 | }; | |
207 | ||
208 | i2c3: i2c@58783000 { | |
209 | compatible = "socionext,uniphier-fi2c"; | |
210 | status = "disabled"; | |
211 | reg = <0x58783000 0x80>; | |
212 | #address-cells = <1>; | |
213 | #size-cells = <0>; | |
214 | pinctrl-names = "default"; | |
215 | pinctrl-0 = <&pinctrl_i2c3>; | |
216 | interrupts = <0 44 4>; | |
217 | clocks = <&i2c_clk>; | |
218 | clock-frequency = <100000>; | |
219 | }; | |
220 | ||
221 | /* chip-internal connection for DMD */ | |
222 | i2c4: i2c@58784000 { | |
223 | compatible = "socionext,uniphier-fi2c"; | |
224 | reg = <0x58784000 0x80>; | |
225 | #address-cells = <1>; | |
226 | #size-cells = <0>; | |
227 | interrupts = <0 45 4>; | |
228 | clocks = <&i2c_clk>; | |
229 | clock-frequency = <400000>; | |
230 | }; | |
231 | ||
232 | /* chip-internal connection for STM */ | |
233 | i2c5: i2c@58785000 { | |
234 | compatible = "socionext,uniphier-fi2c"; | |
235 | reg = <0x58785000 0x80>; | |
236 | #address-cells = <1>; | |
237 | #size-cells = <0>; | |
238 | interrupts = <0 25 4>; | |
239 | clocks = <&i2c_clk>; | |
240 | clock-frequency = <400000>; | |
241 | }; | |
242 | ||
243 | /* chip-internal connection for HDMI */ | |
244 | i2c6: i2c@58786000 { | |
245 | compatible = "socionext,uniphier-fi2c"; | |
246 | reg = <0x58786000 0x80>; | |
247 | #address-cells = <1>; | |
248 | #size-cells = <0>; | |
249 | interrupts = <0 26 4>; | |
250 | clocks = <&i2c_clk>; | |
251 | clock-frequency = <400000>; | |
252 | }; | |
253 | ||
1b38b0e3 MY |
254 | system-bus-controller@58c00000 { |
255 | compatible = "socionext,uniphier-system-bus-controller"; | |
256 | reg = <0x58c00000 0x400>, <0x59800000 0x2000>; | |
a5e921b4 MY |
257 | }; |
258 | ||
259 | pinctrl: pinctrl@5f801000 { | |
260 | compatible = "socionext,proxstream2-pinctrl", "syscon"; | |
261 | reg = <0x5f801000 0xe00>; | |
262 | }; | |
263 | ||
264 | timer@60000200 { | |
265 | compatible = "arm,cortex-a9-global-timer"; | |
266 | reg = <0x60000200 0x20>; | |
f2032f24 | 267 | interrupts = <1 11 0xf04>; |
a5e921b4 MY |
268 | clocks = <&arm_timer_clk>; |
269 | }; | |
270 | ||
271 | timer@60000600 { | |
272 | compatible = "arm,cortex-a9-twd-timer"; | |
273 | reg = <0x60000600 0x20>; | |
f2032f24 | 274 | interrupts = <1 13 0xf04>; |
a5e921b4 MY |
275 | clocks = <&arm_timer_clk>; |
276 | }; | |
277 | ||
278 | intc: interrupt-controller@60001000 { | |
279 | compatible = "arm,cortex-a9-gic"; | |
280 | #interrupt-cells = <3>; | |
281 | interrupt-controller; | |
282 | reg = <0x60001000 0x1000>, | |
283 | <0x60000100 0x100>; | |
284 | }; | |
285 | }; | |
286 | }; | |
287 | ||
288 | /include/ "uniphier-pinctrl.dtsi" |