[deliverable/linux.git] / arch / arm / boot / dts / versatile-ab.dts

/dts-v1/;
/include/ "skeleton.dtsi"

/ {
	model = "ARM Versatile AB";
	compatible = "arm,versatile-ab";
	#address-cells = <1>;
	#size-cells = <1>;
	interrupt-parent = <&vic>;

	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		i2c0 = &i2c0;
	};

	chosen {
		stdout-path = &uart0;
	};

	memory {
		reg = <0x0 0x08000000>;
	};

	xtal24mhz: xtal24mhz@24M {
		#clock-cells = <0>;
		compatible = "fixed-clock";
		clock-frequency = <24000000>;
	};

	core-module@10000000 {
		compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
		reg = <0x10000000 0x200>;

		led@08.0 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x01>;
			label = "versatile:0";
			linux,default-trigger = "heartbeat";
			default-state = "on";
		};
		led@08.1 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x02>;
			label = "versatile:1";
			linux,default-trigger = "mmc0";
			default-state = "off";
		};
		led@08.2 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x04>;
			label = "versatile:2";
			linux,default-trigger = "cpu0";
			default-state = "off";
		};
		led@08.3 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x08>;
			label = "versatile:3";
			default-state = "off";
		};
		led@08.4 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x10>;
			label = "versatile:4";
			default-state = "off";
		};
		led@08.5 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x20>;
			label = "versatile:5";
			default-state = "off";
		};
		led@08.6 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x40>;
			label = "versatile:6";
			default-state = "off";
		};
		led@08.7 {
			compatible = "register-bit-led";
			offset = <0x08>;
			mask = <0x80>;
			label = "versatile:7";
			default-state = "off";
		};

		/* OSC1 on AB, OSC4 on PB */
		osc1: cm_aux_osc@24M {
			#clock-cells = <0>;
			compatible = "arm,versatile-cm-auxosc";
			clocks = <&xtal24mhz>;
		};

		/* The timer clock is the 24 MHz oscillator divided to 1MHz */
		timclk: timclk@1M {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <24>;
			clock-mult = <1>;
			clocks = <&xtal24mhz>;
		};

		pclk: pclk@24M {
			#clock-cells = <0>;
			compatible = "fixed-factor-clock";
			clock-div = <1>;
			clock-mult = <1>;
			clocks = <&xtal24mhz>;
		};
	};

	flash@34000000 {
		compatible = "arm,versatile-flash";
		reg = <0x34000000 0x4000000>;
		bank-width = <4>;
	};

	i2c0: i2c@10002000 {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "arm,versatile-i2c";
		reg = <0x10002000 0x1000>;

		rtc@68 {
			compatible = "dallas,ds1338";
			reg = <0x68>;
		};
	};

	net@10010000 {
		compatible = "smsc,lan91c111";
		reg = <0x10010000 0x10000>;
		interrupts = <25>;
	};

	lcd@10008000 {
		compatible = "arm,versatile-lcd";
		reg = <0x10008000 0x1000>;
	};

	amba {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		vic: intc@10140000 {
			compatible = "arm,versatile-vic";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x10140000 0x1000>;
			clear-mask = <0xffffffff>;
			valid-mask = <0xffffffff>;
		};

		sic: intc@10003000 {
			compatible = "arm,versatile-sic";
			interrupt-controller;
			#interrupt-cells = <1>;
			reg = <0x10003000 0x1000>;
			interrupt-parent = <&vic>;
			interrupts = <31>; /* Cascaded to vic */
			clear-mask = <0xffffffff>;
			/*
			 * Valid interrupt lines mask according to
			 * table 4-36 page 4-50 of ARM DUI 0225D
			 */
			valid-mask = <0x0760031b>;
		};

		dma@10130000 {
			compatible = "arm,pl081", "arm,primecell";
			reg = <0x10130000 0x1000>;
			interrupts = <17>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		uart0: uart@101f1000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f1000 0x1000>;
			interrupts = <12>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart1: uart@101f2000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f2000 0x1000>;
			interrupts = <13>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		uart2: uart@101f3000 {
			compatible = "arm,pl011", "arm,primecell";
			reg = <0x101f3000 0x1000>;
			interrupts = <14>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "uartclk", "apb_pclk";
		};

		smc@10100000 {
			compatible = "arm,primecell";
			reg = <0x10100000 0x1000>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		mpmc@10110000 {
			compatible = "arm,primecell";
			reg = <0x10110000 0x1000>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		display@10120000 {
			compatible = "arm,pl110", "arm,primecell";
			reg = <0x10120000 0x1000>;
			interrupts = <16>;
			clocks = <&osc1>, <&pclk>;
			clock-names = "clcd", "apb_pclk";
		};

		sctl@101e0000 {
			compatible = "arm,primecell";
			reg = <0x101e0000 0x1000>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		watchdog@101e1000 {
			compatible = "arm,primecell";
			reg = <0x101e1000 0x1000>;
			interrupts = <0>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		timer@101e2000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x101e2000 0x1000>;
			interrupts = <4>;
			clocks = <&timclk>, <&timclk>, <&pclk>;
			clock-names = "timer0", "timer1", "apb_pclk";
		};

		timer@101e3000 {
			compatible = "arm,sp804", "arm,primecell";
			reg = <0x101e3000 0x1000>;
			interrupts = <5>;
			clocks = <&timclk>, <&timclk>, <&pclk>;
			clock-names = "timer0", "timer1", "apb_pclk";
		};

		gpio0: gpio@101e4000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x101e4000 0x1000>;
			gpio-controller;
			interrupts = <6>;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		gpio1: gpio@101e5000 {
			compatible = "arm,pl061", "arm,primecell";
			reg = <0x101e5000 0x1000>;
			interrupts = <7>;
			gpio-controller;
			#gpio-cells = <2>;
			interrupt-controller;
			#interrupt-cells = <2>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		rtc@101e8000 {
			compatible = "arm,pl030", "arm,primecell";
			reg = <0x101e8000 0x1000>;
			interrupts = <10>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		sci@101f0000 {
			compatible = "arm,primecell";
			reg = <0x101f0000 0x1000>;
			interrupts = <15>;
			clocks = <&pclk>;
			clock-names = "apb_pclk";
		};

		ssp@101f4000 {
			compatible = "arm,pl022", "arm,primecell";
			reg = <0x101f4000 0x1000>;
			interrupts = <11>;
			clocks = <&xtal24mhz>, <&pclk>;
			clock-names = "SSPCLK", "apb_pclk";
		};

		fpga {
			compatible = "arm,versatile-fpga", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 0x10000000 0x10000>;

			sysreg@0 {
				compatible = "arm,versatile-sysreg", "syscon";
				reg = <0x00000 0x1000>;
			};

			aaci@4000 {
				compatible = "arm,primecell";
				reg = <0x4000 0x1000>;
				interrupts = <24>;
				clocks = <&pclk>;
				clock-names = "apb_pclk";
			};
			mmc@5000 {
				compatible = "arm,pl180", "arm,primecell";
				reg = <0x5000 0x1000>;
				interrupts-extended = <&vic 22 &sic 1>;
				clocks = <&xtal24mhz>, <&pclk>;
				clock-names = "mclk", "apb_pclk";
			};
			kmi@6000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x6000 0x1000>;
				interrupt-parent = <&sic>;
				interrupts = <3>;
				clocks = <&xtal24mhz>, <&pclk>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};
			kmi@7000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x7000 0x1000>;
				interrupt-parent = <&sic>;
				interrupts = <4>;
				clocks = <&xtal24mhz>, <&pclk>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};
		};
	};
};
Commit	Line	Data
3ba7222a GL	1	/dts-v1/;
	2	/include/ "skeleton.dtsi"
	3
	4	/ {
	5	model = "ARM Versatile AB";
	6	compatible = "arm,versatile-ab";
	7	#address-cells = <1>;
	8	#size-cells = <1>;
	9	interrupt-parent = <&vic>;
	10
	11	aliases {
	12	serial0 = &uart0;
	13	serial1 = &uart1;
	14	serial2 = &uart2;
	15	i2c0 = &i2c0;
	16	};
	17
00388218 GL	18	chosen {
	19	stdout-path = &uart0;
	20	};
	21
3ba7222a GL	22	memory {
	23	reg = <0x0 0x08000000>;
	24	};
	25
2e452785 RH	26	xtal24mhz: xtal24mhz@24M {
	27	#clock-cells = <0>;
	28	compatible = "fixed-clock";
	29	clock-frequency = <24000000>;
	30	};
	31
	32	core-module@10000000 {
07ebfa59	33	compatible = "arm,core-module-versatile", "syscon", "simple-mfd";
2e452785 RH	34	reg = <0x10000000 0x200>;
2e452785 RH	35
07ebfa59 LW	36	led@08.0 {
	37	compatible = "register-bit-led";
	38	offset = <0x08>;
	39	mask = <0x01>;
	40	label = "versatile:0";
	41	linux,default-trigger = "heartbeat";
	42	default-state = "on";
	43	};
	44	led@08.1 {
	45	compatible = "register-bit-led";
	46	offset = <0x08>;
	47	mask = <0x02>;
	48	label = "versatile:1";
	49	linux,default-trigger = "mmc0";
	50	default-state = "off";
	51	};
	52	led@08.2 {
	53	compatible = "register-bit-led";
	54	offset = <0x08>;
	55	mask = <0x04>;
	56	label = "versatile:2";
	57	linux,default-trigger = "cpu0";
	58	default-state = "off";
	59	};
	60	led@08.3 {
	61	compatible = "register-bit-led";
	62	offset = <0x08>;
	63	mask = <0x08>;
	64	label = "versatile:3";
	65	default-state = "off";
	66	};
	67	led@08.4 {
	68	compatible = "register-bit-led";
	69	offset = <0x08>;
	70	mask = <0x10>;
	71	label = "versatile:4";
	72	default-state = "off";
	73	};
	74	led@08.5 {
	75	compatible = "register-bit-led";
	76	offset = <0x08>;
	77	mask = <0x20>;
	78	label = "versatile:5";
	79	default-state = "off";
	80	};
	81	led@08.6 {
	82	compatible = "register-bit-led";
	83	offset = <0x08>;
	84	mask = <0x40>;
	85	label = "versatile:6";
	86	default-state = "off";
	87	};
	88	led@08.7 {
	89	compatible = "register-bit-led";
	90	offset = <0x08>;
	91	mask = <0x80>;
	92	label = "versatile:7";
	93	default-state = "off";
	94	};
	95
2e452785 RH	96	/* OSC1 on AB, OSC4 on PB */
	97	osc1: cm_aux_osc@24M {
	98	#clock-cells = <0>;
	99	compatible = "arm,versatile-cm-auxosc";
	100	clocks = <&xtal24mhz>;
	101	};
	102
	103	/* The timer clock is the 24 MHz oscillator divided to 1MHz */
	104	timclk: timclk@1M {
	105	#clock-cells = <0>;
	106	compatible = "fixed-factor-clock";
	107	clock-div = <24>;
	108	clock-mult = <1>;
	109	clocks = <&xtal24mhz>;
	110	};
	111
	112	pclk: pclk@24M {
	113	#clock-cells = <0>;
	114	compatible = "fixed-factor-clock";
	115	clock-div = <1>;
	116	clock-mult = <1>;
	117	clocks = <&xtal24mhz>;
	118	};
	119	};
	120
3ba7222a GL	121	flash@34000000 {
	122	compatible = "arm,versatile-flash";
	123	reg = <0x34000000 0x4000000>;
	124	bank-width = <4>;
	125	};
	126
	127	i2c0: i2c@10002000 {
	128	#address-cells = <1>;
	129	#size-cells = <0>;
	130	compatible = "arm,versatile-i2c";
	131	reg = <0x10002000 0x1000>;
	132
	133	rtc@68 {
	134	compatible = "dallas,ds1338";
	135	reg = <0x68>;
	136	};
	137	};
	138
	139	net@10010000 {
	140	compatible = "smsc,lan91c111";
	141	reg = <0x10010000 0x10000>;
	142	interrupts = <25>;
	143	};
	144
	145	lcd@10008000 {
	146	compatible = "arm,versatile-lcd";
	147	reg = <0x10008000 0x1000>;
	148	};
	149
	150	amba {
2ef7d5f3	151	compatible = "simple-bus";
3ba7222a GL	152	#address-cells = <1>;
	153	#size-cells = <1>;
	154	ranges;
	155
	156	vic: intc@10140000 {
	157	compatible = "arm,versatile-vic";
	158	interrupt-controller;
	159	#interrupt-cells = <1>;
	160	reg = <0x10140000 0x1000>;
0ba6c5d2 RH	161	clear-mask = <0xffffffff>;
0ba6c5d2 RH	162	valid-mask = <0xffffffff>;
3ba7222a GL	163	};
	164
	165	sic: intc@10003000 {
	166	compatible = "arm,versatile-sic";
	167	interrupt-controller;
	168	#interrupt-cells = <1>;
	169	reg = <0x10003000 0x1000>;
	170	interrupt-parent = <&vic>;
	171	interrupts = <31>; /* Cascaded to vic */
0ba6c5d2	172	clear-mask = <0xffffffff>;
20f12758 LW	173	/*
	174	* Valid interrupt lines mask according to
	175	* table 4-36 page 4-50 of ARM DUI 0225D
	176	*/
	177	valid-mask = <0x0760031b>;
3ba7222a GL	178	};
	179
	180	dma@10130000 {
	181	compatible = "arm,pl081", "arm,primecell";
	182	reg = <0x10130000 0x1000>;
	183	interrupts = <17>;
2e452785 RH	184	clocks = <&pclk>;
2e452785 RH	185	clock-names = "apb_pclk";
3ba7222a GL	186	};
	187
	188	uart0: uart@101f1000 {
	189	compatible = "arm,pl011", "arm,primecell";
	190	reg = <0x101f1000 0x1000>;
	191	interrupts = <12>;
2e452785 RH	192	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	193	clock-names = "uartclk", "apb_pclk";
3ba7222a GL	194	};
	195
	196	uart1: uart@101f2000 {
	197	compatible = "arm,pl011", "arm,primecell";
	198	reg = <0x101f2000 0x1000>;
	199	interrupts = <13>;
2e452785 RH	200	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	201	clock-names = "uartclk", "apb_pclk";
3ba7222a GL	202	};
	203
	204	uart2: uart@101f3000 {
	205	compatible = "arm,pl011", "arm,primecell";
	206	reg = <0x101f3000 0x1000>;
	207	interrupts = <14>;
2e452785 RH	208	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	209	clock-names = "uartclk", "apb_pclk";
3ba7222a GL	210	};
	211
	212	smc@10100000 {
	213	compatible = "arm,primecell";
	214	reg = <0x10100000 0x1000>;
2e452785 RH	215	clocks = <&pclk>;
2e452785 RH	216	clock-names = "apb_pclk";
3ba7222a GL	217	};
	218
	219	mpmc@10110000 {
	220	compatible = "arm,primecell";
	221	reg = <0x10110000 0x1000>;
2e452785 RH	222	clocks = <&pclk>;
2e452785 RH	223	clock-names = "apb_pclk";
3ba7222a GL	224	};
	225
	226	display@10120000 {
	227	compatible = "arm,pl110", "arm,primecell";
	228	reg = <0x10120000 0x1000>;
	229	interrupts = <16>;
2e452785 RH	230	clocks = <&osc1>, <&pclk>;
2e452785 RH	231	clock-names = "clcd", "apb_pclk";
3ba7222a GL	232	};
	233
	234	sctl@101e0000 {
	235	compatible = "arm,primecell";
	236	reg = <0x101e0000 0x1000>;
2e452785 RH	237	clocks = <&pclk>;
2e452785 RH	238	clock-names = "apb_pclk";
3ba7222a GL	239	};
	240
	241	watchdog@101e1000 {
	242	compatible = "arm,primecell";
	243	reg = <0x101e1000 0x1000>;
	244	interrupts = <0>;
2e452785 RH	245	clocks = <&pclk>;
2e452785 RH	246	clock-names = "apb_pclk";
3ba7222a GL	247	};
3ba7222a GL	248
818270d5 RH	249	timer@101e2000 {
	250	compatible = "arm,sp804", "arm,primecell";
	251	reg = <0x101e2000 0x1000>;
	252	interrupts = <4>;
2e452785 RH	253	clocks = <&timclk>, <&timclk>, <&pclk>;
2e452785 RH	254	clock-names = "timer0", "timer1", "apb_pclk";
818270d5 RH	255	};
	256
	257	timer@101e3000 {
	258	compatible = "arm,sp804", "arm,primecell";
	259	reg = <0x101e3000 0x1000>;
	260	interrupts = <5>;
2e452785 RH	261	clocks = <&timclk>, <&timclk>, <&pclk>;
2e452785 RH	262	clock-names = "timer0", "timer1", "apb_pclk";
818270d5 RH	263	};
818270d5 RH	264
3ba7222a GL	265	gpio0: gpio@101e4000 {
	266	compatible = "arm,pl061", "arm,primecell";
	267	reg = <0x101e4000 0x1000>;
	268	gpio-controller;
	269	interrupts = <6>;
	270	#gpio-cells = <2>;
	271	interrupt-controller;
	272	#interrupt-cells = <2>;
2e452785 RH	273	clocks = <&pclk>;
2e452785 RH	274	clock-names = "apb_pclk";
3ba7222a GL	275	};
	276
	277	gpio1: gpio@101e5000 {
	278	compatible = "arm,pl061", "arm,primecell";
	279	reg = <0x101e5000 0x1000>;
	280	interrupts = <7>;
	281	gpio-controller;
	282	#gpio-cells = <2>;
	283	interrupt-controller;
	284	#interrupt-cells = <2>;
2e452785 RH	285	clocks = <&pclk>;
2e452785 RH	286	clock-names = "apb_pclk";
3ba7222a GL	287	};
	288
	289	rtc@101e8000 {
	290	compatible = "arm,pl030", "arm,primecell";
	291	reg = <0x101e8000 0x1000>;
	292	interrupts = <10>;
2e452785 RH	293	clocks = <&pclk>;
2e452785 RH	294	clock-names = "apb_pclk";
3ba7222a GL	295	};
	296
	297	sci@101f0000 {
	298	compatible = "arm,primecell";
	299	reg = <0x101f0000 0x1000>;
	300	interrupts = <15>;
2e452785 RH	301	clocks = <&pclk>;
2e452785 RH	302	clock-names = "apb_pclk";
3ba7222a GL	303	};
	304
	305	ssp@101f4000 {
	306	compatible = "arm,pl022", "arm,primecell";
	307	reg = <0x101f4000 0x1000>;
	308	interrupts = <11>;
2e452785 RH	309	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	310	clock-names = "SSPCLK", "apb_pclk";
3ba7222a GL	311	};
	312
	313	fpga {
	314	compatible = "arm,versatile-fpga", "simple-bus";
	315	#address-cells = <1>;
	316	#size-cells = <1>;
	317	ranges = <0 0x10000000 0x10000>;
	318
35a8578e RH	319	sysreg@0 {
	320	compatible = "arm,versatile-sysreg", "syscon";
	321	reg = <0x00000 0x1000>;
	322	};
	323
3ba7222a GL	324	aaci@4000 {
	325	compatible = "arm,primecell";
	326	reg = <0x4000 0x1000>;
	327	interrupts = <24>;
2e452785 RH	328	clocks = <&pclk>;
2e452785 RH	329	clock-names = "apb_pclk";
3ba7222a GL	330	};
3ba7222a GL	331	mmc@5000 {
04aa49f6	332	compatible = "arm,pl180", "arm,primecell";
20f12758 LW	333	reg = <0x5000 0x1000>;
20f12758 LW	334	interrupts-extended = <&vic 22 &sic 1>;
2e452785 RH	335	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	336	clock-names = "mclk", "apb_pclk";
3ba7222a GL	337	};
	338	kmi@6000 {
	339	compatible = "arm,pl050", "arm,primecell";
	340	reg = <0x6000 0x1000>;
	341	interrupt-parent = <&sic>;
	342	interrupts = <3>;
2e452785 RH	343	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	344	clock-names = "KMIREFCLK", "apb_pclk";
3ba7222a GL	345	};
	346	kmi@7000 {
	347	compatible = "arm,pl050", "arm,primecell";
	348	reg = <0x7000 0x1000>;
	349	interrupt-parent = <&sic>;
	350	interrupts = <4>;
2e452785 RH	351	clocks = <&xtal24mhz>, <&pclk>;
2e452785 RH	352	clock-names = "KMIREFCLK", "apb_pclk";
3ba7222a GL	353	};
	354	};
	355	};
	356	};