projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 3ba7222a GL |
1 | /dts-v1/; |
| 2 | /include/ "skeleton.dtsi" | |
| 3 | ||
| 4 | / { | |
| 5 | model = "ARM Versatile AB"; | |
| 6 | compatible = "arm,versatile-ab"; | |
| 7 | #address-cells = <1>; | |
| 8 | #size-cells = <1>; | |
| 9 | interrupt-parent = <&vic>; | |
| 10 | ||
| 11 | aliases { | |
| 12 | serial0 = &uart0; | |
| 13 | serial1 = &uart1; | |
| 14 | serial2 = &uart2; | |
| 15 | i2c0 = &i2c0; | |
| 16 | }; | |
| 17 | ||
| 18 | memory { | |
| 19 | reg = <0x0 0x08000000>; | |
| 20 | }; | |
| 21 | ||
| 22 | flash@34000000 { | |
| 23 | compatible = "arm,versatile-flash"; | |
| 24 | reg = <0x34000000 0x4000000>; | |
| 25 | bank-width = <4>; | |
| 26 | }; | |
| 27 | ||
| 28 | i2c0: i2c@10002000 { | |
| 29 | #address-cells = <1>; | |
| 30 | #size-cells = <0>; | |
| 31 | compatible = "arm,versatile-i2c"; | |
| 32 | reg = <0x10002000 0x1000>; | |
| 33 | ||
| 34 | rtc@68 { | |
| 35 | compatible = "dallas,ds1338"; | |
| 36 | reg = <0x68>; | |
| 37 | }; | |
| 38 | }; | |
| 39 | ||
| 40 | net@10010000 { | |
| 41 | compatible = "smsc,lan91c111"; | |
| 42 | reg = <0x10010000 0x10000>; | |
| 43 | interrupts = <25>; | |
| 44 | }; | |
| 45 | ||
| 46 | lcd@10008000 { | |
| 47 | compatible = "arm,versatile-lcd"; | |
| 48 | reg = <0x10008000 0x1000>; | |
| 49 | }; | |
| 50 | ||
| 51 | amba { | |
| 52 | compatible = "arm,amba-bus"; | |
| 53 | #address-cells = <1>; | |
| 54 | #size-cells = <1>; | |
| 55 | ranges; | |
| 56 | ||
| 57 | vic: intc@10140000 { | |
| 58 | compatible = "arm,versatile-vic"; | |
| 59 | interrupt-controller; | |
| 60 | #interrupt-cells = <1>; | |
| 61 | reg = <0x10140000 0x1000>; | |
| 62 | }; | |
| 63 | ||
| 64 | sic: intc@10003000 { | |
| 65 | compatible = "arm,versatile-sic"; | |
| 66 | interrupt-controller; | |
| 67 | #interrupt-cells = <1>; | |
| 68 | reg = <0x10003000 0x1000>; | |
| 69 | interrupt-parent = <&vic>; | |
| 70 | interrupts = <31>; /* Cascaded to vic */ | |
| 71 | }; | |
| 72 | ||
| 73 | dma@10130000 { | |
| 74 | compatible = "arm,pl081", "arm,primecell"; | |
| 75 | reg = <0x10130000 0x1000>; | |
| 76 | interrupts = <17>; | |
| 77 | }; | |
| 78 | ||
| 79 | uart0: uart@101f1000 { | |
| 80 | compatible = "arm,pl011", "arm,primecell"; | |
| 81 | reg = <0x101f1000 0x1000>; | |
| 82 | interrupts = <12>; | |
| 83 | }; | |
| 84 | ||
| 85 | uart1: uart@101f2000 { | |
| 86 | compatible = "arm,pl011", "arm,primecell"; | |
| 87 | reg = <0x101f2000 0x1000>; | |
| 88 | interrupts = <13>; | |
| 89 | }; | |
| 90 | ||
| 91 | uart2: uart@101f3000 { | |
| 92 | compatible = "arm,pl011", "arm,primecell"; | |
| 93 | reg = <0x101f3000 0x1000>; | |
| 94 | interrupts = <14>; | |
| 95 | }; | |
| 96 | ||
| 97 | smc@10100000 { | |
| 98 | compatible = "arm,primecell"; | |
| 99 | reg = <0x10100000 0x1000>; | |
| 100 | }; | |
| 101 | ||
| 102 | mpmc@10110000 { | |
| 103 | compatible = "arm,primecell"; | |
| 104 | reg = <0x10110000 0x1000>; | |
| 105 | }; | |
| 106 | ||
| 107 | display@10120000 { | |
| 108 | compatible = "arm,pl110", "arm,primecell"; | |
| 109 | reg = <0x10120000 0x1000>; | |
| 110 | interrupts = <16>; | |
| 111 | }; | |
| 112 | ||
| 113 | sctl@101e0000 { | |
| 114 | compatible = "arm,primecell"; | |
| 115 | reg = <0x101e0000 0x1000>; | |
| 116 | }; | |
| 117 | ||
| 118 | watchdog@101e1000 { | |
| 119 | compatible = "arm,primecell"; | |
| 120 | reg = <0x101e1000 0x1000>; | |
| 121 | interrupts = <0>; | |
| 122 | }; | |
| 123 | ||
| 818270d5 RH |
124 | timer@101e2000 { |
| 125 | compatible = "arm,sp804", "arm,primecell"; | |
| 126 | reg = <0x101e2000 0x1000>; | |
| 127 | interrupts = <4>; | |
| 128 | }; | |
| 129 | ||
| 130 | timer@101e3000 { | |
| 131 | compatible = "arm,sp804", "arm,primecell"; | |
| 132 | reg = <0x101e3000 0x1000>; | |
| 133 | interrupts = <5>; | |
| 134 | }; | |
| 135 | ||
| 3ba7222a GL |
136 | gpio0: gpio@101e4000 { |
| 137 | compatible = "arm,pl061", "arm,primecell"; | |
| 138 | reg = <0x101e4000 0x1000>; | |
| 139 | gpio-controller; | |
| 140 | interrupts = <6>; | |
| 141 | #gpio-cells = <2>; | |
| 142 | interrupt-controller; | |
| 143 | #interrupt-cells = <2>; | |
| 144 | }; | |
| 145 | ||
| 146 | gpio1: gpio@101e5000 { | |
| 147 | compatible = "arm,pl061", "arm,primecell"; | |
| 148 | reg = <0x101e5000 0x1000>; | |
| 149 | interrupts = <7>; | |
| 150 | gpio-controller; | |
| 151 | #gpio-cells = <2>; | |
| 152 | interrupt-controller; | |
| 153 | #interrupt-cells = <2>; | |
| 154 | }; | |
| 155 | ||
| 156 | rtc@101e8000 { | |
| 157 | compatible = "arm,pl030", "arm,primecell"; | |
| 158 | reg = <0x101e8000 0x1000>; | |
| 159 | interrupts = <10>; | |
| 160 | }; | |
| 161 | ||
| 162 | sci@101f0000 { | |
| 163 | compatible = "arm,primecell"; | |
| 164 | reg = <0x101f0000 0x1000>; | |
| 165 | interrupts = <15>; | |
| 166 | }; | |
| 167 | ||
| 168 | ssp@101f4000 { | |
| 169 | compatible = "arm,pl022", "arm,primecell"; | |
| 170 | reg = <0x101f4000 0x1000>; | |
| 171 | interrupts = <11>; | |
| 172 | }; | |
| 173 | ||
| 174 | fpga { | |
| 175 | compatible = "arm,versatile-fpga", "simple-bus"; | |
| 176 | #address-cells = <1>; | |
| 177 | #size-cells = <1>; | |
| 178 | ranges = <0 0x10000000 0x10000>; | |
| 179 | ||
| 180 | aaci@4000 { | |
| 181 | compatible = "arm,primecell"; | |
| 182 | reg = <0x4000 0x1000>; | |
| 183 | interrupts = <24>; | |
| 184 | }; | |
| 185 | mmc@5000 { | |
| 186 | compatible = "arm,primecell"; | |
| 187 | reg = < 0x5000 0x1000>; | |
| 754aba43 | 188 | interrupts = <22 34>; |
| 3ba7222a GL |
189 | }; |
| 190 | kmi@6000 { | |
| 191 | compatible = "arm,pl050", "arm,primecell"; | |
| 192 | reg = <0x6000 0x1000>; | |
| 193 | interrupt-parent = <&sic>; | |
| 194 | interrupts = <3>; | |
| 195 | }; | |
| 196 | kmi@7000 { | |
| 197 | compatible = "arm,pl050", "arm,primecell"; | |
| 198 | reg = <0x7000 0x1000>; | |
| 199 | interrupt-parent = <&sic>; | |
| 200 | interrupts = <4>; | |
| 201 | }; | |
| 202 | }; | |
| 203 | }; | |
| 204 | }; |