[deliverable/linux.git] / arch / arm / boot / dts / vexpress-v2m-rs1.dtsi

/*
 * ARM Ltd. Versatile Express
 *
 * Motherboard Express uATX
 * V2M-P1
 *
 * HBI-0190D
 *
 * RS1 memory map ("ARM Cortex-A Series memory map" in the board's
 * Technical Reference Manual)
 *
 * WARNING! The hardware described in this file is independent from the
 * original variant (vexpress-v2m.dtsi), but there is a strong
 * correspondence between the two configurations.
 *
 * TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
 * CHANGES TO vexpress-v2m.dtsi!
 */

/ {
	aliases {
		arm,v2m_timer = &v2m_timer01;
	};

	motherboard {
		compatible = "simple-bus";
		arm,vexpress,site = <0>;
		arm,v2m-memory-map = "rs1";
		#address-cells = <2>; /* SMB chipselect number and offset */
		#size-cells = <1>;
		#interrupt-cells = <1>;

		flash@0,00000000 {
			compatible = "arm,vexpress-flash", "cfi-flash";
			reg = <0 0x00000000 0x04000000>,
			      <4 0x00000000 0x04000000>;
			bank-width = <4>;
		};

		psram@1,00000000 {
			compatible = "arm,vexpress-psram", "mtd-ram";
			reg = <1 0x00000000 0x02000000>;
			bank-width = <4>;
		};

		vram@2,00000000 {
			compatible = "arm,vexpress-vram";
			reg = <2 0x00000000 0x00800000>;
		};

		ethernet@2,02000000 {
			compatible = "smsc,lan9118", "smsc,lan9115";
			reg = <2 0x02000000 0x10000>;
			interrupts = <15>;
			phy-mode = "mii";
			reg-io-width = <4>;
			smsc,irq-active-high;
			smsc,irq-push-pull;
			vdd33a-supply = <&v2m_fixed_3v3>;
			vddvario-supply = <&v2m_fixed_3v3>;
		};

		usb@2,03000000 {
			compatible = "nxp,usb-isp1761";
			reg = <2 0x03000000 0x20000>;
			interrupts = <16>;
			port1-otg;
		};

		iofpga@3,00000000 {
			compatible = "arm,amba-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 3 0 0x200000>;

			v2m_sysreg: sysreg@010000 {
				compatible = "arm,vexpress-sysreg";
				reg = <0x010000 0x1000>;
				gpio-controller;
				#gpio-cells = <2>;
			};

			v2m_sysctl: sysctl@020000 {
				compatible = "arm,sp810", "arm,primecell";
				reg = <0x020000 0x1000>;
				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
				clock-names = "refclk", "timclk", "apb_pclk";
				#clock-cells = <1>;
				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
			};

			/* PCI-E I2C bus */
			v2m_i2c_pcie: i2c@030000 {
				compatible = "arm,versatile-i2c";
				reg = <0x030000 0x1000>;

				#address-cells = <1>;
				#size-cells = <0>;

				pcie-switch@60 {
					compatible = "idt,89hpes32h8";
					reg = <0x60>;
				};
			};

			aaci@040000 {
				compatible = "arm,pl041", "arm,primecell";
				reg = <0x040000 0x1000>;
				interrupts = <11>;
				clocks = <&smbclk>;
				clock-names = "apb_pclk";
			};

			mmci@050000 {
				compatible = "arm,pl180", "arm,primecell";
				reg = <0x050000 0x1000>;
				interrupts = <9 10>;
				cd-gpios = <&v2m_sysreg 0 0>;
				wp-gpios = <&v2m_sysreg 1 0>;
				max-frequency = <12000000>;
				vmmc-supply = <&v2m_fixed_3v3>;
				clocks = <&v2m_clk24mhz>, <&smbclk>;
				clock-names = "mclk", "apb_pclk";
			};

			kmi@060000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x060000 0x1000>;
				interrupts = <12>;
				clocks = <&v2m_clk24mhz>, <&smbclk>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};

			kmi@070000 {
				compatible = "arm,pl050", "arm,primecell";
				reg = <0x070000 0x1000>;
				interrupts = <13>;
				clocks = <&v2m_clk24mhz>, <&smbclk>;
				clock-names = "KMIREFCLK", "apb_pclk";
			};

			v2m_serial0: uart@090000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x090000 0x1000>;
				interrupts = <5>;
				clocks = <&v2m_oscclk2>, <&smbclk>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial1: uart@0a0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0a0000 0x1000>;
				interrupts = <6>;
				clocks = <&v2m_oscclk2>, <&smbclk>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial2: uart@0b0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0b0000 0x1000>;
				interrupts = <7>;
				clocks = <&v2m_oscclk2>, <&smbclk>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial3: uart@0c0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0c0000 0x1000>;
				interrupts = <8>;
				clocks = <&v2m_oscclk2>, <&smbclk>;
				clock-names = "uartclk", "apb_pclk";
			};

			wdt@0f0000 {
				compatible = "arm,sp805", "arm,primecell";
				reg = <0x0f0000 0x1000>;
				interrupts = <0>;
				clocks = <&v2m_refclk32khz>, <&smbclk>;
				clock-names = "wdogclk", "apb_pclk";
			};

			v2m_timer01: timer@110000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x110000 0x1000>;
				interrupts = <2>;
				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
				clock-names = "timclken1", "timclken2", "apb_pclk";
			};

			v2m_timer23: timer@120000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x120000 0x1000>;
				interrupts = <3>;
				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
				clock-names = "timclken1", "timclken2", "apb_pclk";
			};

			/* DVI I2C bus */
			v2m_i2c_dvi: i2c@160000 {
				compatible = "arm,versatile-i2c";
				reg = <0x160000 0x1000>;

				#address-cells = <1>;
				#size-cells = <0>;

				dvi-transmitter@39 {
					compatible = "sil,sii9022-tpi", "sil,sii9022";
					reg = <0x39>;
				};

				dvi-transmitter@60 {
					compatible = "sil,sii9022-cpi", "sil,sii9022";
					reg = <0x60>;
				};
			};

			rtc@170000 {
				compatible = "arm,pl031", "arm,primecell";
				reg = <0x170000 0x1000>;
				interrupts = <4>;
				clocks = <&smbclk>;
				clock-names = "apb_pclk";
			};

			compact-flash@1a0000 {
				compatible = "arm,vexpress-cf", "ata-generic";
				reg = <0x1a0000 0x100
				       0x1a0100 0xf00>;
				reg-shift = <2>;
			};

			clcd@1f0000 {
				compatible = "arm,pl111", "arm,primecell";
				reg = <0x1f0000 0x1000>;
				interrupts = <14>;
				clocks = <&v2m_oscclk1>, <&smbclk>;
				clock-names = "clcdclk", "apb_pclk";
			};
		};

		v2m_fixed_3v3: fixedregulator@0 {
			compatible = "regulator-fixed";
			regulator-name = "3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};

		v2m_clk24mhz: clk24mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
			clock-output-names = "v2m:clk24mhz";
		};

		v2m_refclk1mhz: refclk1mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000>;
			clock-output-names = "v2m:refclk1mhz";
		};

		v2m_refclk32khz: refclk32khz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "v2m:refclk32khz";
		};

		mcc {
			compatible = "arm,vexpress,config-bus";
			arm,vexpress,config-bridge = <&v2m_sysreg>;

			osc@0 {
				/* MCC static memory clock */
				compatible = "arm,vexpress-osc";
				arm,vexpress-sysreg,func = <1 0>;
				freq-range = <25000000 60000000>;
				#clock-cells = <0>;
				clock-output-names = "v2m:oscclk0";
			};

			v2m_oscclk1: osc@1 {
				/* CLCD clock */
				compatible = "arm,vexpress-osc";
				arm,vexpress-sysreg,func = <1 1>;
				freq-range = <23750000 63500000>;
				#clock-cells = <0>;
				clock-output-names = "v2m:oscclk1";
			};

			v2m_oscclk2: osc@2 {
				/* IO FPGA peripheral clock */
				compatible = "arm,vexpress-osc";
				arm,vexpress-sysreg,func = <1 2>;
				freq-range = <24000000 24000000>;
				#clock-cells = <0>;
				clock-output-names = "v2m:oscclk2";
			};

			volt@0 {
				/* Logic level voltage */
				compatible = "arm,vexpress-volt";
				arm,vexpress-sysreg,func = <2 0>;
				regulator-name = "VIO";
				regulator-always-on;
				label = "VIO";
			};

			temp@0 {
				/* MCC internal operating temperature */
				compatible = "arm,vexpress-temp";
				arm,vexpress-sysreg,func = <4 0>;
				label = "MCC";
			};

			reset@0 {
				compatible = "arm,vexpress-reset";
				arm,vexpress-sysreg,func = <5 0>;
			};

			muxfpga@0 {
				compatible = "arm,vexpress-muxfpga";
				arm,vexpress-sysreg,func = <7 0>;
			};

			shutdown@0 {
				compatible = "arm,vexpress-shutdown";
				arm,vexpress-sysreg,func = <8 0>;
			};

			reboot@0 {
				compatible = "arm,vexpress-reboot";
				arm,vexpress-sysreg,func = <9 0>;
			};

			dvimode@0 {
				compatible = "arm,vexpress-dvimode";
				arm,vexpress-sysreg,func = <11 0>;
			};
		};
	};
};
Commit	Line	Data
6a371956 PM	1	/*
	2	* ARM Ltd. Versatile Express
	3	*
	4	* Motherboard Express uATX
	5	* V2M-P1
	6	*
	7	* HBI-0190D
	8	*
	9	* RS1 memory map ("ARM Cortex-A Series memory map" in the board's
	10	* Technical Reference Manual)
	11	*
	12	* WARNING! The hardware described in this file is independent from the
	13	* original variant (vexpress-v2m.dtsi), but there is a strong
	14	* correspondence between the two configurations.
	15	*
	16	* TAKE CARE WHEN MAINTAINING THIS FILE TO PROPAGATE ANY RELEVANT
	17	* CHANGES TO vexpress-v2m.dtsi!
	18	*/
	19
	20	/ {
	21	aliases {
	22	arm,v2m_timer = &v2m_timer01;
	23	};
	24
	25	motherboard {
	26	compatible = "simple-bus";
842839a3	27	arm,vexpress,site = <0>;
6a371956 PM	28	arm,v2m-memory-map = "rs1";
	29	#address-cells = <2>; /* SMB chipselect number and offset */
	30	#size-cells = <1>;
	31	#interrupt-cells = <1>;
	32
	33	flash@0,00000000 {
	34	compatible = "arm,vexpress-flash", "cfi-flash";
	35	reg = <0 0x00000000 0x04000000>,
	36	<4 0x00000000 0x04000000>;
	37	bank-width = <4>;
	38	};
	39
	40	psram@1,00000000 {
	41	compatible = "arm,vexpress-psram", "mtd-ram";
	42	reg = <1 0x00000000 0x02000000>;
	43	bank-width = <4>;
	44	};
	45
	46	vram@2,00000000 {
	47	compatible = "arm,vexpress-vram";
	48	reg = <2 0x00000000 0x00800000>;
	49	};
	50
	51	ethernet@2,02000000 {
	52	compatible = "smsc,lan9118", "smsc,lan9115";
	53	reg = <2 0x02000000 0x10000>;
	54	interrupts = <15>;
	55	phy-mode = "mii";
	56	reg-io-width = <4>;
	57	smsc,irq-active-high;
	58	smsc,irq-push-pull;
b2a54ff0 PM	59	vdd33a-supply = <&v2m_fixed_3v3>;
b2a54ff0 PM	60	vddvario-supply = <&v2m_fixed_3v3>;
6a371956 PM	61	};
	62
	63	usb@2,03000000 {
	64	compatible = "nxp,usb-isp1761";
	65	reg = <2 0x03000000 0x20000>;
	66	interrupts = <16>;
	67	port1-otg;
	68	};
	69
	70	iofpga@3,00000000 {
	71	compatible = "arm,amba-bus", "simple-bus";
	72	#address-cells = <1>;
	73	#size-cells = <1>;
	74	ranges = <0 3 0 0x200000>;
	75
842839a3	76	v2m_sysreg: sysreg@010000 {
6a371956 PM	77	compatible = "arm,vexpress-sysreg";
6a371956 PM	78	reg = <0x010000 0x1000>;
842839a3 PM	79	gpio-controller;
842839a3 PM	80	#gpio-cells = <2>;
6a371956 PM	81	};
6a371956 PM	82
842839a3	83	v2m_sysctl: sysctl@020000 {
6a371956 PM	84	compatible = "arm,sp810", "arm,primecell";
6a371956 PM	85	reg = <0x020000 0x1000>;
842839a3 PM	86	clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&smbclk>;
	87	clock-names = "refclk", "timclk", "apb_pclk";
	88	#clock-cells = <1>;
	89	clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
6a371956 PM	90	};
	91
	92	/* PCI-E I2C bus */
	93	v2m_i2c_pcie: i2c@030000 {
	94	compatible = "arm,versatile-i2c";
	95	reg = <0x030000 0x1000>;
	96
	97	#address-cells = <1>;
	98	#size-cells = <0>;
	99
	100	pcie-switch@60 {
	101	compatible = "idt,89hpes32h8";
	102	reg = <0x60>;
	103	};
	104	};
	105
	106	aaci@040000 {
	107	compatible = "arm,pl041", "arm,primecell";
	108	reg = <0x040000 0x1000>;
	109	interrupts = <11>;
842839a3 PM	110	clocks = <&smbclk>;
842839a3 PM	111	clock-names = "apb_pclk";
6a371956 PM	112	};
	113
	114	mmci@050000 {
	115	compatible = "arm,pl180", "arm,primecell";
	116	reg = <0x050000 0x1000>;
	117	interrupts = <9 10>;
842839a3 PM	118	cd-gpios = <&v2m_sysreg 0 0>;
	119	wp-gpios = <&v2m_sysreg 1 0>;
	120	max-frequency = <12000000>;
	121	vmmc-supply = <&v2m_fixed_3v3>;
	122	clocks = <&v2m_clk24mhz>, <&smbclk>;
	123	clock-names = "mclk", "apb_pclk";
6a371956 PM	124	};
	125
	126	kmi@060000 {
	127	compatible = "arm,pl050", "arm,primecell";
	128	reg = <0x060000 0x1000>;
	129	interrupts = <12>;
842839a3 PM	130	clocks = <&v2m_clk24mhz>, <&smbclk>;
842839a3 PM	131	clock-names = "KMIREFCLK", "apb_pclk";
6a371956 PM	132	};
	133
	134	kmi@070000 {
	135	compatible = "arm,pl050", "arm,primecell";
	136	reg = <0x070000 0x1000>;
	137	interrupts = <13>;
842839a3 PM	138	clocks = <&v2m_clk24mhz>, <&smbclk>;
842839a3 PM	139	clock-names = "KMIREFCLK", "apb_pclk";
6a371956 PM	140	};
	141
	142	v2m_serial0: uart@090000 {
	143	compatible = "arm,pl011", "arm,primecell";
	144	reg = <0x090000 0x1000>;
	145	interrupts = <5>;
842839a3 PM	146	clocks = <&v2m_oscclk2>, <&smbclk>;
842839a3 PM	147	clock-names = "uartclk", "apb_pclk";
6a371956 PM	148	};
	149
	150	v2m_serial1: uart@0a0000 {
	151	compatible = "arm,pl011", "arm,primecell";
	152	reg = <0x0a0000 0x1000>;
	153	interrupts = <6>;
842839a3 PM	154	clocks = <&v2m_oscclk2>, <&smbclk>;
842839a3 PM	155	clock-names = "uartclk", "apb_pclk";
6a371956 PM	156	};
	157
	158	v2m_serial2: uart@0b0000 {
	159	compatible = "arm,pl011", "arm,primecell";
	160	reg = <0x0b0000 0x1000>;
	161	interrupts = <7>;
842839a3 PM	162	clocks = <&v2m_oscclk2>, <&smbclk>;
842839a3 PM	163	clock-names = "uartclk", "apb_pclk";
6a371956 PM	164	};
	165
	166	v2m_serial3: uart@0c0000 {
	167	compatible = "arm,pl011", "arm,primecell";
	168	reg = <0x0c0000 0x1000>;
	169	interrupts = <8>;
842839a3 PM	170	clocks = <&v2m_oscclk2>, <&smbclk>;
842839a3 PM	171	clock-names = "uartclk", "apb_pclk";
6a371956 PM	172	};
	173
	174	wdt@0f0000 {
	175	compatible = "arm,sp805", "arm,primecell";
	176	reg = <0x0f0000 0x1000>;
	177	interrupts = <0>;
842839a3 PM	178	clocks = <&v2m_refclk32khz>, <&smbclk>;
842839a3 PM	179	clock-names = "wdogclk", "apb_pclk";
6a371956 PM	180	};
	181
	182	v2m_timer01: timer@110000 {
	183	compatible = "arm,sp804", "arm,primecell";
	184	reg = <0x110000 0x1000>;
	185	interrupts = <2>;
842839a3 PM	186	clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&smbclk>;
842839a3 PM	187	clock-names = "timclken1", "timclken2", "apb_pclk";
6a371956 PM	188	};
	189
	190	v2m_timer23: timer@120000 {
	191	compatible = "arm,sp804", "arm,primecell";
	192	reg = <0x120000 0x1000>;
b7541a95	193	interrupts = <3>;
842839a3 PM	194	clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&smbclk>;
842839a3 PM	195	clock-names = "timclken1", "timclken2", "apb_pclk";
6a371956 PM	196	};
	197
	198	/* DVI I2C bus */
	199	v2m_i2c_dvi: i2c@160000 {
	200	compatible = "arm,versatile-i2c";
	201	reg = <0x160000 0x1000>;
	202
	203	#address-cells = <1>;
	204	#size-cells = <0>;
	205
	206	dvi-transmitter@39 {
	207	compatible = "sil,sii9022-tpi", "sil,sii9022";
	208	reg = <0x39>;
	209	};
	210
	211	dvi-transmitter@60 {
	212	compatible = "sil,sii9022-cpi", "sil,sii9022";
	213	reg = <0x60>;
	214	};
	215	};
	216
	217	rtc@170000 {
	218	compatible = "arm,pl031", "arm,primecell";
	219	reg = <0x170000 0x1000>;
	220	interrupts = <4>;
842839a3 PM	221	clocks = <&smbclk>;
842839a3 PM	222	clock-names = "apb_pclk";
6a371956 PM	223	};
	224
	225	compact-flash@1a0000 {
	226	compatible = "arm,vexpress-cf", "ata-generic";
	227	reg = <0x1a0000 0x100
	228	0x1a0100 0xf00>;
	229	reg-shift = <2>;
	230	};
	231
	232	clcd@1f0000 {
	233	compatible = "arm,pl111", "arm,primecell";
	234	reg = <0x1f0000 0x1000>;
	235	interrupts = <14>;
842839a3 PM	236	clocks = <&v2m_oscclk1>, <&smbclk>;
842839a3 PM	237	clock-names = "clcdclk", "apb_pclk";
6a371956 PM	238	};
6a371956 PM	239	};
b2a54ff0 PM	240
	241	v2m_fixed_3v3: fixedregulator@0 {
	242	compatible = "regulator-fixed";
	243	regulator-name = "3V3";
	244	regulator-min-microvolt = <3300000>;
	245	regulator-max-microvolt = <3300000>;
	246	regulator-always-on;
	247	};
842839a3 PM	248
	249	v2m_clk24mhz: clk24mhz {
	250	compatible = "fixed-clock";
	251	#clock-cells = <0>;
	252	clock-frequency = <24000000>;
	253	clock-output-names = "v2m:clk24mhz";
	254	};
	255
	256	v2m_refclk1mhz: refclk1mhz {
	257	compatible = "fixed-clock";
	258	#clock-cells = <0>;
	259	clock-frequency = <1000000>;
	260	clock-output-names = "v2m:refclk1mhz";
	261	};
	262
	263	v2m_refclk32khz: refclk32khz {
	264	compatible = "fixed-clock";
	265	#clock-cells = <0>;
	266	clock-frequency = <32768>;
	267	clock-output-names = "v2m:refclk32khz";
	268	};
	269
	270	mcc {
	271	compatible = "arm,vexpress,config-bus";
	272	arm,vexpress,config-bridge = <&v2m_sysreg>;
	273
	274	osc@0 {
	275	/* MCC static memory clock */
	276	compatible = "arm,vexpress-osc";
	277	arm,vexpress-sysreg,func = <1 0>;
	278	freq-range = <25000000 60000000>;
	279	#clock-cells = <0>;
	280	clock-output-names = "v2m:oscclk0";
	281	};
	282
	283	v2m_oscclk1: osc@1 {
	284	/* CLCD clock */
	285	compatible = "arm,vexpress-osc";
	286	arm,vexpress-sysreg,func = <1 1>;
	287	freq-range = <23750000 63500000>;
	288	#clock-cells = <0>;
	289	clock-output-names = "v2m:oscclk1";
	290	};
	291
	292	v2m_oscclk2: osc@2 {
	293	/* IO FPGA peripheral clock */
	294	compatible = "arm,vexpress-osc";
	295	arm,vexpress-sysreg,func = <1 2>;
	296	freq-range = <24000000 24000000>;
	297	#clock-cells = <0>;
	298	clock-output-names = "v2m:oscclk2";
	299	};
	300
	301	volt@0 {
	302	/* Logic level voltage */
	303	compatible = "arm,vexpress-volt";
	304	arm,vexpress-sysreg,func = <2 0>;
	305	regulator-name = "VIO";
	306	regulator-always-on;
	307	label = "VIO";
	308	};
	309
	310	temp@0 {
	311	/* MCC internal operating temperature */
312	compatible = "arm,vexpress-temp";
313	arm,vexpress-sysreg,func = <4 0>;
314	label = "MCC";
315	};
316
317	reset@0 {
318	compatible = "arm,vexpress-reset";
319	arm,vexpress-sysreg,func = <5 0>;
320	};
321
322	muxfpga@0 {
323	compatible = "arm,vexpress-muxfpga";
324	arm,vexpress-sysreg,func = <7 0>;
325	};
326
327	shutdown@0 {
328	compatible = "arm,vexpress-shutdown";
329	arm,vexpress-sysreg,func = <8 0>;
330	};
331
332	reboot@0 {
333	compatible = "arm,vexpress-reboot";
334	arm,vexpress-sysreg,func = <9 0>;
335	};
336
337	dvimode@0 {
338	compatible = "arm,vexpress-dvimode";
339	arm,vexpress-sysreg,func = <11 0>;
340	};
341	};
6a371956 PM	342	};
6a371956 PM	343	};