[deliverable/linux.git] / arch / arm / boot / dts / vf-colibri.dtsi

/*
 * Copyright 2014 Toradex AG
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 *  a) This file is free software; you can redistribute it and/or
 *     modify it under the terms of the GNU General Public License
 *     version 2 as published by the Free Software Foundation.
 *
 *     This file is distributed in the hope that it will be useful
 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *     GNU General Public License for more details.
 *
 * Or, alternatively
 *
 *  b) Permission is hereby granted, free of charge, to any person
 *     obtaining a copy of this software and associated documentation
 *     files (the "Software"), to deal in the Software without
 *     restriction, including without limitation the rights to use
 *     copy, modify, merge, publish, distribute, sublicense, and/or
 *     sell copies of the Software, and to permit persons to whom the
 *     Software is furnished to do so, subject to the following
 *     conditions:
 *
 *     The above copyright notice and this permission notice shall be
 *     included in all copies or substantial portions of the Software.
 *
 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 *     OTHER DEALINGS IN THE SOFTWARE.
 */

/ {
	bl: backlight {
		compatible = "pwm-backlight";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_gpio_bl_on>;
		pwms = <&pwm0 0 5000000 0>;
		enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
		status = "disabled";
	};
};

&adc0 {
	status = "okay";
};

&adc1 {
	status = "okay";
};

&can0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan0>;
	status = "disabled";
};

&can1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_flexcan1>;
	status = "disabled";
};

&clks {
	assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
			  <&clks VF610_CLK_ENET_TS_SEL>;
	assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
				 <&clks VF610_CLK_ENET_50M>;
};

&dspi1 {
	bus-num = <1>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi1>;
};

&edma0 {
	status = "okay";
};

&esdhc1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_esdhc1>;
	bus-width = <4>;
	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
};

&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
};

&i2c0 {
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
};

&nfc {
	assigned-clocks = <&clks VF610_CLK_NFC>;
	assigned-clock-rates = <33000000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_nfc>;
	status = "okay";

	nand@0 {
		compatible = "fsl,vf610-nfc-nandcs";
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <1>;
		nand-bus-width = <8>;
		nand-ecc-mode = "hw";
		nand-ecc-strength = <32>;
		nand-ecc-step-size = <2048>;
		nand-on-flash-bbt;
	};
};

&pwm0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm0>;
};

&pwm1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_pwm1>;
};

&uart0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart0>;
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
};

&uart2 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart2>;
};

&usbdev0 {
	disable-over-current;
	status = "okay";
};

&usbh1 {
	disable-over-current;
	status = "okay";
};

&usbmisc0 {
	status = "okay";
};

&usbmisc1 {
	status = "okay";
};

&usbphy0 {
	status = "okay";
};

&usbphy1 {
	status = "okay";
};

&iomuxc {
	vf610-colibri {
		pinctrl_flexcan0: can0grp {
			fsl,pins = <
				VF610_PAD_PTB14__CAN0_RX	0x31F1
				VF610_PAD_PTB15__CAN0_TX	0x31F2
			>;
		};

		pinctrl_flexcan1: can1grp {
			fsl,pins = <
				VF610_PAD_PTB16__CAN1_RX	0x31F1
				VF610_PAD_PTB17__CAN1_TX	0x31F2
			>;
		};

		pinctrl_gpio_ext: gpio_ext {
			fsl,pins = <
				VF610_PAD_PTD10__GPIO_89	0x22ed /* EXT_IO_0 */
				VF610_PAD_PTD9__GPIO_88		0x22ed /* EXT_IO_1 */
				VF610_PAD_PTD26__GPIO_68	0x22ed /* EXT_IO_2 */
			>;
		};

		pinctrl_dspi1: dspi1grp {
			fsl,pins = <
				VF610_PAD_PTD5__DSPI1_CS0		0x33e2
				VF610_PAD_PTD6__DSPI1_SIN		0x33e1
				VF610_PAD_PTD7__DSPI1_SOUT		0x33e2
				VF610_PAD_PTD8__DSPI1_SCK		0x33e2
			>;
		};

		pinctrl_esdhc1: esdhc1grp {
			fsl,pins = <
				VF610_PAD_PTA24__ESDHC1_CLK	0x31ef
				VF610_PAD_PTA25__ESDHC1_CMD	0x31ef
				VF610_PAD_PTA26__ESDHC1_DAT0	0x31ef
				VF610_PAD_PTA27__ESDHC1_DAT1	0x31ef
				VF610_PAD_PTA28__ESDHC1_DATA2	0x31ef
				VF610_PAD_PTA29__ESDHC1_DAT3	0x31ef
				VF610_PAD_PTB20__GPIO_42	0x219d
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				VF610_PAD_PTA6__RMII_CLKOUT		0x30d2
				VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
				VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
				VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
				VF610_PAD_PTC12__ENET_RMII1_RXD1	0x30d1
				VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
				VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
				VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
				VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
				VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
			>;
		};

		pinctrl_gpio_bl_on: gpio_bl_on {
			fsl,pins = <
				VF610_PAD_PTC0__GPIO_45		0x22ef
			>;
		};

		pinctrl_i2c0: i2c0grp {
			fsl,pins = <
				VF610_PAD_PTB14__I2C0_SCL		0x37ff
				VF610_PAD_PTB15__I2C0_SDA		0x37ff
			>;
		};

		pinctrl_nfc: nfcgrp {
			fsl,pins = <
				VF610_PAD_PTD23__NF_IO7		0x28df
				VF610_PAD_PTD22__NF_IO6		0x28df
				VF610_PAD_PTD21__NF_IO5		0x28df
				VF610_PAD_PTD20__NF_IO4		0x28df
				VF610_PAD_PTD19__NF_IO3		0x28df
				VF610_PAD_PTD18__NF_IO2		0x28df
				VF610_PAD_PTD17__NF_IO1		0x28df
				VF610_PAD_PTD16__NF_IO0		0x28df
				VF610_PAD_PTB24__NF_WE_B	0x28c2
				VF610_PAD_PTB25__NF_CE0_B	0x28c2
				VF610_PAD_PTB27__NF_RE_B	0x28c2
				VF610_PAD_PTC26__NF_RB_B	0x283d
				VF610_PAD_PTC27__NF_ALE		0x28c2
				VF610_PAD_PTC28__NF_CLE		0x28c2
			>;
		};

		pinctrl_pwm0: pwm0grp {
			fsl,pins = <
				VF610_PAD_PTB0__FTM0_CH0		0x1182
				VF610_PAD_PTB1__FTM0_CH1		0x1182
			>;
		};

		pinctrl_pwm1: pwm1grp {
			fsl,pins = <
				VF610_PAD_PTB8__FTM1_CH0		0x1182
				VF610_PAD_PTB9__FTM1_CH1		0x1182
			>;
		};

		pinctrl_uart0: uart0grp {
			fsl,pins = <
				VF610_PAD_PTB10__UART0_TX		0x21a2
				VF610_PAD_PTB11__UART0_RX		0x21a1
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				VF610_PAD_PTB4__UART1_TX		0x21a2
				VF610_PAD_PTB5__UART1_RX		0x21a1
			>;
		};

		pinctrl_uart2: uart2grp {
			fsl,pins = <
				VF610_PAD_PTD0__UART2_TX		0x21a2
				VF610_PAD_PTD1__UART2_RX		0x21a1
				VF610_PAD_PTD2__UART2_RTS		0x21a2
				VF610_PAD_PTD3__UART2_CTS		0x21a1
			>;
		};

		pinctrl_usbh1_reg: gpio_usb_vbus {
			fsl,pins = <
				VF610_PAD_PTD4__GPIO_83			0x22ed
			>;
		};
	};
};
Commit	Line	Data
e1bf86ac SA	1	/*
	2	* Copyright 2014 Toradex AG
	3	*
9f3440dd SA	4	* This file is dual-licensed: you can use it either under the terms
	5	* of the GPL or the X11 license, at your option. Note that this dual
	6	* licensing only applies to this file, and not this project as a
	7	* whole.
	8	*
	9	* a) This file is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* version 2 as published by the Free Software Foundation.
	12	*
	13	* This file is distributed in the hope that it will be useful
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* Or, alternatively
	19	*
	20	* b) Permission is hereby granted, free of charge, to any person
	21	* obtaining a copy of this software and associated documentation
	22	* files (the "Software"), to deal in the Software without
	23	* restriction, including without limitation the rights to use
	24	* copy, modify, merge, publish, distribute, sublicense, and/or
	25	* sell copies of the Software, and to permit persons to whom the
	26	* Software is furnished to do so, subject to the following
	27	* conditions:
	28	*
	29	* The above copyright notice and this permission notice shall be
	30	* included in all copies or substantial portions of the Software.
	31	*
	32	* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
	33	* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
	34	* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
	35	* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
	36	* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
	37	* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	38	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
	39	* OTHER DEALINGS IN THE SOFTWARE.
e1bf86ac SA	40	*/
	41
	42	/ {
	43	bl: backlight {
	44	compatible = "pwm-backlight";
b2e42446 BD	45	pinctrl-names = "default";
b2e42446 BD	46	pinctrl-0 = <&pinctrl_gpio_bl_on>;
e1bf86ac	47	pwms = <&pwm0 0 5000000 0>;
b2e42446	48	enable-gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>;
e1bf86ac SA	49	status = "disabled";
	50	};
	51	};
	52
	53	&adc0 {
	54	status = "okay";
	55	};
	56
	57	&adc1 {
	58	status = "okay";
	59	};
	60
2afa06cb SA	61	&can0 {
	62	pinctrl-names = "default";
	63	pinctrl-0 = <&pinctrl_flexcan0>;
	64	status = "disabled";
	65	};
	66
	67	&can1 {
	68	pinctrl-names = "default";
	69	pinctrl-0 = <&pinctrl_flexcan1>;
	70	status = "disabled";
	71	};
	72
5c35b778 SA	73	&clks {
	74	assigned-clocks = <&clks VF610_CLK_ENET_SEL>,
	75	<&clks VF610_CLK_ENET_TS_SEL>;
	76	assigned-clock-parents = <&clks VF610_CLK_ENET_50M>,
	77	<&clks VF610_CLK_ENET_50M>;
	78	};
	79
9fca0151 BD	80	&dspi1 {
	81	bus-num = <1>;
	82	pinctrl-names = "default";
	83	pinctrl-0 = <&pinctrl_dspi1>;
	84	};
	85
e1bf86ac SA	86	&edma0 {
	87	status = "okay";
	88	};
	89
	90	&esdhc1 {
	91	pinctrl-names = "default";
	92	pinctrl-0 = <&pinctrl_esdhc1>;
	93	bus-width = <4>;
76713954	94	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
e1bf86ac SA	95	};
	96
	97	&fec1 {
	98	phy-mode = "rmii";
	99	pinctrl-names = "default";
	100	pinctrl-0 = <&pinctrl_fec1>;
	101	};
	102
1ddeb484 BD	103	&i2c0 {
	104	clock-frequency = <400000>;
	105	pinctrl-names = "default";
	106	pinctrl-0 = <&pinctrl_i2c0>;
	107	};
	108
65425265 SA	109	&nfc {
	110	assigned-clocks = <&clks VF610_CLK_NFC>;
	111	assigned-clock-rates = <33000000>;
	112	pinctrl-names = "default";
	113	pinctrl-0 = <&pinctrl_nfc>;
	114	status = "okay";
	115
	116	nand@0 {
	117	compatible = "fsl,vf610-nfc-nandcs";
	118	reg = <0>;
	119	#address-cells = <1>;
	120	#size-cells = <1>;
	121	nand-bus-width = <8>;
	122	nand-ecc-mode = "hw";
	123	nand-ecc-strength = <32>;
	124	nand-ecc-step-size = <2048>;
	125	nand-on-flash-bbt;
	126	};
	127	};
	128
e1bf86ac SA	129	&pwm0 {
	130	pinctrl-names = "default";
	131	pinctrl-0 = <&pinctrl_pwm0>;
	132	};
	133
	134	&pwm1 {
	135	pinctrl-names = "default";
	136	pinctrl-0 = <&pinctrl_pwm1>;
	137	};
	138
	139	&uart0 {
	140	pinctrl-names = "default";
	141	pinctrl-0 = <&pinctrl_uart0>;
	142	};
	143
	144	&uart1 {
	145	pinctrl-names = "default";
	146	pinctrl-0 = <&pinctrl_uart1>;
	147	};
	148
	149	&uart2 {
	150	pinctrl-names = "default";
	151	pinctrl-0 = <&pinctrl_uart2>;
	152	};
	153
	154	&usbdev0 {
	155	disable-over-current;
	156	status = "okay";
	157	};
	158
	159	&usbh1 {
	160	disable-over-current;
	161	status = "okay";
	162	};
	163
ac039cd9 SA	164	&usbmisc0 {
	165	status = "okay";
	166	};
	167
	168	&usbmisc1 {
	169	status = "okay";
	170	};
	171
	172	&usbphy0 {
	173	status = "okay";
	174	};
	175
	176	&usbphy1 {
	177	status = "okay";
	178	};
	179
e1bf86ac SA	180	&iomuxc {
e1bf86ac SA	181	vf610-colibri {
2afa06cb SA	182	pinctrl_flexcan0: can0grp {
	183	fsl,pins = <
	184	VF610_PAD_PTB14__CAN0_RX 0x31F1
	185	VF610_PAD_PTB15__CAN0_TX 0x31F2
	186	>;
	187	};
	188
	189	pinctrl_flexcan1: can1grp {
	190	fsl,pins = <
	191	VF610_PAD_PTB16__CAN1_RX 0x31F1
	192	VF610_PAD_PTB17__CAN1_TX 0x31F2
	193	>;
	194	};
	195
2b36bda3 SA	196	pinctrl_gpio_ext: gpio_ext {
	197	fsl,pins = <
	198	VF610_PAD_PTD10__GPIO_89 0x22ed /* EXT_IO_0 */
	199	VF610_PAD_PTD9__GPIO_88 0x22ed /* EXT_IO_1 */
	200	VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */
	201	>;
	202	};
	203
9fca0151 BD	204	pinctrl_dspi1: dspi1grp {
	205	fsl,pins = <
	206	VF610_PAD_PTD5__DSPI1_CS0 0x33e2
	207	VF610_PAD_PTD6__DSPI1_SIN 0x33e1
	208	VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
	209	VF610_PAD_PTD8__DSPI1_SCK 0x33e2
	210	>;
	211	};
	212
e1bf86ac SA	213	pinctrl_esdhc1: esdhc1grp {
	214	fsl,pins = <
	215	VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
	216	VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
	217	VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
	218	VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
	219	VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
	220	VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
	221	VF610_PAD_PTB20__GPIO_42 0x219d
	222	>;
	223	};
	224
	225	pinctrl_fec1: fec1grp {
	226	fsl,pins = <
eddb00fa	227	VF610_PAD_PTA6__RMII_CLKOUT 0x30d2
e1bf86ac SA	228	VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
	229	VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
	230	VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
aa5fec2d	231	VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
e1bf86ac SA	232	VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
	233	VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
	234	VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
	235	VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
	236	VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
	237	>;
	238	};
	239
b2e42446 BD	240	pinctrl_gpio_bl_on: gpio_bl_on {
	241	fsl,pins = <
	242	VF610_PAD_PTC0__GPIO_45 0x22ef
	243	>;
	244	};
	245
1ddeb484 BD	246	pinctrl_i2c0: i2c0grp {
	247	fsl,pins = <
	248	VF610_PAD_PTB14__I2C0_SCL 0x37ff
	249	VF610_PAD_PTB15__I2C0_SDA 0x37ff
	250	>;
	251	};
	252
65425265 SA	253	pinctrl_nfc: nfcgrp {
	254	fsl,pins = <
	255	VF610_PAD_PTD23__NF_IO7 0x28df
	256	VF610_PAD_PTD22__NF_IO6 0x28df
	257	VF610_PAD_PTD21__NF_IO5 0x28df
	258	VF610_PAD_PTD20__NF_IO4 0x28df
	259	VF610_PAD_PTD19__NF_IO3 0x28df
	260	VF610_PAD_PTD18__NF_IO2 0x28df
	261	VF610_PAD_PTD17__NF_IO1 0x28df
	262	VF610_PAD_PTD16__NF_IO0 0x28df
	263	VF610_PAD_PTB24__NF_WE_B 0x28c2
	264	VF610_PAD_PTB25__NF_CE0_B 0x28c2
	265	VF610_PAD_PTB27__NF_RE_B 0x28c2
	266	VF610_PAD_PTC26__NF_RB_B 0x283d
	267	VF610_PAD_PTC27__NF_ALE 0x28c2
	268	VF610_PAD_PTC28__NF_CLE 0x28c2
	269	>;
	270	};
	271
e1bf86ac SA	272	pinctrl_pwm0: pwm0grp {
	273	fsl,pins = <
	274	VF610_PAD_PTB0__FTM0_CH0 0x1182
	275	VF610_PAD_PTB1__FTM0_CH1 0x1182
	276	>;
	277	};
	278
	279	pinctrl_pwm1: pwm1grp {
	280	fsl,pins = <
	281	VF610_PAD_PTB8__FTM1_CH0 0x1182
	282	VF610_PAD_PTB9__FTM1_CH1 0x1182
	283	>;
	284	};
	285
	286	pinctrl_uart0: uart0grp {
	287	fsl,pins = <
	288	VF610_PAD_PTB10__UART0_TX 0x21a2
	289	VF610_PAD_PTB11__UART0_RX 0x21a1
	290	>;
	291	};
	292
	293	pinctrl_uart1: uart1grp {
	294	fsl,pins = <
	295	VF610_PAD_PTB4__UART1_TX 0x21a2
	296	VF610_PAD_PTB5__UART1_RX 0x21a1
	297	>;
	298	};
	299
	300	pinctrl_uart2: uart2grp {
	301	fsl,pins = <
	302	VF610_PAD_PTD0__UART2_TX 0x21a2
	303	VF610_PAD_PTD1__UART2_RX 0x21a1
	304	VF610_PAD_PTD2__UART2_RTS 0x21a2
	305	VF610_PAD_PTD3__UART2_CTS 0x21a1
	306	>;
	307	};
505251e5 SA	308
	309	pinctrl_usbh1_reg: gpio_usb_vbus {
	310	fsl,pins = <
	311	VF610_PAD_PTD4__GPIO_83 0x22ed
	312	>;
	313	};
e1bf86ac SA	314	};
e1bf86ac SA	315	};