[deliverable/linux.git] / arch / arm / boot / dts / vf610-twr.dts

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

/dts-v1/;
#include "vf610.dtsi"

/ {
	model = "VF610 Tower Board";
	compatible = "fsl,vf610-twr", "fsl,vf610";

	chosen {
		bootargs = "console=ttyLP1,115200";
	};

	memory {
		reg = <0x80000000 0x8000000>;
	};

	clocks {
		audio_ext {
			compatible = "fixed-clock";
			clock-frequency = <24576000>;
		};

		enet_ext {
			compatible = "fixed-clock";
			clock-frequency = <50000000>;
		};
	};

	regulators {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <0>;

		reg_3p3v: regulator@0 {
			compatible = "regulator-fixed";
			reg = <0>;
			regulator-name = "3P3V";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};
	};

	sound {
		compatible = "simple-audio-card";
		simple-audio-card,format = "i2s";
		simple-audio-card,widgets =
			"Microphone", "Microphone Jack",
			"Headphone", "Headphone Jack",
			"Speaker", "Speaker Ext",
			"Line", "Line In Jack";
		simple-audio-card,routing =
			"MIC_IN", "Microphone Jack",
			"Microphone Jack", "Mic Bias",
			"LINE_IN", "Line In Jack",
			"Headphone Jack", "HP_OUT",
			"Speaker Ext", "LINE_OUT";

		simple-audio-card,cpu {
			sound-dai = <&sai2>;
			master-clkdir-out;
			frame-master;
			bitclock-master;
		};

		simple-audio-card,codec {
			sound-dai = <&codec>;
			frame-master;
			bitclock-master;
		};
	};
};

&dspi0 {
	bus-num = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_dspi0>;
	status = "okay";

	sflash: at26df081a@0 {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "atmel,at26df081a";
		spi-max-frequency = <16000000>;
		spi-cpol;
		spi-cpha;
		reg = <0>;
	};
};

&fec0 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec0>;
	status = "okay";
};

&fec1 {
	phy-mode = "rmii";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_fec1>;
	status = "okay";
};

&i2c0 {
	clock-frequency = <100000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0>;
	status = "okay";

	codec: sgtl5000@0a {
	       #sound-dai-cells = <0>;
	       compatible = "fsl,sgtl5000";
	       reg = <0x0a>;
	       VDDA-supply = <&reg_3p3v>;
	       VDDIO-supply = <&reg_3p3v>;
	       clocks = <&clks VF610_CLK_SAI2>;
       };
};

&iomuxc {
	vf610-twr {
		pinctrl_dspi0: dspi0grp {
			fsl,pins = <
				VF610_PAD_PTB19__DSPI0_CS0		0x1182
				VF610_PAD_PTB20__DSPI0_SIN		0x1181
				VF610_PAD_PTB21__DSPI0_SOUT		0x1182
				VF610_PAD_PTB22__DSPI0_SCK		0x1182
			>;
		};

		pinctrl_fec0: fec0grp {
			fsl,pins = <
				VF610_PAD_PTA6__RMII_CLKIN		0x30d1
				VF610_PAD_PTC0__ENET_RMII0_MDC		0x30d3
				VF610_PAD_PTC1__ENET_RMII0_MDIO		0x30d1
				VF610_PAD_PTC2__ENET_RMII0_CRS		0x30d1
				VF610_PAD_PTC3__ENET_RMII0_RXD1		0x30d1
				VF610_PAD_PTC4__ENET_RMII0_RXD0		0x30d1
				VF610_PAD_PTC5__ENET_RMII0_RXER		0x30d1
				VF610_PAD_PTC6__ENET_RMII0_TXD1		0x30d2
				VF610_PAD_PTC7__ENET_RMII0_TXD0		0x30d2
				VF610_PAD_PTC8__ENET_RMII0_TXEN		0x30d2
			>;
		};

		pinctrl_fec1: fec1grp {
			fsl,pins = <
				VF610_PAD_PTC9__ENET_RMII1_MDC		0x30d2
				VF610_PAD_PTC10__ENET_RMII1_MDIO	0x30d3
				VF610_PAD_PTC11__ENET_RMII1_CRS		0x30d1
				VF610_PAD_PTC12__ENET_RMII_RXD1		0x30d1
				VF610_PAD_PTC13__ENET_RMII1_RXD0	0x30d1
				VF610_PAD_PTC14__ENET_RMII1_RXER	0x30d1
				VF610_PAD_PTC15__ENET_RMII1_TXD1	0x30d2
				VF610_PAD_PTC16__ENET_RMII1_TXD0	0x30d2
				VF610_PAD_PTC17__ENET_RMII1_TXEN	0x30d2
			>;
		};

		pinctrl_i2c0: i2c0grp {
			fsl,pins = <
				VF610_PAD_PTB14__I2C0_SCL		0x30d3
				VF610_PAD_PTB15__I2C0_SDA		0x30d3
			>;
		};

		pinctrl_sai2: sai2grp {
			fsl,pins = <
				VF610_PAD_PTA16__SAI2_TX_BCLK		0x02ed
				VF610_PAD_PTA18__SAI2_TX_DATA		0x02ee
				VF610_PAD_PTA19__SAI2_TX_SYNC		0x02ed
				VF610_PAD_PTA21__SAI2_RX_BCLK		0x02ed
				VF610_PAD_PTA22__SAI2_RX_DATA		0x02ed
				VF610_PAD_PTA23__SAI2_RX_SYNC		0x02ed
				VF610_PAD_PTB18__EXT_AUDIO_MCLK		0x02ed
			>;
		};

		pinctrl_uart1: uart1grp {
			fsl,pins = <
				VF610_PAD_PTB4__UART1_TX		0x21a2
				VF610_PAD_PTB5__UART1_RX		0x21a1
			>;
		};
	};
};

&sai2 {
	#sound-dai-cells = <0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sai2>;
	status = "okay";
};

&uart1 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1>;
	status = "okay";
};
Commit	Line	Data
e77b74ee JL	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
	10	/dts-v1/;
	11	#include "vf610.dtsi"
	12
	13	/ {
	14	model = "VF610 Tower Board";
	15	compatible = "fsl,vf610-twr", "fsl,vf610";
	16
	17	chosen {
	18	bootargs = "console=ttyLP1,115200";
	19	};
	20
	21	memory {
	22	reg = <0x80000000 0x8000000>;
	23	};
	24
	25	clocks {
	26	audio_ext {
	27	compatible = "fixed-clock";
	28	clock-frequency = <24576000>;
	29	};
	30
	31	enet_ext {
	32	compatible = "fixed-clock";
	33	clock-frequency = <50000000>;
	34	};
	35	};
	36
c5d571e7 XL	37	regulators {
	38	compatible = "simple-bus";
	39	#address-cells = <1>;
	40	#size-cells = <0>;
	41
	42	reg_3p3v: regulator@0 {
	43	compatible = "regulator-fixed";
	44	reg = <0>;
	45	regulator-name = "3P3V";
	46	regulator-min-microvolt = <3300000>;
	47	regulator-max-microvolt = <3300000>;
	48	regulator-always-on;
	49	};
	50	};
8128c4f3 XL	51
	52	sound {
	53	compatible = "simple-audio-card";
	54	simple-audio-card,format = "i2s";
	55	simple-audio-card,widgets =
	56	"Microphone", "Microphone Jack",
	57	"Headphone", "Headphone Jack",
	58	"Speaker", "Speaker Ext",
	59	"Line", "Line In Jack";
	60	simple-audio-card,routing =
	61	"MIC_IN", "Microphone Jack",
	62	"Microphone Jack", "Mic Bias",
	63	"LINE_IN", "Line In Jack",
	64	"Headphone Jack", "HP_OUT",
	65	"Speaker Ext", "LINE_OUT";
	66
	67	simple-audio-card,cpu {
	68	sound-dai = <&sai2>;
	69	master-clkdir-out;
	70	frame-master;
	71	bitclock-master;
	72	};
	73
	74	simple-audio-card,codec {
	75	sound-dai = <&codec>;
	76	frame-master;
	77	bitclock-master;
	78	};
	79	};
e77b74ee JL	80	};
e77b74ee JL	81
dc03a50f CF	82	&dspi0 {
	83	bus-num = <0>;
	84	pinctrl-names = "default";
07ed1eed	85	pinctrl-0 = <&pinctrl_dspi0>;
dc03a50f CF	86	status = "okay";
	87
	88	sflash: at26df081a@0 {
	89	#address-cells = <1>;
	90	#size-cells = <1>;
	91	compatible = "atmel,at26df081a";
	92	spi-max-frequency = <16000000>;
	93	spi-cpol;
	94	spi-cpha;
	95	reg = <0>;
	96	};
	97	};
	98
e77b74ee JL	99	&fec0 {
	100	phy-mode = "rmii";
	101	pinctrl-names = "default";
07ed1eed	102	pinctrl-0 = <&pinctrl_fec0>;
e77b74ee JL	103	status = "okay";
	104	};
	105
	106	&fec1 {
	107	phy-mode = "rmii";
	108	pinctrl-names = "default";
07ed1eed	109	pinctrl-0 = <&pinctrl_fec1>;
e77b74ee JL	110	status = "okay";
	111	};
	112
d45393cd JL	113	&i2c0 {
	114	clock-frequency = <100000>;
	115	pinctrl-names = "default";
07ed1eed	116	pinctrl-0 = <&pinctrl_i2c0>;
d45393cd	117	status = "okay";
c5d571e7 XL	118
c5d571e7 XL	119	codec: sgtl5000@0a {
8128c4f3	120	#sound-dai-cells = <0>;
c5d571e7 XL	121	compatible = "fsl,sgtl5000";
	122	reg = <0x0a>;
	123	VDDA-supply = <&reg_3p3v>;
	124	VDDIO-supply = <&reg_3p3v>;
	125	clocks = <&clks VF610_CLK_SAI2>;
	126	};
d45393cd JL	127	};
d45393cd JL	128
07ed1eed SG	129	&iomuxc {
	130	vf610-twr {
	131	pinctrl_dspi0: dspi0grp {
	132	fsl,pins = <
	133	VF610_PAD_PTB19__DSPI0_CS0 0x1182
	134	VF610_PAD_PTB20__DSPI0_SIN 0x1181
	135	VF610_PAD_PTB21__DSPI0_SOUT 0x1182
	136	VF610_PAD_PTB22__DSPI0_SCK 0x1182
	137	>;
	138	};
	139
	140	pinctrl_fec0: fec0grp {
	141	fsl,pins = <
	142	VF610_PAD_PTA6__RMII_CLKIN 0x30d1
	143	VF610_PAD_PTC0__ENET_RMII0_MDC 0x30d3
	144	VF610_PAD_PTC1__ENET_RMII0_MDIO 0x30d1
	145	VF610_PAD_PTC2__ENET_RMII0_CRS 0x30d1
	146	VF610_PAD_PTC3__ENET_RMII0_RXD1 0x30d1
	147	VF610_PAD_PTC4__ENET_RMII0_RXD0 0x30d1
	148	VF610_PAD_PTC5__ENET_RMII0_RXER 0x30d1
	149	VF610_PAD_PTC6__ENET_RMII0_TXD1 0x30d2
	150	VF610_PAD_PTC7__ENET_RMII0_TXD0 0x30d2
	151	VF610_PAD_PTC8__ENET_RMII0_TXEN 0x30d2
	152	>;
	153	};
	154
	155	pinctrl_fec1: fec1grp {
	156	fsl,pins = <
	157	VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
	158	VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
	159	VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
	160	VF610_PAD_PTC12__ENET_RMII_RXD1 0x30d1
	161	VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
	162	VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
	163	VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
	164	VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
	165	VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
	166	>;
	167	};
	168
	169	pinctrl_i2c0: i2c0grp {
	170	fsl,pins = <
	171	VF610_PAD_PTB14__I2C0_SCL 0x30d3
	172	VF610_PAD_PTB15__I2C0_SDA 0x30d3
	173	>;
	174	};
	175
95b13b66 XL	176	pinctrl_sai2: sai2grp {
	177	fsl,pins = <
	178	VF610_PAD_PTA16__SAI2_TX_BCLK 0x02ed
	179	VF610_PAD_PTA18__SAI2_TX_DATA 0x02ee
	180	VF610_PAD_PTA19__SAI2_TX_SYNC 0x02ed
	181	VF610_PAD_PTA21__SAI2_RX_BCLK 0x02ed
	182	VF610_PAD_PTA22__SAI2_RX_DATA 0x02ed
	183	VF610_PAD_PTA23__SAI2_RX_SYNC 0x02ed
	184	VF610_PAD_PTB18__EXT_AUDIO_MCLK 0x02ed
	185	>;
	186	};
	187
07ed1eed SG	188	pinctrl_uart1: uart1grp {
	189	fsl,pins = <
	190	VF610_PAD_PTB4__UART1_TX 0x21a2
	191	VF610_PAD_PTB5__UART1_RX 0x21a1
	192	>;
	193	};
	194	};
	195	};
	196
95b13b66	197	&sai2 {
8128c4f3	198	#sound-dai-cells = <0>;
95b13b66 XL	199	pinctrl-names = "default";
	200	pinctrl-0 = <&pinctrl_sai2>;
	201	status = "okay";
	202	};
	203
e77b74ee JL	204	&uart1 {
e77b74ee JL	205	pinctrl-names = "default";
07ed1eed	206	pinctrl-0 = <&pinctrl_uart1>;
e77b74ee JL	207	status = "okay";
e77b74ee JL	208	};