[deliverable/linux.git] / arch / arm / boot / dts / vf610.dtsi

/*
 * Copyright 2013 Freescale Semiconductor, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 */

#include "skeleton.dtsi"
#include "vf610-pinfunc.h"
#include <dt-bindings/clock/vf610-clock.h>
#include <dt-bindings/interrupt-controller/irq.h>

/ {
	aliases {
		serial0 = &uart0;
		serial1 = &uart1;
		serial2 = &uart2;
		serial3 = &uart3;
		serial4 = &uart4;
		serial5 = &uart5;
		gpio0 = &gpio1;
		gpio1 = &gpio2;
		gpio2 = &gpio3;
		gpio3 = &gpio4;
		gpio4 = &gpio5;
	};

	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			compatible = "arm,cortex-a5";
			device_type = "cpu";
			reg = <0x0>;
			next-level-cache = <&L2>;
		};
	};

	clocks {
		#address-cells = <1>;
		#size-cells = <0>;

		sxosc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
		};

		fxosc {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
		};
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		interrupt-parent = <&intc>;
		ranges;

		aips0: aips-bus@40000000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			interrupt-parent = <&intc>;
			reg = <0x40000000 0x70000>;
			ranges;

			intc: interrupt-controller@40002000 {
				compatible = "arm,cortex-a9-gic";
				#interrupt-cells = <3>;
				interrupt-controller;
				reg = <0x40003000 0x1000>,
				      <0x40002100 0x100>;
			};

			L2: l2-cache@40006000 {
				compatible = "arm,pl310-cache";
				reg = <0x40006000 0x1000>;
				cache-unified;
				cache-level = <2>;
				arm,data-latency = <1 1 1>;
				arm,tag-latency = <2 2 2>;
			};

			edma0: dma-controller@40018000 {
				#dma-cells = <2>;
				compatible = "fsl,vf610-edma";
				reg = <0x40018000 0x2000>,
					<0x40024000 0x1000>,
					<0x40025000 0x1000>;
				interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
						<0 9 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "edma-tx", "edma-err";
				dma-channels = <32>;
				clock-names = "dmamux0", "dmamux1";
				clocks = <&clks VF610_CLK_DMAMUX0>,
					<&clks VF610_CLK_DMAMUX1>;
			};

			uart0: serial@40027000 {
				compatible = "fsl,vf610-lpuart";
				reg = <0x40027000 0x1000>;
				interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_UART0>;
				clock-names = "ipg";
				dmas = <&edma0 0 2>,
					<&edma0 0 3>;
				dma-names = "rx","tx";
				status = "disabled";
			};

			uart1: serial@40028000 {
				compatible = "fsl,vf610-lpuart";
				reg = <0x40028000 0x1000>;
				interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_UART1>;
				clock-names = "ipg";
				dmas = <&edma0 0 4>,
					<&edma0 0 5>;
				dma-names = "rx","tx";
				status = "disabled";
			};

			uart2: serial@40029000 {
				compatible = "fsl,vf610-lpuart";
				reg = <0x40029000 0x1000>;
				interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_UART2>;
				clock-names = "ipg";
				dmas = <&edma0 0 6>,
					<&edma0 0 7>;
				dma-names = "rx","tx";
				status = "disabled";
			};

			uart3: serial@4002a000 {
				compatible = "fsl,vf610-lpuart";
				reg = <0x4002a000 0x1000>;
				interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_UART3>;
				clock-names = "ipg";
				dmas = <&edma0 0 8>,
					<&edma0 0 9>;
				dma-names = "rx","tx";
				status = "disabled";
			};

			dspi0: dspi0@4002c000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-dspi";
				reg = <0x4002c000 0x1000>;
				interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_DSPI0>;
				clock-names = "dspi";
				spi-num-chipselects = <5>;
				status = "disabled";
			};

			sai2: sai@40031000 {
				compatible = "fsl,vf610-sai";
				reg = <0x40031000 0x1000>;
				interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_SAI2>;
				clock-names = "sai";
				dma-names = "tx", "rx";
				dmas = <&edma0 0 21>,
					<&edma0 0 20>;
				status = "disabled";
			};

			pit: pit@40037000 {
				compatible = "fsl,vf610-pit";
				reg = <0x40037000 0x1000>;
				interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_PIT>;
				clock-names = "pit";
			};

			adc0: adc@4003b000 {
				compatible = "fsl,vf610-adc";
				reg = <0x4003b000 0x1000>;
				interrupts = <0 53 0x04>;
				clocks = <&clks VF610_CLK_ADC0>;
				clock-names = "adc";
				status = "disabled";
			};

			wdog@4003e000 {
				compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
				reg = <0x4003e000 0x1000>;
				clocks = <&clks VF610_CLK_WDT>;
				clock-names = "wdog";
			};

			qspi0: quadspi@40044000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-qspi";
				reg = <0x40044000 0x1000>;
				interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_QSPI0_EN>,
					<&clks VF610_CLK_QSPI0>;
				clock-names = "qspi_en", "qspi";
				status = "disabled";
			};

			iomuxc: iomuxc@40048000 {
				compatible = "fsl,vf610-iomuxc";
				reg = <0x40048000 0x1000>;
				#gpio-range-cells = <3>;
			};

			gpio1: gpio@40049000 {
				compatible = "fsl,vf610-gpio";
				reg = <0x40049000 0x1000 0x400ff000 0x40>;
				interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 0 32>;
			};

			gpio2: gpio@4004a000 {
				compatible = "fsl,vf610-gpio";
				reg = <0x4004a000 0x1000 0x400ff040 0x40>;
				interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 32 32>;
			};

			gpio3: gpio@4004b000 {
				compatible = "fsl,vf610-gpio";
				reg = <0x4004b000 0x1000 0x400ff080 0x40>;
				interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 64 32>;
			};

			gpio4: gpio@4004c000 {
				compatible = "fsl,vf610-gpio";
				reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
				interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 96 32>;
			};

			gpio5: gpio@4004d000 {
				compatible = "fsl,vf610-gpio";
				reg = <0x4004d000 0x1000 0x400ff100 0x40>;
				interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
				gpio-controller;
				#gpio-cells = <2>;
				interrupt-controller;
				#interrupt-cells = <2>;
				gpio-ranges = <&iomuxc 0 128 7>;
			};

			anatop@40050000 {
				compatible = "fsl,vf610-anatop";
				reg = <0x40050000 0x1000>;
			};

			i2c0: i2c@40066000 {
				#address-cells = <1>;
				#size-cells = <0>;
				compatible = "fsl,vf610-i2c";
				reg = <0x40066000 0x1000>;
				interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_I2C0>;
				clock-names = "ipg";
				dmas = <&edma0 0 50>,
					<&edma0 0 51>;
				dma-names = "rx","tx";
				status = "disabled";
			};

			clks: ccm@4006b000 {
				compatible = "fsl,vf610-ccm";
				reg = <0x4006b000 0x1000>;
				#clock-cells = <1>;
			};
		};

		aips1: aips-bus@40080000 {
			compatible = "fsl,aips-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			reg = <0x40080000 0x80000>;
			ranges;

			edma1: dma-controller@40098000 {
				#dma-cells = <2>;
				compatible = "fsl,vf610-edma";
				reg = <0x40098000 0x2000>,
					<0x400a1000 0x1000>,
					<0x400a2000 0x1000>;
				interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
						<0 11 IRQ_TYPE_LEVEL_HIGH>;
				interrupt-names = "edma-tx", "edma-err";
				dma-channels = <32>;
				clock-names = "dmamux0", "dmamux1";
				clocks = <&clks VF610_CLK_DMAMUX2>,
					<&clks VF610_CLK_DMAMUX3>;
			};

			uart4: serial@400a9000 {
				compatible = "fsl,vf610-lpuart";
				reg = <0x400a9000 0x1000>;
				interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_UART4>;
				clock-names = "ipg";
				status = "disabled";
			};

			uart5: serial@400aa000 {
				compatible = "fsl,vf610-lpuart";
				reg = <0x400aa000 0x1000>;
				interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_UART5>;
				clock-names = "ipg";
				status = "disabled";
			};

			adc1: adc@400bb000 {
				compatible = "fsl,vf610-adc";
				reg = <0x400bb000 0x1000>;
				interrupts = <0 54 0x04>;
				clocks = <&clks VF610_CLK_ADC1>;
				clock-names = "adc";
				status = "disabled";
			};

			fec0: ethernet@400d0000 {
				compatible = "fsl,mvf600-fec";
				reg = <0x400d0000 0x1000>;
				interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_ENET0>,
					<&clks VF610_CLK_ENET0>,
					<&clks VF610_CLK_ENET>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};

			fec1: ethernet@400d1000 {
				compatible = "fsl,mvf600-fec";
				reg = <0x400d1000 0x1000>;
				interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
				clocks = <&clks VF610_CLK_ENET1>,
					<&clks VF610_CLK_ENET1>,
					<&clks VF610_CLK_ENET>;
				clock-names = "ipg", "ahb", "ptp";
				status = "disabled";
			};
		};
	};
};
Commit	Line	Data
d02e1349 JL	1	/*
	2	* Copyright 2013 Freescale Semiconductor, Inc.
	3	*
	4	* This program is free software; you can redistribute it and/or modify
	5	* it under the terms of the GNU General Public License as published by
	6	* the Free Software Foundation; either version 2 of the License, or
	7	* (at your option) any later version.
	8	*/
	9
	10	#include "skeleton.dtsi"
	11	#include "vf610-pinfunc.h"
	12	#include <dt-bindings/clock/vf610-clock.h>
2bc88b1b	13	#include <dt-bindings/interrupt-controller/irq.h>
d02e1349 JL	14
	15	/ {
	16	aliases {
	17	serial0 = &uart0;
	18	serial1 = &uart1;
	19	serial2 = &uart2;
	20	serial3 = &uart3;
	21	serial4 = &uart4;
	22	serial5 = &uart5;
	23	gpio0 = &gpio1;
	24	gpio1 = &gpio2;
	25	gpio2 = &gpio3;
	26	gpio3 = &gpio4;
	27	gpio4 = &gpio5;
	28	};
	29
	30	cpus {
	31	#address-cells = <1>;
	32	#size-cells = <0>;
	33
	34	cpu@0 {
	35	compatible = "arm,cortex-a5";
	36	device_type = "cpu";
	37	reg = <0x0>;
	38	next-level-cache = <&L2>;
	39	};
	40	};
	41
	42	clocks {
	43	#address-cells = <1>;
	44	#size-cells = <0>;
	45
	46	sxosc {
	47	compatible = "fixed-clock";
4b2b4043	48	#clock-cells = <0>;
d02e1349 JL	49	clock-frequency = <32768>;
	50	};
	51
	52	fxosc {
	53	compatible = "fixed-clock";
4b2b4043	54	#clock-cells = <0>;
d02e1349 JL	55	clock-frequency = <24000000>;
	56	};
	57	};
	58
	59	soc {
	60	#address-cells = <1>;
	61	#size-cells = <1>;
	62	compatible = "simple-bus";
	63	interrupt-parent = <&intc>;
	64	ranges;
	65
	66	aips0: aips-bus@40000000 {
	67	compatible = "fsl,aips-bus", "simple-bus";
	68	#address-cells = <1>;
	69	#size-cells = <1>;
	70	interrupt-parent = <&intc>;
	71	reg = <0x40000000 0x70000>;
	72	ranges;
	73
	74	intc: interrupt-controller@40002000 {
	75	compatible = "arm,cortex-a9-gic";
	76	#interrupt-cells = <3>;
d02e1349 JL	77	interrupt-controller;
	78	reg = <0x40003000 0x1000>,
	79	<0x40002100 0x100>;
	80	};
	81
	82	L2: l2-cache@40006000 {
	83	compatible = "arm,pl310-cache";
	84	reg = <0x40006000 0x1000>;
	85	cache-unified;
	86	cache-level = <2>;
	87	arm,data-latency = <1 1 1>;
	88	arm,tag-latency = <2 2 2>;
	89	};
	90
b93293b9 JL	91	edma0: dma-controller@40018000 {
	92	#dma-cells = <2>;
	93	compatible = "fsl,vf610-edma";
	94	reg = <0x40018000 0x2000>,
	95	<0x40024000 0x1000>,
	96	<0x40025000 0x1000>;
	97	interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>,
	98	<0 9 IRQ_TYPE_LEVEL_HIGH>;
	99	interrupt-names = "edma-tx", "edma-err";
	100	dma-channels = <32>;
	101	clock-names = "dmamux0", "dmamux1";
	102	clocks = <&clks VF610_CLK_DMAMUX0>,
	103	<&clks VF610_CLK_DMAMUX1>;
	104	};
	105
d02e1349 JL	106	uart0: serial@40027000 {
	107	compatible = "fsl,vf610-lpuart";
	108	reg = <0x40027000 0x1000>;
2bc88b1b	109	interrupts = <0 61 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	110	clocks = <&clks VF610_CLK_UART0>;
d02e1349 JL	111	clock-names = "ipg";
8fbc8c07 YY	112	dmas = <&edma0 0 2>,
	113	<&edma0 0 3>;
	114	dma-names = "rx","tx";
d02e1349 JL	115	status = "disabled";
	116	};
	117
	118	uart1: serial@40028000 {
	119	compatible = "fsl,vf610-lpuart";
	120	reg = <0x40028000 0x1000>;
2bc88b1b	121	interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	122	clocks = <&clks VF610_CLK_UART1>;
d02e1349 JL	123	clock-names = "ipg";
8fbc8c07 YY	124	dmas = <&edma0 0 4>,
	125	<&edma0 0 5>;
	126	dma-names = "rx","tx";
d02e1349 JL	127	status = "disabled";
	128	};
	129
	130	uart2: serial@40029000 {
	131	compatible = "fsl,vf610-lpuart";
	132	reg = <0x40029000 0x1000>;
2bc88b1b	133	interrupts = <0 63 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	134	clocks = <&clks VF610_CLK_UART2>;
d02e1349 JL	135	clock-names = "ipg";
8fbc8c07 YY	136	dmas = <&edma0 0 6>,
	137	<&edma0 0 7>;
	138	dma-names = "rx","tx";
d02e1349 JL	139	status = "disabled";
	140	};
	141
	142	uart3: serial@4002a000 {
	143	compatible = "fsl,vf610-lpuart";
	144	reg = <0x4002a000 0x1000>;
2bc88b1b	145	interrupts = <0 64 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	146	clocks = <&clks VF610_CLK_UART3>;
d02e1349 JL	147	clock-names = "ipg";
8fbc8c07 YY	148	dmas = <&edma0 0 8>,
	149	<&edma0 0 9>;
	150	dma-names = "rx","tx";
d02e1349 JL	151	status = "disabled";
	152	};
	153
d7a9d8e2 CF	154	dspi0: dspi0@4002c000 {
	155	#address-cells = <1>;
	156	#size-cells = <0>;
	157	compatible = "fsl,vf610-dspi";
	158	reg = <0x4002c000 0x1000>;
2bc88b1b	159	interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>;
d7a9d8e2 CF	160	clocks = <&clks VF610_CLK_DSPI0>;
	161	clock-names = "dspi";
	162	spi-num-chipselects = <5>;
	163	status = "disabled";
	164	};
	165
d02e1349 JL	166	sai2: sai@40031000 {
	167	compatible = "fsl,vf610-sai";
	168	reg = <0x40031000 0x1000>;
2bc88b1b	169	interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	170	clocks = <&clks VF610_CLK_SAI2>;
d02e1349 JL	171	clock-names = "sai";
1d412417 XL	172	dma-names = "tx", "rx";
	173	dmas = <&edma0 0 21>,
	174	<&edma0 0 20>;
d02e1349 JL	175	status = "disabled";
	176	};
	177
	178	pit: pit@40037000 {
	179	compatible = "fsl,vf610-pit";
	180	reg = <0x40037000 0x1000>;
2bc88b1b	181	interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	182	clocks = <&clks VF610_CLK_PIT>;
	183	clock-names = "pit";
	184	};
	185
64436ff6 FD	186	adc0: adc@4003b000 {
	187	compatible = "fsl,vf610-adc";
	188	reg = <0x4003b000 0x1000>;
	189	interrupts = <0 53 0x04>;
	190	clocks = <&clks VF610_CLK_ADC0>;
	191	clock-names = "adc";
	192	status = "disabled";
	193	};
	194
d02e1349 JL	195	wdog@4003e000 {
	196	compatible = "fsl,vf610-wdt", "fsl,imx21-wdt";
	197	reg = <0x4003e000 0x1000>;
	198	clocks = <&clks VF610_CLK_WDT>;
	199	clock-names = "wdog";
	200	};
	201
	202	qspi0: quadspi@40044000 {
	203	#address-cells = <1>;
	204	#size-cells = <0>;
	205	compatible = "fsl,vf610-qspi";
	206	reg = <0x40044000 0x1000>;
2bc88b1b	207	interrupts = <0 24 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	208	clocks = <&clks VF610_CLK_QSPI0_EN>,
	209	<&clks VF610_CLK_QSPI0>;
	210	clock-names = "qspi_en", "qspi";
	211	status = "disabled";
	212	};
	213
	214	iomuxc: iomuxc@40048000 {
	215	compatible = "fsl,vf610-iomuxc";
	216	reg = <0x40048000 0x1000>;
36af8f3e	217	#gpio-range-cells = <3>;
d02e1349 JL	218	};
	219
	220	gpio1: gpio@40049000 {
	221	compatible = "fsl,vf610-gpio";
	222	reg = <0x40049000 0x1000 0x400ff000 0x40>;
2bc88b1b	223	interrupts = <0 107 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	224	gpio-controller;
	225	#gpio-cells = <2>;
	226	interrupt-controller;
	227	#interrupt-cells = <2>;
36af8f3e	228	gpio-ranges = <&iomuxc 0 0 32>;
d02e1349 JL	229	};
	230
	231	gpio2: gpio@4004a000 {
	232	compatible = "fsl,vf610-gpio";
	233	reg = <0x4004a000 0x1000 0x400ff040 0x40>;
2bc88b1b	234	interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	235	gpio-controller;
	236	#gpio-cells = <2>;
	237	interrupt-controller;
	238	#interrupt-cells = <2>;
36af8f3e	239	gpio-ranges = <&iomuxc 0 32 32>;
d02e1349 JL	240	};
	241
	242	gpio3: gpio@4004b000 {
	243	compatible = "fsl,vf610-gpio";
	244	reg = <0x4004b000 0x1000 0x400ff080 0x40>;
2bc88b1b	245	interrupts = <0 109 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	246	gpio-controller;
	247	#gpio-cells = <2>;
	248	interrupt-controller;
	249	#interrupt-cells = <2>;
36af8f3e	250	gpio-ranges = <&iomuxc 0 64 32>;
d02e1349 JL	251	};
	252
	253	gpio4: gpio@4004c000 {
	254	compatible = "fsl,vf610-gpio";
	255	reg = <0x4004c000 0x1000 0x400ff0c0 0x40>;
2bc88b1b	256	interrupts = <0 110 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	257	gpio-controller;
	258	#gpio-cells = <2>;
	259	interrupt-controller;
	260	#interrupt-cells = <2>;
36af8f3e	261	gpio-ranges = <&iomuxc 0 96 32>;
d02e1349 JL	262	};
	263
	264	gpio5: gpio@4004d000 {
	265	compatible = "fsl,vf610-gpio";
	266	reg = <0x4004d000 0x1000 0x400ff100 0x40>;
2bc88b1b	267	interrupts = <0 111 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	268	gpio-controller;
	269	#gpio-cells = <2>;
	270	interrupt-controller;
	271	#interrupt-cells = <2>;
36af8f3e	272	gpio-ranges = <&iomuxc 0 128 7>;
d02e1349 JL	273	};
	274
	275	anatop@40050000 {
	276	compatible = "fsl,vf610-anatop";
	277	reg = <0x40050000 0x1000>;
	278	};
	279
	280	i2c0: i2c@40066000 {
	281	#address-cells = <1>;
	282	#size-cells = <0>;
	283	compatible = "fsl,vf610-i2c";
	284	reg = <0x40066000 0x1000>;
2bc88b1b	285	interrupts =<0 71 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	286	clocks = <&clks VF610_CLK_I2C0>;
d02e1349 JL	287	clock-names = "ipg";
b4e5e84d YY	288	dmas = <&edma0 0 50>,
	289	<&edma0 0 51>;
	290	dma-names = "rx","tx";
d02e1349 JL	291	status = "disabled";
	292	};
	293
	294	clks: ccm@4006b000 {
	295	compatible = "fsl,vf610-ccm";
	296	reg = <0x4006b000 0x1000>;
	297	#clock-cells = <1>;
	298	};
	299	};
	300
	301	aips1: aips-bus@40080000 {
	302	compatible = "fsl,aips-bus", "simple-bus";
	303	#address-cells = <1>;
	304	#size-cells = <1>;
	305	reg = <0x40080000 0x80000>;
	306	ranges;
	307
b93293b9 JL	308	edma1: dma-controller@40098000 {
	309	#dma-cells = <2>;
	310	compatible = "fsl,vf610-edma";
	311	reg = <0x40098000 0x2000>,
	312	<0x400a1000 0x1000>,
	313	<0x400a2000 0x1000>;
	314	interrupts = <0 10 IRQ_TYPE_LEVEL_HIGH>,
	315	<0 11 IRQ_TYPE_LEVEL_HIGH>;
	316	interrupt-names = "edma-tx", "edma-err";
	317	dma-channels = <32>;
	318	clock-names = "dmamux0", "dmamux1";
	319	clocks = <&clks VF610_CLK_DMAMUX2>,
	320	<&clks VF610_CLK_DMAMUX3>;
	321	};
	322
d02e1349 JL	323	uart4: serial@400a9000 {
	324	compatible = "fsl,vf610-lpuart";
	325	reg = <0x400a9000 0x1000>;
2bc88b1b	326	interrupts = <0 65 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	327	clocks = <&clks VF610_CLK_UART4>;
	328	clock-names = "ipg";
	329	status = "disabled";
	330	};
	331
	332	uart5: serial@400aa000 {
	333	compatible = "fsl,vf610-lpuart";
	334	reg = <0x400aa000 0x1000>;
2bc88b1b	335	interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>;
d02e1349 JL	336	clocks = <&clks VF610_CLK_UART5>;
	337	clock-names = "ipg";
	338	status = "disabled";
	339	};
	340
64436ff6 FD	341	adc1: adc@400bb000 {
	342	compatible = "fsl,vf610-adc";
	343	reg = <0x400bb000 0x1000>;
	344	interrupts = <0 54 0x04>;
	345	clocks = <&clks VF610_CLK_ADC1>;
	346	clock-names = "adc";
	347	status = "disabled";
	348	};
	349
d02e1349 JL	350	fec0: ethernet@400d0000 {
	351	compatible = "fsl,mvf600-fec";
	352	reg = <0x400d0000 0x1000>;
2bc88b1b	353	interrupts = <0 78 IRQ_TYPE_LEVEL_HIGH>;
4f71612e SG	354	clocks = <&clks VF610_CLK_ENET0>,
4f71612e SG	355	<&clks VF610_CLK_ENET0>,
d02e1349 JL	356	<&clks VF610_CLK_ENET>;
	357	clock-names = "ipg", "ahb", "ptp";
	358	status = "disabled";
	359	};
	360
	361	fec1: ethernet@400d1000 {
	362	compatible = "fsl,mvf600-fec";
	363	reg = <0x400d1000 0x1000>;
2bc88b1b	364	interrupts = <0 79 IRQ_TYPE_LEVEL_HIGH>;
4f71612e SG	365	clocks = <&clks VF610_CLK_ENET1>,
4f71612e SG	366	<&clks VF610_CLK_ENET1>,
d02e1349 JL	367	<&clks VF610_CLK_ENET>;
	368	clock-names = "ipg", "ahb", "ptp";
	369	status = "disabled";
	370	};
	371	};
	372	};
	373	};