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cb935e71 TP |
1 | /* |
2 | * vt8500.dtsi - Device tree file for VIA VT8500 SoC | |
3 | * | |
4 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | |
5 | * | |
6 | * Licensed under GPLv2 or later | |
7 | */ | |
8 | ||
9 | /include/ "skeleton.dtsi" | |
10 | ||
11 | / { | |
12 | compatible = "via,vt8500"; | |
13 | ||
14 | soc { | |
15 | #address-cells = <1>; | |
16 | #size-cells = <1>; | |
17 | compatible = "simple-bus"; | |
18 | ranges; | |
19 | interrupt-parent = <&intc>; | |
20 | ||
21 | intc: interrupt-controller@d8140000 { | |
22 | compatible = "via,vt8500-intc"; | |
23 | interrupt-controller; | |
24 | reg = <0xd8140000 0x10000>; | |
25 | #interrupt-cells = <1>; | |
26 | }; | |
27 | ||
28 | gpio: gpio-controller@d8110000 { | |
29 | compatible = "via,vt8500-gpio"; | |
30 | gpio-controller; | |
31 | reg = <0xd8110000 0x10000>; | |
32 | #gpio-cells = <3>; | |
33 | }; | |
34 | ||
35 | pmc@d8130000 { | |
36 | compatible = "via,vt8500-pmc"; | |
37 | reg = <0xd8130000 0x1000>; | |
38 | ||
39 | clocks { | |
40 | #address-cells = <1>; | |
41 | #size-cells = <0>; | |
42 | ||
43 | ref24: ref24M { | |
44 | #clock-cells = <0>; | |
45 | compatible = "fixed-clock"; | |
46 | clock-frequency = <24000000>; | |
47 | }; | |
12faa35a TP |
48 | |
49 | clkuart0: uart0 { | |
50 | #clock-cells = <0>; | |
51 | compatible = "via,vt8500-device-clock"; | |
52 | clocks = <&ref24>; | |
53 | enable-reg = <0x250>; | |
54 | enable-bit = <1>; | |
55 | }; | |
56 | ||
57 | clkuart1: uart1 { | |
58 | #clock-cells = <0>; | |
59 | compatible = "via,vt8500-device-clock"; | |
60 | clocks = <&ref24>; | |
61 | enable-reg = <0x250>; | |
62 | enable-bit = <2>; | |
63 | }; | |
64 | ||
65 | clkuart2: uart2 { | |
66 | #clock-cells = <0>; | |
67 | compatible = "via,vt8500-device-clock"; | |
68 | clocks = <&ref24>; | |
69 | enable-reg = <0x250>; | |
70 | enable-bit = <3>; | |
71 | }; | |
72 | ||
73 | clkuart3: uart3 { | |
74 | #clock-cells = <0>; | |
75 | compatible = "via,vt8500-device-clock"; | |
76 | clocks = <&ref24>; | |
77 | enable-reg = <0x250>; | |
78 | enable-bit = <4>; | |
79 | }; | |
cb935e71 TP |
80 | }; |
81 | }; | |
82 | ||
83 | timer@d8130100 { | |
84 | compatible = "via,vt8500-timer"; | |
85 | reg = <0xd8130100 0x28>; | |
86 | interrupts = <36>; | |
87 | }; | |
88 | ||
89 | ehci@d8007900 { | |
90 | compatible = "via,vt8500-ehci"; | |
91 | reg = <0xd8007900 0x200>; | |
92 | interrupts = <43>; | |
93 | }; | |
94 | ||
95 | uhci@d8007b00 { | |
96 | compatible = "platform-uhci"; | |
97 | reg = <0xd8007b00 0x200>; | |
98 | interrupts = <43>; | |
99 | }; | |
100 | ||
101 | fb@d800e400 { | |
102 | compatible = "via,vt8500-fb"; | |
103 | reg = <0xd800e400 0x400>; | |
104 | interrupts = <12>; | |
105 | display = <&display>; | |
106 | default-mode = <&mode0>; | |
107 | }; | |
108 | ||
109 | ge_rops@d8050400 { | |
110 | compatible = "wm,prizm-ge-rops"; | |
111 | reg = <0xd8050400 0x100>; | |
112 | }; | |
113 | ||
114 | uart@d8200000 { | |
115 | compatible = "via,vt8500-uart"; | |
116 | reg = <0xd8200000 0x1040>; | |
117 | interrupts = <32>; | |
12faa35a | 118 | clocks = <&clkuart0>; |
cb935e71 TP |
119 | }; |
120 | ||
121 | uart@d82b0000 { | |
122 | compatible = "via,vt8500-uart"; | |
123 | reg = <0xd82b0000 0x1040>; | |
124 | interrupts = <33>; | |
12faa35a | 125 | clocks = <&clkuart1>; |
cb935e71 TP |
126 | }; |
127 | ||
128 | uart@d8210000 { | |
129 | compatible = "via,vt8500-uart"; | |
130 | reg = <0xd8210000 0x1040>; | |
131 | interrupts = <47>; | |
12faa35a | 132 | clocks = <&clkuart2>; |
cb935e71 TP |
133 | }; |
134 | ||
135 | uart@d82c0000 { | |
136 | compatible = "via,vt8500-uart"; | |
137 | reg = <0xd82c0000 0x1040>; | |
138 | interrupts = <50>; | |
12faa35a | 139 | clocks = <&clkuart3>; |
cb935e71 TP |
140 | }; |
141 | ||
142 | rtc@d8100000 { | |
143 | compatible = "via,vt8500-rtc"; | |
144 | reg = <0xd8100000 0x10000>; | |
145 | interrupts = <48>; | |
146 | }; | |
147 | }; | |
148 | }; |