projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| def4d6c0 TP |
1 | /* |
| 2 | * wm8850.dtsi - Device tree file for Wondermedia WM8850 SoC | |
| 3 | * | |
| 4 | * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz> | |
| 5 | * | |
| 6 | * Licensed under GPLv2 or later | |
| 7 | */ | |
| 8 | ||
| 9 | /include/ "skeleton.dtsi" | |
| 10 | ||
| 11 | / { | |
| 12 | compatible = "wm,wm8850"; | |
| 13 | ||
| 7ec13d42 TP |
14 | cpus { |
| 15 | #address-cells = <1>; | |
| 16 | #size-cells = <0>; | |
| 17 | ||
| 18 | cpu@0 { | |
| 19 | device_type = "cpu"; | |
| 20 | compatible = "arm,cortex-a9"; | |
| 21 | reg = <0x0>; | |
| 22 | }; | |
| 23 | }; | |
| 24 | ||
| def4d6c0 TP |
25 | aliases { |
| 26 | serial0 = &uart0; | |
| 27 | serial1 = &uart1; | |
| 28 | serial2 = &uart2; | |
| 29 | serial3 = &uart3; | |
| 30 | }; | |
| 31 | ||
| 32 | soc { | |
| 33 | #address-cells = <1>; | |
| 34 | #size-cells = <1>; | |
| 35 | compatible = "simple-bus"; | |
| 36 | ranges; | |
| 37 | interrupt-parent = <&intc0>; | |
| 38 | ||
| 39 | intc0: interrupt-controller@d8140000 { | |
| 40 | compatible = "via,vt8500-intc"; | |
| 41 | interrupt-controller; | |
| 42 | reg = <0xd8140000 0x10000>; | |
| 43 | #interrupt-cells = <1>; | |
| 44 | }; | |
| 45 | ||
| 46 | /* Secondary IC cascaded to intc0 */ | |
| 47 | intc1: interrupt-controller@d8150000 { | |
| 48 | compatible = "via,vt8500-intc"; | |
| 49 | interrupt-controller; | |
| 50 | #interrupt-cells = <1>; | |
| 51 | reg = <0xD8150000 0x10000>; | |
| 52 | interrupts = <56 57 58 59 60 61 62 63>; | |
| 53 | }; | |
| 54 | ||
| 649a59cf TP |
55 | pinctrl: pinctrl@d8110000 { |
| 56 | compatible = "wm,wm8850-pinctrl"; | |
| def4d6c0 | 57 | reg = <0xd8110000 0x10000>; |
| 649a59cf TP |
58 | interrupt-controller; |
| 59 | #interrupt-cells = <2>; | |
| 60 | gpio-controller; | |
| 61 | #gpio-cells = <2>; | |
| def4d6c0 TP |
62 | }; |
| 63 | ||
| 64 | pmc@d8130000 { | |
| 65 | compatible = "via,vt8500-pmc"; | |
| 66 | reg = <0xd8130000 0x1000>; | |
| 67 | ||
| 68 | clocks { | |
| 69 | #address-cells = <1>; | |
| 70 | #size-cells = <0>; | |
| 71 | ||
| 72 | ref25: ref25M { | |
| 73 | #clock-cells = <0>; | |
| 74 | compatible = "fixed-clock"; | |
| 75 | clock-frequency = <25000000>; | |
| 76 | }; | |
| 77 | ||
| 78 | ref24: ref24M { | |
| 79 | #clock-cells = <0>; | |
| 80 | compatible = "fixed-clock"; | |
| 81 | clock-frequency = <24000000>; | |
| 82 | }; | |
| 83 | ||
| 84 | plla: plla { | |
| 85 | #clock-cells = <0>; | |
| 7d4c6f3c | 86 | compatible = "wm,wm8850-pll-clock"; |
| def4d6c0 TP |
87 | clocks = <&ref25>; |
| 88 | reg = <0x200>; | |
| 89 | }; | |
| 90 | ||
| 91 | pllb: pllb { | |
| 92 | #clock-cells = <0>; | |
| 7d4c6f3c | 93 | compatible = "wm,wm8850-pll-clock"; |
| def4d6c0 TP |
94 | clocks = <&ref25>; |
| 95 | reg = <0x204>; | |
| 96 | }; | |
| 97 | ||
| 5c2b0a85 TP |
98 | pllc: pllc { |
| 99 | #clock-cells = <0>; | |
| 100 | compatible = "wm,wm8850-pll-clock"; | |
| 101 | clocks = <&ref25>; | |
| 102 | reg = <0x208>; | |
| 103 | }; | |
| 104 | ||
| 105 | plld: plld { | |
| 106 | #clock-cells = <0>; | |
| 107 | compatible = "wm,wm8850-pll-clock"; | |
| 108 | clocks = <&ref25>; | |
| 109 | reg = <0x20c>; | |
| 110 | }; | |
| 111 | ||
| 112 | plle: plle { | |
| 113 | #clock-cells = <0>; | |
| 114 | compatible = "wm,wm8850-pll-clock"; | |
| 115 | clocks = <&ref25>; | |
| 116 | reg = <0x210>; | |
| 117 | }; | |
| 118 | ||
| 119 | pllf: pllf { | |
| 120 | #clock-cells = <0>; | |
| 121 | compatible = "wm,wm8850-pll-clock"; | |
| 122 | clocks = <&ref25>; | |
| 123 | reg = <0x214>; | |
| 124 | }; | |
| 125 | ||
| 126 | pllg: pllg { | |
| 127 | #clock-cells = <0>; | |
| 128 | compatible = "wm,wm8850-pll-clock"; | |
| 129 | clocks = <&ref25>; | |
| 130 | reg = <0x218>; | |
| 131 | }; | |
| 132 | ||
| def4d6c0 TP |
133 | clkuart0: uart0 { |
| 134 | #clock-cells = <0>; | |
| 135 | compatible = "via,vt8500-device-clock"; | |
| 136 | clocks = <&ref24>; | |
| 137 | enable-reg = <0x254>; | |
| 138 | enable-bit = <24>; | |
| 139 | }; | |
| 140 | ||
| 141 | clkuart1: uart1 { | |
| 142 | #clock-cells = <0>; | |
| 143 | compatible = "via,vt8500-device-clock"; | |
| 144 | clocks = <&ref24>; | |
| 145 | enable-reg = <0x254>; | |
| 146 | enable-bit = <25>; | |
| 147 | }; | |
| 148 | ||
| 149 | clkuart2: uart2 { | |
| 150 | #clock-cells = <0>; | |
| 151 | compatible = "via,vt8500-device-clock"; | |
| 152 | clocks = <&ref24>; | |
| 153 | enable-reg = <0x254>; | |
| 154 | enable-bit = <26>; | |
| 155 | }; | |
| 156 | ||
| 157 | clkuart3: uart3 { | |
| 158 | #clock-cells = <0>; | |
| 159 | compatible = "via,vt8500-device-clock"; | |
| 160 | clocks = <&ref24>; | |
| 161 | enable-reg = <0x254>; | |
| 162 | enable-bit = <27>; | |
| 163 | }; | |
| 164 | ||
| 165 | clkpwm: pwm { | |
| 166 | #clock-cells = <0>; | |
| 167 | compatible = "via,vt8500-device-clock"; | |
| 168 | clocks = <&pllb>; | |
| 169 | divisor-reg = <0x350>; | |
| 170 | enable-reg = <0x250>; | |
| 171 | enable-bit = <17>; | |
| 172 | }; | |
| 173 | ||
| 174 | clksdhc: sdhc { | |
| 175 | #clock-cells = <0>; | |
| 176 | compatible = "via,vt8500-device-clock"; | |
| 177 | clocks = <&pllb>; | |
| 178 | divisor-reg = <0x330>; | |
| 179 | divisor-mask = <0x3f>; | |
| 180 | enable-reg = <0x250>; | |
| 181 | enable-bit = <0>; | |
| 182 | }; | |
| 183 | }; | |
| 184 | }; | |
| 185 | ||
| 7ab0a484 | 186 | fb: fb@d8051700 { |
| def4d6c0 TP |
187 | compatible = "wm,wm8505-fb"; |
| 188 | reg = <0xd8051700 0x200>; | |
| def4d6c0 TP |
189 | }; |
| 190 | ||
| 191 | ge_rops@d8050400 { | |
| 192 | compatible = "wm,prizm-ge-rops"; | |
| 193 | reg = <0xd8050400 0x100>; | |
| 194 | }; | |
| 195 | ||
| 196 | pwm: pwm@d8220000 { | |
| 197 | #pwm-cells = <3>; | |
| 198 | compatible = "via,vt8500-pwm"; | |
| 199 | reg = <0xd8220000 0x100>; | |
| 200 | clocks = <&clkpwm>; | |
| 201 | }; | |
| 202 | ||
| 203 | timer@d8130100 { | |
| 204 | compatible = "via,vt8500-timer"; | |
| 205 | reg = <0xd8130100 0x28>; | |
| 206 | interrupts = <36>; | |
| 207 | }; | |
| 208 | ||
| 209 | ehci@d8007900 { | |
| 210 | compatible = "via,vt8500-ehci"; | |
| 211 | reg = <0xd8007900 0x200>; | |
| 212 | interrupts = <26>; | |
| 213 | }; | |
| 214 | ||
| 215 | uhci@d8007b00 { | |
| 216 | compatible = "platform-uhci"; | |
| 217 | reg = <0xd8007b00 0x200>; | |
| 218 | interrupts = <26>; | |
| 219 | }; | |
| 220 | ||
| 221 | uhci@d8008d00 { | |
| 222 | compatible = "platform-uhci"; | |
| 223 | reg = <0xd8008d00 0x200>; | |
| 224 | interrupts = <26>; | |
| 225 | }; | |
| 226 | ||
| 55954f85 | 227 | uart0: serial@d8200000 { |
| def4d6c0 TP |
228 | compatible = "via,vt8500-uart"; |
| 229 | reg = <0xd8200000 0x1040>; | |
| 230 | interrupts = <32>; | |
| 231 | clocks = <&clkuart0>; | |
| 55954f85 | 232 | status = "disabled"; |
| def4d6c0 TP |
233 | }; |
| 234 | ||
| 55954f85 | 235 | uart1: serial@d82b0000 { |
| def4d6c0 TP |
236 | compatible = "via,vt8500-uart"; |
| 237 | reg = <0xd82b0000 0x1040>; | |
| 238 | interrupts = <33>; | |
| 239 | clocks = <&clkuart1>; | |
| 55954f85 | 240 | status = "disabled"; |
| def4d6c0 TP |
241 | }; |
| 242 | ||
| 55954f85 | 243 | uart2: serial@d8210000 { |
| def4d6c0 TP |
244 | compatible = "via,vt8500-uart"; |
| 245 | reg = <0xd8210000 0x1040>; | |
| 246 | interrupts = <47>; | |
| 247 | clocks = <&clkuart2>; | |
| 55954f85 | 248 | status = "disabled"; |
| def4d6c0 TP |
249 | }; |
| 250 | ||
| 55954f85 | 251 | uart3: serial@d82c0000 { |
| def4d6c0 TP |
252 | compatible = "via,vt8500-uart"; |
| 253 | reg = <0xd82c0000 0x1040>; | |
| 254 | interrupts = <50>; | |
| 255 | clocks = <&clkuart3>; | |
| 55954f85 | 256 | status = "disabled"; |
| def4d6c0 TP |
257 | }; |
| 258 | ||
| 259 | rtc@d8100000 { | |
| 260 | compatible = "via,vt8500-rtc"; | |
| 261 | reg = <0xd8100000 0x10000>; | |
| 262 | interrupts = <48>; | |
| 263 | }; | |
| 264 | ||
| 265 | sdhc@d800a000 { | |
| 266 | compatible = "wm,wm8505-sdhc"; | |
| 267 | reg = <0xd800a000 0x1000>; | |
| 268 | interrupts = <20 21>; | |
| 269 | clocks = <&clksdhc>; | |
| 270 | bus-width = <4>; | |
| 271 | sdon-inverted; | |
| 272 | }; | |
| 273 | }; | |
| 274 | }; |