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b85a3ef4 JL |
1 | /* |
2 | * Copyright (C) 2011 Xilinx | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
e06f1a9e | 13 | /include/ "skeleton.dtsi" |
b85a3ef4 | 14 | |
b85a3ef4 | 15 | / { |
e06f1a9e | 16 | compatible = "xlnx,zynq-7000"; |
b85a3ef4 | 17 | |
268a8200 MS |
18 | pmu { |
19 | compatible = "arm,cortex-a9-pmu"; | |
20 | interrupts = <0 5 4>, <0 6 4>; | |
21 | interrupt-parent = <&intc>; | |
22 | reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; | |
23 | }; | |
24 | ||
b85a3ef4 JL |
25 | amba { |
26 | compatible = "simple-bus"; | |
27 | #address-cells = <1>; | |
28 | #size-cells = <1>; | |
e06f1a9e | 29 | interrupt-parent = <&intc>; |
b85a3ef4 JL |
30 | ranges; |
31 | ||
32 | intc: interrupt-controller@f8f01000 { | |
f447ed2d JC |
33 | compatible = "arm,cortex-a9-gic"; |
34 | #interrupt-cells = <3>; | |
35 | #address-cells = <1>; | |
b85a3ef4 | 36 | interrupt-controller; |
f447ed2d JC |
37 | reg = <0xF8F01000 0x1000>, |
38 | <0xF8F00100 0x100>; | |
b85a3ef4 JL |
39 | }; |
40 | ||
0fcfdbca JC |
41 | L2: cache-controller { |
42 | compatible = "arm,pl310-cache"; | |
43 | reg = <0xF8F02000 0x1000>; | |
44 | arm,data-latency = <2 3 2>; | |
45 | arm,tag-latency = <2 3 2>; | |
46 | cache-unified; | |
47 | cache-level = <2>; | |
48 | }; | |
49 | ||
b85a3ef4 JL |
50 | uart0: uart@e0000000 { |
51 | compatible = "xlnx,xuartps"; | |
ec11ebcf | 52 | status = "disabled"; |
30e1e285 SB |
53 | clocks = <&clkc 23>, <&clkc 40>; |
54 | clock-names = "ref_clk", "aper_clk"; | |
b85a3ef4 | 55 | reg = <0xE0000000 0x1000>; |
f447ed2d | 56 | interrupts = <0 27 4>; |
b85a3ef4 | 57 | }; |
78d6785d JC |
58 | |
59 | uart1: uart@e0001000 { | |
60 | compatible = "xlnx,xuartps"; | |
ec11ebcf | 61 | status = "disabled"; |
30e1e285 SB |
62 | clocks = <&clkc 24>, <&clkc 41>; |
63 | clock-names = "ref_clk", "aper_clk"; | |
78d6785d JC |
64 | reg = <0xE0001000 0x1000>; |
65 | interrupts = <0 50 4>; | |
78d6785d | 66 | }; |
0f586fbf JC |
67 | |
68 | slcr: slcr@f8000000 { | |
69 | compatible = "xlnx,zynq-slcr"; | |
70 | reg = <0xF8000000 0x1000>; | |
71 | ||
72 | clocks { | |
73 | #address-cells = <1>; | |
74 | #size-cells = <0>; | |
75 | ||
30e1e285 | 76 | clkc: clkc { |
0f586fbf | 77 | #clock-cells = <1>; |
30e1e285 SB |
78 | compatible = "xlnx,ps7-clkc"; |
79 | ps-clk-frequency = <33333333>; | |
80 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", | |
81 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", | |
82 | "dci", "lqspi", "smc", "pcap", "gem0", "gem1", | |
83 | "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", | |
84 | "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", | |
85 | "dma", "usb0_aper", "usb1_aper", "gem0_aper", | |
86 | "gem1_aper", "sdio0_aper", "sdio1_aper", | |
87 | "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", | |
88 | "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", | |
89 | "gpio_aper", "lqspi_aper", "smc_aper", "swdt", | |
90 | "dbg_trc", "dbg_apb"; | |
0f586fbf JC |
91 | }; |
92 | }; | |
93 | }; | |
91dc985c JC |
94 | |
95 | ttc0: ttc0@f8001000 { | |
e932900a MS |
96 | interrupt-parent = <&intc>; |
97 | interrupts = < 0 10 4 0 11 4 0 12 4 >; | |
98 | compatible = "cdns,ttc"; | |
30e1e285 | 99 | clocks = <&clkc 6>; |
91dc985c | 100 | reg = <0xF8001000 0x1000>; |
91dc985c | 101 | clock-ranges; |
91dc985c JC |
102 | }; |
103 | ||
104 | ttc1: ttc1@f8002000 { | |
e932900a MS |
105 | interrupt-parent = <&intc>; |
106 | interrupts = < 0 37 4 0 38 4 0 39 4 >; | |
107 | compatible = "cdns,ttc"; | |
30e1e285 | 108 | clocks = <&clkc 6>; |
91dc985c | 109 | reg = <0xF8002000 0x1000>; |
91dc985c | 110 | clock-ranges; |
91dc985c | 111 | }; |
2f34e0a5 MS |
112 | scutimer: scutimer@f8f00600 { |
113 | interrupt-parent = <&intc>; | |
114 | interrupts = < 1 13 0x301 >; | |
115 | compatible = "arm,cortex-a9-twd-timer"; | |
116 | reg = < 0xf8f00600 0x20 >; | |
30e1e285 | 117 | clocks = <&clkc 4>; |
2f34e0a5 | 118 | } ; |
b85a3ef4 JL |
119 | }; |
120 | }; |