Commit | Line | Data |
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b85a3ef4 JL |
1 | /* |
2 | * Copyright (C) 2011 Xilinx | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
e06f1a9e | 13 | /include/ "skeleton.dtsi" |
b85a3ef4 | 14 | |
b85a3ef4 | 15 | / { |
e06f1a9e | 16 | compatible = "xlnx,zynq-7000"; |
b85a3ef4 | 17 | |
41e4cdb9 SB |
18 | cpus { |
19 | #address-cells = <1>; | |
20 | #size-cells = <0>; | |
21 | ||
22 | cpu@0 { | |
23 | compatible = "arm,cortex-a9"; | |
24 | device_type = "cpu"; | |
25 | reg = <0>; | |
26 | clocks = <&clkc 3>; | |
b2bf5d48 | 27 | clock-latency = <1000>; |
cd325295 SB |
28 | operating-points = < |
29 | /* kHz uV */ | |
30 | 666667 1000000 | |
31 | 333334 1000000 | |
32 | 222223 1000000 | |
33 | >; | |
41e4cdb9 SB |
34 | }; |
35 | ||
36 | cpu@1 { | |
37 | compatible = "arm,cortex-a9"; | |
38 | device_type = "cpu"; | |
39 | reg = <1>; | |
40 | clocks = <&clkc 3>; | |
41 | }; | |
42 | }; | |
43 | ||
268a8200 MS |
44 | pmu { |
45 | compatible = "arm,cortex-a9-pmu"; | |
46 | interrupts = <0 5 4>, <0 6 4>; | |
47 | interrupt-parent = <&intc>; | |
48 | reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >; | |
49 | }; | |
50 | ||
b85a3ef4 JL |
51 | amba { |
52 | compatible = "simple-bus"; | |
53 | #address-cells = <1>; | |
54 | #size-cells = <1>; | |
e06f1a9e | 55 | interrupt-parent = <&intc>; |
b85a3ef4 JL |
56 | ranges; |
57 | ||
0f6faa3f SB |
58 | i2c0: zynq-i2c@e0004000 { |
59 | compatible = "cdns,i2c-r1p10"; | |
60 | status = "disabled"; | |
61 | clocks = <&clkc 38>; | |
62 | interrupt-parent = <&intc>; | |
63 | interrupts = <0 25 4>; | |
64 | reg = <0xe0004000 0x1000>; | |
65 | #address-cells = <1>; | |
66 | #size-cells = <0>; | |
67 | }; | |
68 | ||
69 | i2c1: zynq-i2c@e0005000 { | |
70 | compatible = "cdns,i2c-r1p10"; | |
71 | status = "disabled"; | |
72 | clocks = <&clkc 39>; | |
73 | interrupt-parent = <&intc>; | |
74 | interrupts = <0 48 4>; | |
75 | reg = <0xe0005000 0x1000>; | |
76 | #address-cells = <1>; | |
77 | #size-cells = <0>; | |
78 | }; | |
79 | ||
b85a3ef4 | 80 | intc: interrupt-controller@f8f01000 { |
f447ed2d JC |
81 | compatible = "arm,cortex-a9-gic"; |
82 | #interrupt-cells = <3>; | |
83 | #address-cells = <1>; | |
b85a3ef4 | 84 | interrupt-controller; |
f447ed2d JC |
85 | reg = <0xF8F01000 0x1000>, |
86 | <0xF8F00100 0x100>; | |
b85a3ef4 JL |
87 | }; |
88 | ||
0fcfdbca JC |
89 | L2: cache-controller { |
90 | compatible = "arm,pl310-cache"; | |
91 | reg = <0xF8F02000 0x1000>; | |
39c41df9 SB |
92 | arm,data-latency = <3 2 2>; |
93 | arm,tag-latency = <2 2 2>; | |
0fcfdbca JC |
94 | cache-unified; |
95 | cache-level = <2>; | |
96 | }; | |
97 | ||
b85a3ef4 JL |
98 | uart0: uart@e0000000 { |
99 | compatible = "xlnx,xuartps"; | |
ec11ebcf | 100 | status = "disabled"; |
30e1e285 SB |
101 | clocks = <&clkc 23>, <&clkc 40>; |
102 | clock-names = "ref_clk", "aper_clk"; | |
b85a3ef4 | 103 | reg = <0xE0000000 0x1000>; |
f447ed2d | 104 | interrupts = <0 27 4>; |
b85a3ef4 | 105 | }; |
78d6785d JC |
106 | |
107 | uart1: uart@e0001000 { | |
108 | compatible = "xlnx,xuartps"; | |
ec11ebcf | 109 | status = "disabled"; |
30e1e285 SB |
110 | clocks = <&clkc 24>, <&clkc 41>; |
111 | clock-names = "ref_clk", "aper_clk"; | |
78d6785d JC |
112 | reg = <0xE0001000 0x1000>; |
113 | interrupts = <0 50 4>; | |
78d6785d | 114 | }; |
0f586fbf | 115 | |
982264c3 ST |
116 | gem0: ethernet@e000b000 { |
117 | compatible = "cdns,gem"; | |
118 | reg = <0xe000b000 0x4000>; | |
119 | status = "disabled"; | |
120 | interrupts = <0 22 4>; | |
121 | clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>; | |
122 | clock-names = "pclk", "hclk", "tx_clk"; | |
123 | }; | |
124 | ||
125 | gem1: ethernet@e000c000 { | |
126 | compatible = "cdns,gem"; | |
127 | reg = <0xe000c000 0x4000>; | |
128 | status = "disabled"; | |
129 | interrupts = <0 45 4>; | |
130 | clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>; | |
131 | clock-names = "pclk", "hclk", "tx_clk"; | |
132 | }; | |
133 | ||
3f7c7302 SB |
134 | sdhci0: ps7-sdhci@e0100000 { |
135 | compatible = "arasan,sdhci-8.9a"; | |
136 | status = "disabled"; | |
137 | clock-names = "clk_xin", "clk_ahb"; | |
138 | clocks = <&clkc 21>, <&clkc 32>; | |
139 | interrupt-parent = <&intc>; | |
140 | interrupts = <0 24 4>; | |
141 | reg = <0xe0100000 0x1000>; | |
142 | } ; | |
143 | ||
144 | sdhci1: ps7-sdhci@e0101000 { | |
145 | compatible = "arasan,sdhci-8.9a"; | |
146 | status = "disabled"; | |
147 | clock-names = "clk_xin", "clk_ahb"; | |
148 | clocks = <&clkc 22>, <&clkc 33>; | |
149 | interrupt-parent = <&intc>; | |
150 | interrupts = <0 47 4>; | |
151 | reg = <0xe0101000 0x1000>; | |
152 | } ; | |
153 | ||
0f586fbf | 154 | slcr: slcr@f8000000 { |
b0504e39 MS |
155 | #address-cells = <1>; |
156 | #size-cells = <1>; | |
016f4dca | 157 | compatible = "xlnx,zynq-slcr", "syscon"; |
0f586fbf | 158 | reg = <0xF8000000 0x1000>; |
b0504e39 MS |
159 | ranges; |
160 | clkc: clkc@100 { | |
161 | #clock-cells = <1>; | |
162 | compatible = "xlnx,ps7-clkc"; | |
163 | ps-clk-frequency = <33333333>; | |
164 | fclk-enable = <0>; | |
165 | clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x", | |
166 | "cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x", | |
167 | "dci", "lqspi", "smc", "pcap", "gem0", "gem1", | |
168 | "fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1", | |
169 | "sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1", | |
170 | "dma", "usb0_aper", "usb1_aper", "gem0_aper", | |
171 | "gem1_aper", "sdio0_aper", "sdio1_aper", | |
172 | "spi0_aper", "spi1_aper", "can0_aper", "can1_aper", | |
173 | "i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper", | |
174 | "gpio_aper", "lqspi_aper", "smc_aper", "swdt", | |
175 | "dbg_trc", "dbg_apb"; | |
176 | reg = <0x100 0x100>; | |
0f586fbf JC |
177 | }; |
178 | }; | |
91dc985c | 179 | |
fa94bd57 SB |
180 | global_timer: timer@f8f00200 { |
181 | compatible = "arm,cortex-a9-global-timer"; | |
182 | reg = <0xf8f00200 0x20>; | |
183 | interrupts = <1 11 0x301>; | |
184 | interrupt-parent = <&intc>; | |
185 | clocks = <&clkc 4>; | |
186 | }; | |
187 | ||
91dc985c | 188 | ttc0: ttc0@f8001000 { |
e932900a MS |
189 | interrupt-parent = <&intc>; |
190 | interrupts = < 0 10 4 0 11 4 0 12 4 >; | |
191 | compatible = "cdns,ttc"; | |
30e1e285 | 192 | clocks = <&clkc 6>; |
91dc985c | 193 | reg = <0xF8001000 0x1000>; |
91dc985c JC |
194 | }; |
195 | ||
196 | ttc1: ttc1@f8002000 { | |
e932900a MS |
197 | interrupt-parent = <&intc>; |
198 | interrupts = < 0 37 4 0 38 4 0 39 4 >; | |
199 | compatible = "cdns,ttc"; | |
30e1e285 | 200 | clocks = <&clkc 6>; |
91dc985c | 201 | reg = <0xF8002000 0x1000>; |
91dc985c | 202 | }; |
2f34e0a5 MS |
203 | scutimer: scutimer@f8f00600 { |
204 | interrupt-parent = <&intc>; | |
205 | interrupts = < 1 13 0x301 >; | |
206 | compatible = "arm,cortex-a9-twd-timer"; | |
207 | reg = < 0xf8f00600 0x20 >; | |
30e1e285 | 208 | clocks = <&clkc 4>; |
2f34e0a5 | 209 | } ; |
b85a3ef4 JL |
210 | }; |
211 | }; |