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b85a3ef4 JL |
1 | /* |
2 | * Copyright (C) 2011 Xilinx | |
3 | * | |
4 | * This software is licensed under the terms of the GNU General Public | |
5 | * License version 2, as published by the Free Software Foundation, and | |
6 | * may be copied, distributed, and modified under those terms. | |
7 | * | |
8 | * This program is distributed in the hope that it will be useful, | |
9 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
10 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
11 | * GNU General Public License for more details. | |
12 | */ | |
e06f1a9e | 13 | /include/ "skeleton.dtsi" |
b85a3ef4 | 14 | |
b85a3ef4 | 15 | / { |
e06f1a9e | 16 | compatible = "xlnx,zynq-7000"; |
b85a3ef4 JL |
17 | |
18 | amba { | |
19 | compatible = "simple-bus"; | |
20 | #address-cells = <1>; | |
21 | #size-cells = <1>; | |
e06f1a9e | 22 | interrupt-parent = <&intc>; |
b85a3ef4 JL |
23 | ranges; |
24 | ||
25 | intc: interrupt-controller@f8f01000 { | |
f447ed2d JC |
26 | compatible = "arm,cortex-a9-gic"; |
27 | #interrupt-cells = <3>; | |
28 | #address-cells = <1>; | |
b85a3ef4 | 29 | interrupt-controller; |
f447ed2d JC |
30 | reg = <0xF8F01000 0x1000>, |
31 | <0xF8F00100 0x100>; | |
b85a3ef4 JL |
32 | }; |
33 | ||
0fcfdbca JC |
34 | L2: cache-controller { |
35 | compatible = "arm,pl310-cache"; | |
36 | reg = <0xF8F02000 0x1000>; | |
37 | arm,data-latency = <2 3 2>; | |
38 | arm,tag-latency = <2 3 2>; | |
39 | cache-unified; | |
40 | cache-level = <2>; | |
41 | }; | |
42 | ||
b85a3ef4 JL |
43 | uart0: uart@e0000000 { |
44 | compatible = "xlnx,xuartps"; | |
45 | reg = <0xE0000000 0x1000>; | |
f447ed2d | 46 | interrupts = <0 27 4>; |
2326669c | 47 | clocks = <&uart_clk 0>; |
b85a3ef4 | 48 | }; |
78d6785d JC |
49 | |
50 | uart1: uart@e0001000 { | |
51 | compatible = "xlnx,xuartps"; | |
52 | reg = <0xE0001000 0x1000>; | |
53 | interrupts = <0 50 4>; | |
2326669c | 54 | clocks = <&uart_clk 1>; |
78d6785d | 55 | }; |
0f586fbf JC |
56 | |
57 | slcr: slcr@f8000000 { | |
58 | compatible = "xlnx,zynq-slcr"; | |
59 | reg = <0xF8000000 0x1000>; | |
60 | ||
61 | clocks { | |
62 | #address-cells = <1>; | |
63 | #size-cells = <0>; | |
64 | ||
65 | ps_clk: ps_clk { | |
66 | #clock-cells = <0>; | |
67 | compatible = "fixed-clock"; | |
68 | /* clock-frequency set in board-specific file */ | |
69 | clock-output-names = "ps_clk"; | |
70 | }; | |
71 | armpll: armpll { | |
72 | #clock-cells = <0>; | |
73 | compatible = "xlnx,zynq-pll"; | |
74 | clocks = <&ps_clk>; | |
75 | reg = <0x100 0x110>; | |
76 | clock-output-names = "armpll"; | |
77 | }; | |
78 | ddrpll: ddrpll { | |
79 | #clock-cells = <0>; | |
80 | compatible = "xlnx,zynq-pll"; | |
81 | clocks = <&ps_clk>; | |
82 | reg = <0x104 0x114>; | |
83 | clock-output-names = "ddrpll"; | |
84 | }; | |
85 | iopll: iopll { | |
86 | #clock-cells = <0>; | |
87 | compatible = "xlnx,zynq-pll"; | |
88 | clocks = <&ps_clk>; | |
89 | reg = <0x108 0x118>; | |
90 | clock-output-names = "iopll"; | |
91 | }; | |
92 | uart_clk: uart_clk { | |
93 | #clock-cells = <1>; | |
94 | compatible = "xlnx,zynq-periph-clock"; | |
95 | clocks = <&iopll &armpll &ddrpll>; | |
96 | reg = <0x154>; | |
97 | clock-output-names = "uart0_ref_clk", | |
98 | "uart1_ref_clk"; | |
99 | }; | |
100 | cpu_clk: cpu_clk { | |
101 | #clock-cells = <1>; | |
102 | compatible = "xlnx,zynq-cpu-clock"; | |
103 | clocks = <&iopll &armpll &ddrpll>; | |
104 | reg = <0x120 0x1C4>; | |
105 | clock-output-names = "cpu_6x4x", | |
106 | "cpu_3x2x", | |
107 | "cpu_2x", | |
108 | "cpu_1x"; | |
109 | }; | |
110 | }; | |
111 | }; | |
91dc985c JC |
112 | |
113 | ttc0: ttc0@f8001000 { | |
114 | #address-cells = <1>; | |
115 | #size-cells = <0>; | |
116 | compatible = "xlnx,ttc"; | |
117 | reg = <0xF8001000 0x1000>; | |
118 | clocks = <&cpu_clk 3>; | |
119 | clock-names = "cpu_1x"; | |
120 | clock-ranges; | |
121 | ||
122 | ttc0_0: ttc0.0 { | |
123 | status = "disabled"; | |
124 | reg = <0>; | |
125 | interrupts = <0 10 4>; | |
126 | }; | |
127 | ttc0_1: ttc0.1 { | |
128 | status = "disabled"; | |
129 | reg = <1>; | |
130 | interrupts = <0 11 4>; | |
131 | }; | |
132 | ttc0_2: ttc0.2 { | |
133 | status = "disabled"; | |
134 | reg = <2>; | |
135 | interrupts = <0 12 4>; | |
136 | }; | |
137 | }; | |
138 | ||
139 | ttc1: ttc1@f8002000 { | |
140 | #interrupt-parent = <&intc>; | |
141 | #address-cells = <1>; | |
142 | #size-cells = <0>; | |
143 | compatible = "xlnx,ttc"; | |
144 | reg = <0xF8002000 0x1000>; | |
145 | clocks = <&cpu_clk 3>; | |
146 | clock-names = "cpu_1x"; | |
147 | clock-ranges; | |
148 | ||
149 | ttc1_0: ttc1.0 { | |
150 | status = "disabled"; | |
151 | reg = <0>; | |
152 | interrupts = <0 37 4>; | |
153 | }; | |
154 | ttc1_1: ttc1.1 { | |
155 | status = "disabled"; | |
156 | reg = <1>; | |
157 | interrupts = <0 38 4>; | |
158 | }; | |
159 | ttc1_2: ttc1.2 { | |
160 | status = "disabled"; | |
161 | reg = <2>; | |
162 | interrupts = <0 39 4>; | |
163 | }; | |
164 | }; | |
b85a3ef4 JL |
165 | }; |
166 | }; |