[deliverable/linux.git] / arch / arm / boot / dts / zynq-zc702.dts

/*
 *  Copyright (C) 2011 - 2014 Xilinx
 *  Copyright (C) 2012 National Instruments Corp.
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */
/dts-v1/;
/include/ "zynq-7000.dtsi"

/ {
	model = "Zynq ZC702 Development Board";
	compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";

	aliases {
		ethernet0 = &gem0;
		i2c0 = &i2c0;
		serial0 = &uart1;
	};

	memory {
		device_type = "memory";
		reg = <0x0 0x40000000>;
	};

	chosen {
		bootargs = "console=ttyPS0,115200 earlyprintk";
	};

	leds {
		compatible = "gpio-leds";

		ds23 {
			label = "ds23";
			gpios = <&gpio0 10 0>;
			linux,default-trigger = "heartbeat";
		};
	};

	usb_phy0: phy0 {
		compatible = "usb-nop-xceiv";
		#phy-cells = <0>;
	};
};

&can0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_can0_default>;
};

&clkc {
	ps-clk-frequency = <33333333>;
};

&gem0 {
	status = "okay";
	phy-mode = "rgmii-id";
	phy-handle = <&ethernet_phy>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gem0_default>;

	ethernet_phy: ethernet-phy@7 {
		reg = <7>;
	};
};

&gpio0 {
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_gpio0_default>;
};

&i2c0 {
	status = "okay";
	clock-frequency = <400000>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2c0_default>;

	i2cswitch@74 {
		compatible = "nxp,pca9548";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x74>;

		i2c@0 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <0>;
			si570: clock-generator@5d {
				#clock-cells = <0>;
				compatible = "silabs,si570";
				temperature-stability = <50>;
				reg = <0x5d>;
				factory-fout = <156250000>;
				clock-frequency = <148500000>;
			};
		};

		i2c@2 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <2>;
			eeprom@54 {
				compatible = "at,24c08";
				reg = <0x54>;
			};
		};

		i2c@3 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <3>;
			gpio@21 {
				compatible = "ti,tca6416";
				reg = <0x21>;
				gpio-controller;
				#gpio-cells = <2>;
			};
		};

		i2c@4 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <4>;
			rtc@51 {
				compatible = "nxp,pcf8563";
				reg = <0x51>;
			};
		};

		i2c@7 {
			#address-cells = <1>;
			#size-cells = <0>;
			reg = <7>;
			hwmon@52 {
				compatible = "ti,ucd9248";
				reg = <52>;
			};
			hwmon@53 {
				compatible = "ti,ucd9248";
				reg = <53>;
			};
			hwmon@54 {
				compatible = "ti,ucd9248";
				reg = <54>;
			};
		};
	};
};

&pinctrl0 {
	pinctrl_can0_default: can0-default {
		mux {
			function = "can0";
			groups = "can0_9_grp";
		};

		conf {
			groups = "can0_9_grp";
			slew-rate = <0>;
			io-standard = <1>;
		};

		conf-rx {
			pins = "MIO46";
			bias-high-impedance;
		};

		conf-tx {
			pins = "MIO47";
			bias-disable;
		};
	};

	pinctrl_gem0_default: gem0-default {
		mux {
			function = "ethernet0";
			groups = "ethernet0_0_grp";
		};

		conf {
			groups = "ethernet0_0_grp";
			slew-rate = <0>;
			io-standard = <4>;
		};

		conf-rx {
			pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
			bias-high-impedance;
			low-power-disable;
		};

		conf-tx {
			pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
			bias-disable;
			low-power-enable;
		};

		mux-mdio {
			function = "mdio0";
			groups = "mdio0_0_grp";
		};

		conf-mdio {
			groups = "mdio0_0_grp";
			slew-rate = <0>;
			io-standard = <1>;
			bias-disable;
		};
	};

	pinctrl_gpio0_default: gpio0-default {
		mux {
			function = "gpio0";
			groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
				 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
				 "gpio0_13_grp", "gpio0_14_grp";
		};

		conf {
			groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
				 "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
				 "gpio0_13_grp", "gpio0_14_grp";
			slew-rate = <0>;
			io-standard = <1>;
		};

		conf-pull-up {
			pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
			bias-pull-up;
		};

		conf-pull-none {
			pins = "MIO7", "MIO8";
			bias-disable;
		};
	};

	pinctrl_i2c0_default: i2c0-default {
		mux {
			groups = "i2c0_10_grp";
			function = "i2c0";
		};

		conf {
			groups = "i2c0_10_grp";
			bias-pull-up;
			slew-rate = <0>;
			io-standard = <1>;
		};
	};

	pinctrl_sdhci0_default: sdhci0-default {
		mux {
			groups = "sdio0_2_grp";
			function = "sdio0";
		};

		conf {
			groups = "sdio0_2_grp";
			slew-rate = <0>;
			io-standard = <1>;
			bias-disable;
		};

		mux-cd {
			groups = "gpio0_0_grp";
			function = "sdio0_cd";
		};

		conf-cd {
			groups = "gpio0_0_grp";
			bias-high-impedance;
			bias-pull-up;
			slew-rate = <0>;
			io-standard = <1>;
		};

		mux-wp {
			groups = "gpio0_15_grp";
			function = "sdio0_wp";
		};

		conf-wp {
			groups = "gpio0_15_grp";
			bias-high-impedance;
			bias-pull-up;
			slew-rate = <0>;
			io-standard = <1>;
		};
	};

	pinctrl_uart1_default: uart1-default {
		mux {
			groups = "uart1_10_grp";
			function = "uart1";
		};

		conf {
			groups = "uart1_10_grp";
			slew-rate = <0>;
			io-standard = <1>;
		};

		conf-rx {
			pins = "MIO49";
			bias-high-impedance;
		};

		conf-tx {
			pins = "MIO48";
			bias-disable;
		};
	};

	pinctrl_usb0_default: usb0-default {
		mux {
			groups = "usb0_0_grp";
			function = "usb0";
		};

		conf {
			groups = "usb0_0_grp";
			slew-rate = <0>;
			io-standard = <1>;
		};

		conf-rx {
			pins = "MIO29", "MIO31", "MIO36";
			bias-high-impedance;
		};

		conf-tx {
			pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
			       "MIO35", "MIO37", "MIO38", "MIO39";
			bias-disable;
		};
	};
};

&sdhci0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_sdhci0_default>;
};

&uart1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_uart1_default>;
};

&usb0 {
	status = "okay";
	dr_mode = "host";
	usb-phy = <&usb_phy0>;
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_usb0_default>;
};
Commit	Line	Data
e06f1a9e	1	/*
aeb29453	2	* Copyright (C) 2011 - 2014 Xilinx
e06f1a9e JC	3	* Copyright (C) 2012 National Instruments Corp.
	4	*
	5	* This software is licensed under the terms of the GNU General Public
	6	* License version 2, as published by the Free Software Foundation, and
	7	* may be copied, distributed, and modified under those terms.
	8	*
	9	* This program is distributed in the hope that it will be useful,
	10	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	11	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	12	* GNU General Public License for more details.
	13	*/
	14	/dts-v1/;
	15	/include/ "zynq-7000.dtsi"
	16
	17	/ {
	18	model = "Zynq ZC702 Development Board";
	19	compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
	20
ab216ac5 MS	21	aliases {
	22	ethernet0 = &gem0;
	23	i2c0 = &i2c0;
	24	serial0 = &uart1;
	25	};
	26
e06f1a9e JC	27	memory {
	28	device_type = "memory";
	29	reg = <0x0 0x40000000>;
	30	};
	31
	32	chosen {
ec11ebcf	33	bootargs = "console=ttyPS0,115200 earlyprintk";
e06f1a9e JC	34	};
e06f1a9e JC	35
f8aa6867 ES	36	leds {
	37	compatible = "gpio-leds";
	38
	39	ds23 {
	40	label = "ds23";
	41	gpios = <&gpio0 10 0>;
	42	linux,default-trigger = "heartbeat";
	43	};
	44	};
1643b316 SB	45
	46	usb_phy0: phy0 {
	47	compatible = "usb-nop-xceiv";
	48	#phy-cells = <0>;
	49	};
e06f1a9e	50	};
ec11ebcf	51
fdf26183 MS	52	&can0 {
fdf26183 MS	53	status = "okay";
f52948ea SB	54	pinctrl-names = "default";
f52948ea SB	55	pinctrl-0 = <&pinctrl_can0_default>;
fdf26183 MS	56	};
fdf26183 MS	57
8c7634c0 PC	58	&clkc {
	59	ps-clk-frequency = <33333333>;
	60	};
	61
982264c3 ST	62	&gem0 {
982264c3 ST	63	status = "okay";
da45581e	64	phy-mode = "rgmii-id";
f62f4047	65	phy-handle = <&ethernet_phy>;
f52948ea SB	66	pinctrl-names = "default";
f52948ea SB	67	pinctrl-0 = <&pinctrl_gem0_default>;
f62f4047 SB	68
	69	ethernet_phy: ethernet-phy@7 {
	70	reg = <7>;
	71	};
982264c3 ST	72	};
982264c3 ST	73
f52948ea SB	74	&gpio0 {
	75	pinctrl-names = "default";
	76	pinctrl-0 = <&pinctrl_gpio0_default>;
	77	};
	78
0f6faa3f SB	79	&i2c0 {
	80	status = "okay";
	81	clock-frequency = <400000>;
f52948ea SB	82	pinctrl-names = "default";
f52948ea SB	83	pinctrl-0 = <&pinctrl_i2c0_default>;
0f6faa3f SB	84
	85	i2cswitch@74 {
	86	compatible = "nxp,pca9548";
	87	#address-cells = <1>;
	88	#size-cells = <0>;
	89	reg = <0x74>;
	90
	91	i2c@0 {
	92	#address-cells = <1>;
	93	#size-cells = <0>;
	94	reg = <0>;
	95	si570: clock-generator@5d {
	96	#clock-cells = <0>;
	97	compatible = "silabs,si570";
	98	temperature-stability = <50>;
	99	reg = <0x5d>;
	100	factory-fout = <156250000>;
	101	clock-frequency = <148500000>;
	102	};
	103	};
	104
	105	i2c@2 {
	106	#address-cells = <1>;
	107	#size-cells = <0>;
	108	reg = <2>;
	109	eeprom@54 {
	110	compatible = "at,24c08";
	111	reg = <0x54>;
	112	};
	113	};
	114
	115	i2c@3 {
	116	#address-cells = <1>;
	117	#size-cells = <0>;
	118	reg = <3>;
	119	gpio@21 {
	120	compatible = "ti,tca6416";
	121	reg = <0x21>;
	122	gpio-controller;
	123	#gpio-cells = <2>;
	124	};
	125	};
	126
	127	i2c@4 {
	128	#address-cells = <1>;
	129	#size-cells = <0>;
	130	reg = <4>;
	131	rtc@51 {
	132	compatible = "nxp,pcf8563";
	133	reg = <0x51>;
	134	};
	135	};
	136
	137	i2c@7 {
	138	#address-cells = <1>;
	139	#size-cells = <0>;
	140	reg = <7>;
	141	hwmon@52 {
	142	compatible = "ti,ucd9248";
	143	reg = <52>;
	144	};
	145	hwmon@53 {
	146	compatible = "ti,ucd9248";
	147	reg = <53>;
148	};
149	hwmon@54 {
150	compatible = "ti,ucd9248";
151	reg = <54>;
152	};
153	};
154	};
155	};
156
f52948ea SB	157	&pinctrl0 {
	158	pinctrl_can0_default: can0-default {
	159	mux {
	160	function = "can0";
	161	groups = "can0_9_grp";
	162	};
	163
	164	conf {
	165	groups = "can0_9_grp";
	166	slew-rate = <0>;
	167	io-standard = <1>;
	168	};
	169
	170	conf-rx {
	171	pins = "MIO46";
	172	bias-high-impedance;
	173	};
	174
	175	conf-tx {
	176	pins = "MIO47";
	177	bias-disable;
	178	};
	179	};
	180
	181	pinctrl_gem0_default: gem0-default {
	182	mux {
	183	function = "ethernet0";
	184	groups = "ethernet0_0_grp";
	185	};
	186
	187	conf {
	188	groups = "ethernet0_0_grp";
	189	slew-rate = <0>;
	190	io-standard = <4>;
	191	};
	192
	193	conf-rx {
	194	pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
	195	bias-high-impedance;
	196	low-power-disable;
	197	};
	198
	199	conf-tx {
	200	pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
	201	bias-disable;
	202	low-power-enable;
	203	};
	204
	205	mux-mdio {
	206	function = "mdio0";
	207	groups = "mdio0_0_grp";
	208	};
	209
	210	conf-mdio {
	211	groups = "mdio0_0_grp";
	212	slew-rate = <0>;
	213	io-standard = <1>;
	214	bias-disable;
	215	};
	216	};
	217
	218	pinctrl_gpio0_default: gpio0-default {
	219	mux {
	220	function = "gpio0";
221	groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
222	"gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
223	"gpio0_13_grp", "gpio0_14_grp";
224	};
225
226	conf {
227	groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
228	"gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
229	"gpio0_13_grp", "gpio0_14_grp";
230	slew-rate = <0>;
231	io-standard = <1>;
232	};
233
234	conf-pull-up {
235	pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
236	bias-pull-up;
237	};
238
239	conf-pull-none {
240	pins = "MIO7", "MIO8";
241	bias-disable;
242	};
243	};
244
245	pinctrl_i2c0_default: i2c0-default {
246	mux {
247	groups = "i2c0_10_grp";
248	function = "i2c0";
249	};
250
251	conf {
252	groups = "i2c0_10_grp";
253	bias-pull-up;
254	slew-rate = <0>;
255	io-standard = <1>;
256	};
257	};
258
259	pinctrl_sdhci0_default: sdhci0-default {
260	mux {
261	groups = "sdio0_2_grp";
262	function = "sdio0";
263	};
264
265	conf {
266	groups = "sdio0_2_grp";
267	slew-rate = <0>;
268	io-standard = <1>;
269	bias-disable;
270	};
271
272	mux-cd {
273	groups = "gpio0_0_grp";
274	function = "sdio0_cd";
275	};
276
277	conf-cd {
278	groups = "gpio0_0_grp";
279	bias-high-impedance;
280	bias-pull-up;
281	slew-rate = <0>;
282	io-standard = <1>;
283	};
284
285	mux-wp {
286	groups = "gpio0_15_grp";
287	function = "sdio0_wp";
288	};
289
290	conf-wp {
291	groups = "gpio0_15_grp";
292	bias-high-impedance;
293	bias-pull-up;
294	slew-rate = <0>;
295	io-standard = <1>;
296	};
297	};
298
299	pinctrl_uart1_default: uart1-default {
300	mux {
301	groups = "uart1_10_grp";
302	function = "uart1";
303	};
304
305	conf {
306	groups = "uart1_10_grp";
307	slew-rate = <0>;
308	io-standard = <1>;
309	};
310
311	conf-rx {
312	pins = "MIO49";
313	bias-high-impedance;
314	};
315
316	conf-tx {
317	pins = "MIO48";
38c735f3	318	bias-disable;
f52948ea SB	319	};
f52948ea SB	320	};
0c79b9fe SB	321
	322	pinctrl_usb0_default: usb0-default {
	323	mux {
	324	groups = "usb0_0_grp";
	325	function = "usb0";
	326	};
	327
	328	conf {
	329	groups = "usb0_0_grp";
	330	slew-rate = <0>;
	331	io-standard = <1>;
	332	};
	333
	334	conf-rx {
	335	pins = "MIO29", "MIO31", "MIO36";
	336	bias-high-impedance;
	337	};
	338
	339	conf-tx {
	340	pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
	341	"MIO35", "MIO37", "MIO38", "MIO39";
	342	bias-disable;
	343	};
	344	};
f52948ea SB	345	};
f52948ea SB	346
3f7c7302 SB	347	&sdhci0 {
3f7c7302 SB	348	status = "okay";
f52948ea SB	349	pinctrl-names = "default";
f52948ea SB	350	pinctrl-0 = <&pinctrl_sdhci0_default>;
3f7c7302 SB	351	};
3f7c7302 SB	352
ec11ebcf SB	353	&uart1 {
ec11ebcf SB	354	status = "okay";
f52948ea SB	355	pinctrl-names = "default";
f52948ea SB	356	pinctrl-0 = <&pinctrl_uart1_default>;
ec11ebcf	357	};
1643b316 SB	358
	359	&usb0 {
	360	status = "okay";
	361	dr_mode = "host";
	362	usb-phy = <&usb_phy0>;
0c79b9fe SB	363	pinctrl-names = "default";
0c79b9fe SB	364	pinctrl-0 = <&pinctrl_usb0_default>;
1643b316	365	};