Commit | Line | Data |
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a4768d22 KH |
1 | /* |
2 | * EDMA3 support for DaVinci | |
3 | * | |
4 | * Copyright (C) 2006-2009 Texas Instruments. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. | |
19 | */ | |
e7eff702 | 20 | #include <linux/err.h> |
a4768d22 | 21 | #include <linux/kernel.h> |
a4768d22 KH |
22 | #include <linux/init.h> |
23 | #include <linux/module.h> | |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/platform_device.h> | |
a4768d22 | 26 | #include <linux/io.h> |
5a0e3ad6 | 27 | #include <linux/slab.h> |
6cba4355 | 28 | #include <linux/edma.h> |
6cba4355 MP |
29 | #include <linux/of_address.h> |
30 | #include <linux/of_device.h> | |
31 | #include <linux/of_dma.h> | |
32 | #include <linux/of_irq.h> | |
33 | #include <linux/pm_runtime.h> | |
a4768d22 | 34 | |
3ad7a42d | 35 | #include <linux/platform_data/edma.h> |
a4768d22 KH |
36 | |
37 | /* Offsets matching "struct edmacc_param" */ | |
38 | #define PARM_OPT 0x00 | |
39 | #define PARM_SRC 0x04 | |
40 | #define PARM_A_B_CNT 0x08 | |
41 | #define PARM_DST 0x0c | |
42 | #define PARM_SRC_DST_BIDX 0x10 | |
43 | #define PARM_LINK_BCNTRLD 0x14 | |
44 | #define PARM_SRC_DST_CIDX 0x18 | |
45 | #define PARM_CCNT 0x1c | |
46 | ||
47 | #define PARM_SIZE 0x20 | |
48 | ||
49 | /* Offsets for EDMA CC global channel registers and their shadows */ | |
50 | #define SH_ER 0x00 /* 64 bits */ | |
51 | #define SH_ECR 0x08 /* 64 bits */ | |
52 | #define SH_ESR 0x10 /* 64 bits */ | |
53 | #define SH_CER 0x18 /* 64 bits */ | |
54 | #define SH_EER 0x20 /* 64 bits */ | |
55 | #define SH_EECR 0x28 /* 64 bits */ | |
56 | #define SH_EESR 0x30 /* 64 bits */ | |
57 | #define SH_SER 0x38 /* 64 bits */ | |
58 | #define SH_SECR 0x40 /* 64 bits */ | |
59 | #define SH_IER 0x50 /* 64 bits */ | |
60 | #define SH_IECR 0x58 /* 64 bits */ | |
61 | #define SH_IESR 0x60 /* 64 bits */ | |
62 | #define SH_IPR 0x68 /* 64 bits */ | |
63 | #define SH_ICR 0x70 /* 64 bits */ | |
64 | #define SH_IEVAL 0x78 | |
65 | #define SH_QER 0x80 | |
66 | #define SH_QEER 0x84 | |
67 | #define SH_QEECR 0x88 | |
68 | #define SH_QEESR 0x8c | |
69 | #define SH_QSER 0x90 | |
70 | #define SH_QSECR 0x94 | |
71 | #define SH_SIZE 0x200 | |
72 | ||
73 | /* Offsets for EDMA CC global registers */ | |
74 | #define EDMA_REV 0x0000 | |
75 | #define EDMA_CCCFG 0x0004 | |
76 | #define EDMA_QCHMAP 0x0200 /* 8 registers */ | |
77 | #define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */ | |
78 | #define EDMA_QDMAQNUM 0x0260 | |
79 | #define EDMA_QUETCMAP 0x0280 | |
80 | #define EDMA_QUEPRI 0x0284 | |
81 | #define EDMA_EMR 0x0300 /* 64 bits */ | |
82 | #define EDMA_EMCR 0x0308 /* 64 bits */ | |
83 | #define EDMA_QEMR 0x0310 | |
84 | #define EDMA_QEMCR 0x0314 | |
85 | #define EDMA_CCERR 0x0318 | |
86 | #define EDMA_CCERRCLR 0x031c | |
87 | #define EDMA_EEVAL 0x0320 | |
88 | #define EDMA_DRAE 0x0340 /* 4 x 64 bits*/ | |
89 | #define EDMA_QRAE 0x0380 /* 4 registers */ | |
90 | #define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */ | |
91 | #define EDMA_QSTAT 0x0600 /* 2 registers */ | |
92 | #define EDMA_QWMTHRA 0x0620 | |
93 | #define EDMA_QWMTHRB 0x0624 | |
94 | #define EDMA_CCSTAT 0x0640 | |
95 | ||
96 | #define EDMA_M 0x1000 /* global channel registers */ | |
97 | #define EDMA_ECR 0x1008 | |
98 | #define EDMA_ECRH 0x100C | |
99 | #define EDMA_SHADOW0 0x2000 /* 4 regions shadowing global channels */ | |
100 | #define EDMA_PARM 0x4000 /* 128 param entries */ | |
101 | ||
a4768d22 KH |
102 | #define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5)) |
103 | ||
60902a2c SR |
104 | #define EDMA_DCHMAP 0x0100 /* 64 registers */ |
105 | #define CHMAP_EXIST BIT(24) | |
106 | ||
a4768d22 KH |
107 | #define EDMA_MAX_DMACH 64 |
108 | #define EDMA_MAX_PARAMENTRY 512 | |
a4768d22 KH |
109 | |
110 | /*****************************************************************************/ | |
111 | ||
60902a2c | 112 | static void __iomem *edmacc_regs_base[EDMA_MAX_CC]; |
a4768d22 | 113 | |
60902a2c | 114 | static inline unsigned int edma_read(unsigned ctlr, int offset) |
a4768d22 | 115 | { |
60902a2c | 116 | return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset); |
a4768d22 KH |
117 | } |
118 | ||
60902a2c | 119 | static inline void edma_write(unsigned ctlr, int offset, int val) |
a4768d22 | 120 | { |
60902a2c | 121 | __raw_writel(val, edmacc_regs_base[ctlr] + offset); |
a4768d22 | 122 | } |
60902a2c SR |
123 | static inline void edma_modify(unsigned ctlr, int offset, unsigned and, |
124 | unsigned or) | |
a4768d22 | 125 | { |
60902a2c | 126 | unsigned val = edma_read(ctlr, offset); |
a4768d22 KH |
127 | val &= and; |
128 | val |= or; | |
60902a2c | 129 | edma_write(ctlr, offset, val); |
a4768d22 | 130 | } |
60902a2c | 131 | static inline void edma_and(unsigned ctlr, int offset, unsigned and) |
a4768d22 | 132 | { |
60902a2c | 133 | unsigned val = edma_read(ctlr, offset); |
a4768d22 | 134 | val &= and; |
60902a2c | 135 | edma_write(ctlr, offset, val); |
a4768d22 | 136 | } |
60902a2c | 137 | static inline void edma_or(unsigned ctlr, int offset, unsigned or) |
a4768d22 | 138 | { |
60902a2c | 139 | unsigned val = edma_read(ctlr, offset); |
a4768d22 | 140 | val |= or; |
60902a2c | 141 | edma_write(ctlr, offset, val); |
a4768d22 | 142 | } |
60902a2c | 143 | static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i) |
a4768d22 | 144 | { |
60902a2c | 145 | return edma_read(ctlr, offset + (i << 2)); |
a4768d22 | 146 | } |
60902a2c SR |
147 | static inline void edma_write_array(unsigned ctlr, int offset, int i, |
148 | unsigned val) | |
a4768d22 | 149 | { |
60902a2c | 150 | edma_write(ctlr, offset + (i << 2), val); |
a4768d22 | 151 | } |
60902a2c | 152 | static inline void edma_modify_array(unsigned ctlr, int offset, int i, |
a4768d22 KH |
153 | unsigned and, unsigned or) |
154 | { | |
60902a2c | 155 | edma_modify(ctlr, offset + (i << 2), and, or); |
a4768d22 | 156 | } |
60902a2c | 157 | static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or) |
a4768d22 | 158 | { |
60902a2c | 159 | edma_or(ctlr, offset + (i << 2), or); |
a4768d22 | 160 | } |
60902a2c SR |
161 | static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j, |
162 | unsigned or) | |
a4768d22 | 163 | { |
60902a2c | 164 | edma_or(ctlr, offset + ((i*2 + j) << 2), or); |
a4768d22 | 165 | } |
60902a2c SR |
166 | static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j, |
167 | unsigned val) | |
a4768d22 | 168 | { |
60902a2c | 169 | edma_write(ctlr, offset + ((i*2 + j) << 2), val); |
a4768d22 | 170 | } |
60902a2c | 171 | static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset) |
a4768d22 | 172 | { |
60902a2c | 173 | return edma_read(ctlr, EDMA_SHADOW0 + offset); |
a4768d22 | 174 | } |
60902a2c SR |
175 | static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset, |
176 | int i) | |
a4768d22 | 177 | { |
60902a2c | 178 | return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2)); |
a4768d22 | 179 | } |
60902a2c | 180 | static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val) |
a4768d22 | 181 | { |
60902a2c | 182 | edma_write(ctlr, EDMA_SHADOW0 + offset, val); |
a4768d22 | 183 | } |
60902a2c SR |
184 | static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i, |
185 | unsigned val) | |
a4768d22 | 186 | { |
60902a2c | 187 | edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val); |
a4768d22 | 188 | } |
60902a2c SR |
189 | static inline unsigned int edma_parm_read(unsigned ctlr, int offset, |
190 | int param_no) | |
a4768d22 | 191 | { |
60902a2c | 192 | return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5)); |
a4768d22 | 193 | } |
60902a2c SR |
194 | static inline void edma_parm_write(unsigned ctlr, int offset, int param_no, |
195 | unsigned val) | |
a4768d22 | 196 | { |
60902a2c | 197 | edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val); |
a4768d22 | 198 | } |
60902a2c | 199 | static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no, |
a4768d22 KH |
200 | unsigned and, unsigned or) |
201 | { | |
60902a2c | 202 | edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or); |
a4768d22 | 203 | } |
60902a2c SR |
204 | static inline void edma_parm_and(unsigned ctlr, int offset, int param_no, |
205 | unsigned and) | |
a4768d22 | 206 | { |
60902a2c | 207 | edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and); |
a4768d22 | 208 | } |
60902a2c SR |
209 | static inline void edma_parm_or(unsigned ctlr, int offset, int param_no, |
210 | unsigned or) | |
a4768d22 | 211 | { |
60902a2c | 212 | edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or); |
a4768d22 KH |
213 | } |
214 | ||
90bd4e6d RS |
215 | static inline void set_bits(int offset, int len, unsigned long *p) |
216 | { | |
217 | for (; len > 0; len--) | |
218 | set_bit(offset + (len - 1), p); | |
219 | } | |
220 | ||
221 | static inline void clear_bits(int offset, int len, unsigned long *p) | |
222 | { | |
223 | for (; len > 0; len--) | |
224 | clear_bit(offset + (len - 1), p); | |
225 | } | |
226 | ||
a4768d22 KH |
227 | /*****************************************************************************/ |
228 | ||
229 | /* actual number of DMA channels and slots on this silicon */ | |
60902a2c SR |
230 | struct edma { |
231 | /* how many dma resources of each type */ | |
232 | unsigned num_channels; | |
233 | unsigned num_region; | |
234 | unsigned num_slots; | |
235 | unsigned num_tc; | |
236 | unsigned num_cc; | |
a0f0202e | 237 | enum dma_event_q default_queue; |
60902a2c SR |
238 | |
239 | /* list of channels with no even trigger; terminated by "-1" */ | |
240 | const s8 *noevent; | |
241 | ||
242 | /* The edma_inuse bit for each PaRAM slot is clear unless the | |
243 | * channel is in use ... by ARM or DSP, for QDMA, or whatever. | |
244 | */ | |
245 | DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY); | |
a4768d22 | 246 | |
f900d552 SR |
247 | /* The edma_unused bit for each channel is clear unless |
248 | * it is not being used on this platform. It uses a bit | |
249 | * of SOC-specific initialization code. | |
60902a2c | 250 | */ |
f900d552 | 251 | DECLARE_BITMAP(edma_unused, EDMA_MAX_DMACH); |
a4768d22 | 252 | |
60902a2c SR |
253 | unsigned irq_res_start; |
254 | unsigned irq_res_end; | |
a4768d22 | 255 | |
60902a2c SR |
256 | struct dma_interrupt_data { |
257 | void (*callback)(unsigned channel, unsigned short ch_status, | |
258 | void *data); | |
259 | void *data; | |
260 | } intr_data[EDMA_MAX_DMACH]; | |
261 | }; | |
262 | ||
3f68b98a | 263 | static struct edma *edma_cc[EDMA_MAX_CC]; |
2d517508 | 264 | static int arch_num_cc; |
a4768d22 KH |
265 | |
266 | /* dummy param set used to (re)initialize parameter RAM slots */ | |
267 | static const struct edmacc_param dummy_paramset = { | |
268 | .link_bcntrld = 0xffff, | |
269 | .ccnt = 1, | |
270 | }; | |
271 | ||
a4768d22 KH |
272 | /*****************************************************************************/ |
273 | ||
60902a2c SR |
274 | static void map_dmach_queue(unsigned ctlr, unsigned ch_no, |
275 | enum dma_event_q queue_no) | |
a4768d22 KH |
276 | { |
277 | int bit = (ch_no & 0x7) * 4; | |
278 | ||
279 | /* default to low priority queue */ | |
280 | if (queue_no == EVENTQ_DEFAULT) | |
3f68b98a | 281 | queue_no = edma_cc[ctlr]->default_queue; |
a4768d22 KH |
282 | |
283 | queue_no &= 7; | |
60902a2c | 284 | edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3), |
a4768d22 KH |
285 | ~(0x7 << bit), queue_no << bit); |
286 | } | |
287 | ||
60902a2c | 288 | static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no) |
a4768d22 KH |
289 | { |
290 | int bit = queue_no * 4; | |
60902a2c | 291 | edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit)); |
a4768d22 KH |
292 | } |
293 | ||
60902a2c SR |
294 | static void __init assign_priority_to_queue(unsigned ctlr, int queue_no, |
295 | int priority) | |
a4768d22 KH |
296 | { |
297 | int bit = queue_no * 4; | |
60902a2c SR |
298 | edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit), |
299 | ((priority & 0x7) << bit)); | |
300 | } | |
301 | ||
302 | /** | |
303 | * map_dmach_param - Maps channel number to param entry number | |
304 | * | |
305 | * This maps the dma channel number to param entry numberter. In | |
306 | * other words using the DMA channel mapping registers a param entry | |
307 | * can be mapped to any channel | |
308 | * | |
309 | * Callers are responsible for ensuring the channel mapping logic is | |
310 | * included in that particular EDMA variant (Eg : dm646x) | |
311 | * | |
312 | */ | |
313 | static void __init map_dmach_param(unsigned ctlr) | |
314 | { | |
315 | int i; | |
316 | for (i = 0; i < EDMA_MAX_DMACH; i++) | |
317 | edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5)); | |
a4768d22 KH |
318 | } |
319 | ||
320 | static inline void | |
321 | setup_dma_interrupt(unsigned lch, | |
322 | void (*callback)(unsigned channel, u16 ch_status, void *data), | |
323 | void *data) | |
324 | { | |
60902a2c SR |
325 | unsigned ctlr; |
326 | ||
327 | ctlr = EDMA_CTLR(lch); | |
328 | lch = EDMA_CHAN_SLOT(lch); | |
329 | ||
243bc654 | 330 | if (!callback) |
60902a2c | 331 | edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5, |
d78a9494 | 332 | BIT(lch & 0x1f)); |
a4768d22 | 333 | |
3f68b98a SN |
334 | edma_cc[ctlr]->intr_data[lch].callback = callback; |
335 | edma_cc[ctlr]->intr_data[lch].data = data; | |
a4768d22 KH |
336 | |
337 | if (callback) { | |
60902a2c | 338 | edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5, |
d78a9494 | 339 | BIT(lch & 0x1f)); |
60902a2c | 340 | edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5, |
d78a9494 | 341 | BIT(lch & 0x1f)); |
a4768d22 KH |
342 | } |
343 | } | |
344 | ||
60902a2c SR |
345 | static int irq2ctlr(int irq) |
346 | { | |
3f68b98a | 347 | if (irq >= edma_cc[0]->irq_res_start && irq <= edma_cc[0]->irq_res_end) |
60902a2c | 348 | return 0; |
3f68b98a SN |
349 | else if (irq >= edma_cc[1]->irq_res_start && |
350 | irq <= edma_cc[1]->irq_res_end) | |
60902a2c SR |
351 | return 1; |
352 | ||
353 | return -1; | |
354 | } | |
355 | ||
a4768d22 KH |
356 | /****************************************************************************** |
357 | * | |
358 | * DMA interrupt handler | |
359 | * | |
360 | *****************************************************************************/ | |
361 | static irqreturn_t dma_irq_handler(int irq, void *data) | |
362 | { | |
93fe23d8 | 363 | int ctlr; |
bcd59b0f SAS |
364 | u32 sh_ier; |
365 | u32 sh_ipr; | |
366 | u32 bank; | |
a4768d22 | 367 | |
60902a2c | 368 | ctlr = irq2ctlr(irq); |
93fe23d8 KV |
369 | if (ctlr < 0) |
370 | return IRQ_NONE; | |
60902a2c | 371 | |
a4768d22 KH |
372 | dev_dbg(data, "dma_irq_handler\n"); |
373 | ||
bcd59b0f SAS |
374 | sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 0); |
375 | if (!sh_ipr) { | |
376 | sh_ipr = edma_shadow0_read_array(ctlr, SH_IPR, 1); | |
377 | if (!sh_ipr) | |
378 | return IRQ_NONE; | |
379 | sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 1); | |
380 | bank = 1; | |
381 | } else { | |
382 | sh_ier = edma_shadow0_read_array(ctlr, SH_IER, 0); | |
383 | bank = 0; | |
384 | } | |
385 | ||
386 | do { | |
387 | u32 slot; | |
388 | u32 channel; | |
a4768d22 | 389 | |
bcd59b0f SAS |
390 | dev_dbg(data, "IPR%d %08x\n", bank, sh_ipr); |
391 | ||
392 | slot = __ffs(sh_ipr); | |
393 | sh_ipr &= ~(BIT(slot)); | |
394 | ||
395 | if (sh_ier & BIT(slot)) { | |
396 | channel = (bank << 5) | slot; | |
397 | /* Clear the corresponding IPR bits */ | |
398 | edma_shadow0_write_array(ctlr, SH_ICR, bank, | |
399 | BIT(slot)); | |
400 | if (edma_cc[ctlr]->intr_data[channel].callback) | |
401 | edma_cc[ctlr]->intr_data[channel].callback( | |
402 | channel, DMA_COMPLETE, | |
403 | edma_cc[ctlr]->intr_data[channel].data); | |
a4768d22 | 404 | } |
bcd59b0f SAS |
405 | } while (sh_ipr); |
406 | ||
60902a2c | 407 | edma_shadow0_write(ctlr, SH_IEVAL, 1); |
a4768d22 KH |
408 | return IRQ_HANDLED; |
409 | } | |
410 | ||
411 | /****************************************************************************** | |
412 | * | |
413 | * DMA error interrupt handler | |
414 | * | |
415 | *****************************************************************************/ | |
416 | static irqreturn_t dma_ccerr_handler(int irq, void *data) | |
417 | { | |
418 | int i; | |
93fe23d8 | 419 | int ctlr; |
a4768d22 KH |
420 | unsigned int cnt = 0; |
421 | ||
60902a2c | 422 | ctlr = irq2ctlr(irq); |
93fe23d8 KV |
423 | if (ctlr < 0) |
424 | return IRQ_NONE; | |
60902a2c | 425 | |
a4768d22 KH |
426 | dev_dbg(data, "dma_ccerr_handler\n"); |
427 | ||
60902a2c SR |
428 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && |
429 | (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && | |
430 | (edma_read(ctlr, EDMA_QEMR) == 0) && | |
431 | (edma_read(ctlr, EDMA_CCERR) == 0)) | |
a4768d22 KH |
432 | return IRQ_NONE; |
433 | ||
434 | while (1) { | |
435 | int j = -1; | |
60902a2c | 436 | if (edma_read_array(ctlr, EDMA_EMR, 0)) |
a4768d22 | 437 | j = 0; |
60902a2c | 438 | else if (edma_read_array(ctlr, EDMA_EMR, 1)) |
a4768d22 KH |
439 | j = 1; |
440 | if (j >= 0) { | |
441 | dev_dbg(data, "EMR%d %08x\n", j, | |
60902a2c | 442 | edma_read_array(ctlr, EDMA_EMR, j)); |
a4768d22 KH |
443 | for (i = 0; i < 32; i++) { |
444 | int k = (j << 5) + i; | |
60902a2c | 445 | if (edma_read_array(ctlr, EDMA_EMR, j) & |
d78a9494 | 446 | BIT(i)) { |
a4768d22 | 447 | /* Clear the corresponding EMR bits */ |
60902a2c | 448 | edma_write_array(ctlr, EDMA_EMCR, j, |
d78a9494 | 449 | BIT(i)); |
a4768d22 | 450 | /* Clear any SER */ |
60902a2c | 451 | edma_shadow0_write_array(ctlr, SH_SECR, |
d78a9494 | 452 | j, BIT(i)); |
3f68b98a | 453 | if (edma_cc[ctlr]->intr_data[k]. |
60902a2c | 454 | callback) { |
3f68b98a | 455 | edma_cc[ctlr]->intr_data[k]. |
60902a2c SR |
456 | callback(k, |
457 | DMA_CC_ERROR, | |
3f68b98a | 458 | edma_cc[ctlr]->intr_data |
60902a2c | 459 | [k].data); |
a4768d22 KH |
460 | } |
461 | } | |
462 | } | |
60902a2c | 463 | } else if (edma_read(ctlr, EDMA_QEMR)) { |
a4768d22 | 464 | dev_dbg(data, "QEMR %02x\n", |
60902a2c | 465 | edma_read(ctlr, EDMA_QEMR)); |
a4768d22 | 466 | for (i = 0; i < 8; i++) { |
d78a9494 | 467 | if (edma_read(ctlr, EDMA_QEMR) & BIT(i)) { |
a4768d22 | 468 | /* Clear the corresponding IPR bits */ |
d78a9494 | 469 | edma_write(ctlr, EDMA_QEMCR, BIT(i)); |
60902a2c | 470 | edma_shadow0_write(ctlr, SH_QSECR, |
d78a9494 | 471 | BIT(i)); |
a4768d22 KH |
472 | |
473 | /* NOTE: not reported!! */ | |
474 | } | |
475 | } | |
60902a2c | 476 | } else if (edma_read(ctlr, EDMA_CCERR)) { |
a4768d22 | 477 | dev_dbg(data, "CCERR %08x\n", |
60902a2c | 478 | edma_read(ctlr, EDMA_CCERR)); |
a4768d22 KH |
479 | /* FIXME: CCERR.BIT(16) ignored! much better |
480 | * to just write CCERRCLR with CCERR value... | |
481 | */ | |
482 | for (i = 0; i < 8; i++) { | |
d78a9494 | 483 | if (edma_read(ctlr, EDMA_CCERR) & BIT(i)) { |
a4768d22 | 484 | /* Clear the corresponding IPR bits */ |
d78a9494 | 485 | edma_write(ctlr, EDMA_CCERRCLR, BIT(i)); |
a4768d22 KH |
486 | |
487 | /* NOTE: not reported!! */ | |
488 | } | |
489 | } | |
490 | } | |
a6374f53 SN |
491 | if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) && |
492 | (edma_read_array(ctlr, EDMA_EMR, 1) == 0) && | |
493 | (edma_read(ctlr, EDMA_QEMR) == 0) && | |
494 | (edma_read(ctlr, EDMA_CCERR) == 0)) | |
a4768d22 | 495 | break; |
a4768d22 KH |
496 | cnt++; |
497 | if (cnt > 10) | |
498 | break; | |
499 | } | |
60902a2c | 500 | edma_write(ctlr, EDMA_EEVAL, 1); |
a4768d22 KH |
501 | return IRQ_HANDLED; |
502 | } | |
503 | ||
134ce221 SP |
504 | static int reserve_contiguous_slots(int ctlr, unsigned int id, |
505 | unsigned int num_slots, | |
506 | unsigned int start_slot) | |
213765d7 SP |
507 | { |
508 | int i, j; | |
134ce221 SP |
509 | unsigned int count = num_slots; |
510 | int stop_slot = start_slot; | |
cc93fc3f | 511 | DECLARE_BITMAP(tmp_inuse, EDMA_MAX_PARAMENTRY); |
213765d7 | 512 | |
3f68b98a | 513 | for (i = start_slot; i < edma_cc[ctlr]->num_slots; ++i) { |
213765d7 | 514 | j = EDMA_CHAN_SLOT(i); |
3f68b98a | 515 | if (!test_and_set_bit(j, edma_cc[ctlr]->edma_inuse)) { |
cc93fc3f | 516 | /* Record our current beginning slot */ |
134ce221 SP |
517 | if (count == num_slots) |
518 | stop_slot = i; | |
cc93fc3f | 519 | |
213765d7 | 520 | count--; |
cc93fc3f SP |
521 | set_bit(j, tmp_inuse); |
522 | ||
213765d7 SP |
523 | if (count == 0) |
524 | break; | |
cc93fc3f SP |
525 | } else { |
526 | clear_bit(j, tmp_inuse); | |
527 | ||
528 | if (id == EDMA_CONT_PARAMS_FIXED_EXACT) { | |
134ce221 | 529 | stop_slot = i; |
cc93fc3f | 530 | break; |
243bc654 | 531 | } else { |
134ce221 | 532 | count = num_slots; |
243bc654 | 533 | } |
cc93fc3f | 534 | } |
213765d7 SP |
535 | } |
536 | ||
537 | /* | |
538 | * We have to clear any bits that we set | |
134ce221 SP |
539 | * if we run out parameter RAM slots, i.e we do find a set |
540 | * of contiguous parameter RAM slots but do not find the exact number | |
541 | * requested as we may reach the total number of parameter RAM slots | |
213765d7 | 542 | */ |
3f68b98a | 543 | if (i == edma_cc[ctlr]->num_slots) |
134ce221 | 544 | stop_slot = i; |
cc93fc3f | 545 | |
98e3b339 AM |
546 | j = start_slot; |
547 | for_each_set_bit_from(j, tmp_inuse, stop_slot) | |
548 | clear_bit(j, edma_cc[ctlr]->edma_inuse); | |
213765d7 | 549 | |
cc93fc3f | 550 | if (count) |
213765d7 | 551 | return -EBUSY; |
213765d7 | 552 | |
134ce221 | 553 | for (j = i - num_slots + 1; j <= i; ++j) |
213765d7 SP |
554 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(j), |
555 | &dummy_paramset, PARM_SIZE); | |
556 | ||
134ce221 | 557 | return EDMA_CTLR_CHAN(ctlr, i - num_slots + 1); |
213765d7 SP |
558 | } |
559 | ||
f900d552 SR |
560 | static int prepare_unused_channel_list(struct device *dev, void *data) |
561 | { | |
562 | struct platform_device *pdev = to_platform_device(dev); | |
563 | int i, ctlr; | |
564 | ||
565 | for (i = 0; i < pdev->num_resources; i++) { | |
566 | if ((pdev->resource[i].flags & IORESOURCE_DMA) && | |
567 | (int)pdev->resource[i].start >= 0) { | |
568 | ctlr = EDMA_CTLR(pdev->resource[i].start); | |
569 | clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start), | |
3f68b98a | 570 | edma_cc[ctlr]->edma_unused); |
f900d552 SR |
571 | } |
572 | } | |
573 | ||
574 | return 0; | |
575 | } | |
576 | ||
a4768d22 KH |
577 | /*-----------------------------------------------------------------------*/ |
578 | ||
f900d552 SR |
579 | static bool unused_chan_list_done; |
580 | ||
a4768d22 KH |
581 | /* Resource alloc/free: dma channels, parameter RAM slots */ |
582 | ||
583 | /** | |
584 | * edma_alloc_channel - allocate DMA channel and paired parameter RAM | |
585 | * @channel: specific channel to allocate; negative for "any unmapped channel" | |
586 | * @callback: optional; to be issued on DMA completion or errors | |
587 | * @data: passed to callback | |
588 | * @eventq_no: an EVENTQ_* constant, used to choose which Transfer | |
589 | * Controller (TC) executes requests using this channel. Use | |
590 | * EVENTQ_DEFAULT unless you really need a high priority queue. | |
591 | * | |
592 | * This allocates a DMA channel and its associated parameter RAM slot. | |
593 | * The parameter RAM is initialized to hold a dummy transfer. | |
594 | * | |
595 | * Normal use is to pass a specific channel number as @channel, to make | |
596 | * use of hardware events mapped to that channel. When the channel will | |
597 | * be used only for software triggering or event chaining, channels not | |
598 | * mapped to hardware events (or mapped to unused events) are preferable. | |
599 | * | |
600 | * DMA transfers start from a channel using edma_start(), or by | |
601 | * chaining. When the transfer described in that channel's parameter RAM | |
602 | * slot completes, that slot's data may be reloaded through a link. | |
603 | * | |
604 | * DMA errors are only reported to the @callback associated with the | |
605 | * channel driving that transfer, but transfer completion callbacks can | |
606 | * be sent to another channel under control of the TCC field in | |
607 | * the option word of the transfer's parameter RAM set. Drivers must not | |
608 | * use DMA transfer completion callbacks for channels they did not allocate. | |
609 | * (The same applies to TCC codes used in transfer chaining.) | |
610 | * | |
611 | * Returns the number of the channel, else negative errno. | |
612 | */ | |
613 | int edma_alloc_channel(int channel, | |
614 | void (*callback)(unsigned channel, u16 ch_status, void *data), | |
615 | void *data, | |
616 | enum dma_event_q eventq_no) | |
617 | { | |
447f18f1 | 618 | unsigned i, done = 0, ctlr = 0; |
f900d552 SR |
619 | int ret = 0; |
620 | ||
621 | if (!unused_chan_list_done) { | |
622 | /* | |
623 | * Scan all the platform devices to find out the EDMA channels | |
624 | * used and clear them in the unused list, making the rest | |
625 | * available for ARM usage. | |
626 | */ | |
627 | ret = bus_for_each_dev(&platform_bus_type, NULL, NULL, | |
628 | prepare_unused_channel_list); | |
629 | if (ret < 0) | |
630 | return ret; | |
631 | ||
632 | unused_chan_list_done = true; | |
633 | } | |
60902a2c SR |
634 | |
635 | if (channel >= 0) { | |
636 | ctlr = EDMA_CTLR(channel); | |
637 | channel = EDMA_CHAN_SLOT(channel); | |
638 | } | |
639 | ||
a4768d22 | 640 | if (channel < 0) { |
2d517508 | 641 | for (i = 0; i < arch_num_cc; i++) { |
60902a2c SR |
642 | channel = 0; |
643 | for (;;) { | |
3f68b98a SN |
644 | channel = find_next_bit(edma_cc[i]->edma_unused, |
645 | edma_cc[i]->num_channels, | |
60902a2c | 646 | channel); |
3f68b98a | 647 | if (channel == edma_cc[i]->num_channels) |
447f18f1 | 648 | break; |
60902a2c | 649 | if (!test_and_set_bit(channel, |
3f68b98a | 650 | edma_cc[i]->edma_inuse)) { |
60902a2c SR |
651 | done = 1; |
652 | ctlr = i; | |
653 | break; | |
654 | } | |
655 | channel++; | |
656 | } | |
657 | if (done) | |
a4768d22 | 658 | break; |
a4768d22 | 659 | } |
447f18f1 SR |
660 | if (!done) |
661 | return -ENOMEM; | |
3f68b98a | 662 | } else if (channel >= edma_cc[ctlr]->num_channels) { |
a4768d22 | 663 | return -EINVAL; |
3f68b98a | 664 | } else if (test_and_set_bit(channel, edma_cc[ctlr]->edma_inuse)) { |
a4768d22 KH |
665 | return -EBUSY; |
666 | } | |
667 | ||
668 | /* ensure access through shadow region 0 */ | |
d78a9494 | 669 | edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f)); |
a4768d22 KH |
670 | |
671 | /* ensure no events are pending */ | |
60902a2c SR |
672 | edma_stop(EDMA_CTLR_CHAN(ctlr, channel)); |
673 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), | |
a4768d22 KH |
674 | &dummy_paramset, PARM_SIZE); |
675 | ||
676 | if (callback) | |
60902a2c SR |
677 | setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel), |
678 | callback, data); | |
a4768d22 | 679 | |
60902a2c | 680 | map_dmach_queue(ctlr, channel, eventq_no); |
a4768d22 | 681 | |
0e6cb8d2 | 682 | return EDMA_CTLR_CHAN(ctlr, channel); |
a4768d22 KH |
683 | } |
684 | EXPORT_SYMBOL(edma_alloc_channel); | |
685 | ||
686 | ||
687 | /** | |
688 | * edma_free_channel - deallocate DMA channel | |
689 | * @channel: dma channel returned from edma_alloc_channel() | |
690 | * | |
691 | * This deallocates the DMA channel and associated parameter RAM slot | |
692 | * allocated by edma_alloc_channel(). | |
693 | * | |
694 | * Callers are responsible for ensuring the channel is inactive, and | |
695 | * will not be reactivated by linking, chaining, or software calls to | |
696 | * edma_start(). | |
697 | */ | |
698 | void edma_free_channel(unsigned channel) | |
699 | { | |
60902a2c SR |
700 | unsigned ctlr; |
701 | ||
702 | ctlr = EDMA_CTLR(channel); | |
703 | channel = EDMA_CHAN_SLOT(channel); | |
704 | ||
3f68b98a | 705 | if (channel >= edma_cc[ctlr]->num_channels) |
a4768d22 KH |
706 | return; |
707 | ||
708 | setup_dma_interrupt(channel, NULL, NULL); | |
709 | /* REVISIT should probably take out of shadow region 0 */ | |
710 | ||
60902a2c | 711 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel), |
a4768d22 | 712 | &dummy_paramset, PARM_SIZE); |
3f68b98a | 713 | clear_bit(channel, edma_cc[ctlr]->edma_inuse); |
a4768d22 KH |
714 | } |
715 | EXPORT_SYMBOL(edma_free_channel); | |
716 | ||
717 | /** | |
718 | * edma_alloc_slot - allocate DMA parameter RAM | |
719 | * @slot: specific slot to allocate; negative for "any unused slot" | |
720 | * | |
721 | * This allocates a parameter RAM slot, initializing it to hold a | |
722 | * dummy transfer. Slots allocated using this routine have not been | |
723 | * mapped to a hardware DMA channel, and will normally be used by | |
724 | * linking to them from a slot associated with a DMA channel. | |
725 | * | |
726 | * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific | |
727 | * slots may be allocated on behalf of DSP firmware. | |
728 | * | |
729 | * Returns the number of the slot, else negative errno. | |
730 | */ | |
60902a2c | 731 | int edma_alloc_slot(unsigned ctlr, int slot) |
a4768d22 | 732 | { |
06955277 MP |
733 | if (!edma_cc[ctlr]) |
734 | return -EINVAL; | |
735 | ||
60902a2c SR |
736 | if (slot >= 0) |
737 | slot = EDMA_CHAN_SLOT(slot); | |
738 | ||
a4768d22 | 739 | if (slot < 0) { |
3f68b98a | 740 | slot = edma_cc[ctlr]->num_channels; |
a4768d22 | 741 | for (;;) { |
3f68b98a SN |
742 | slot = find_next_zero_bit(edma_cc[ctlr]->edma_inuse, |
743 | edma_cc[ctlr]->num_slots, slot); | |
744 | if (slot == edma_cc[ctlr]->num_slots) | |
a4768d22 | 745 | return -ENOMEM; |
3f68b98a | 746 | if (!test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) |
a4768d22 KH |
747 | break; |
748 | } | |
3f68b98a SN |
749 | } else if (slot < edma_cc[ctlr]->num_channels || |
750 | slot >= edma_cc[ctlr]->num_slots) { | |
a4768d22 | 751 | return -EINVAL; |
3f68b98a | 752 | } else if (test_and_set_bit(slot, edma_cc[ctlr]->edma_inuse)) { |
a4768d22 KH |
753 | return -EBUSY; |
754 | } | |
755 | ||
60902a2c | 756 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
a4768d22 KH |
757 | &dummy_paramset, PARM_SIZE); |
758 | ||
60902a2c | 759 | return EDMA_CTLR_CHAN(ctlr, slot); |
a4768d22 KH |
760 | } |
761 | EXPORT_SYMBOL(edma_alloc_slot); | |
762 | ||
763 | /** | |
764 | * edma_free_slot - deallocate DMA parameter RAM | |
765 | * @slot: parameter RAM slot returned from edma_alloc_slot() | |
766 | * | |
767 | * This deallocates the parameter RAM slot allocated by edma_alloc_slot(). | |
768 | * Callers are responsible for ensuring the slot is inactive, and will | |
769 | * not be activated. | |
770 | */ | |
771 | void edma_free_slot(unsigned slot) | |
772 | { | |
60902a2c SR |
773 | unsigned ctlr; |
774 | ||
775 | ctlr = EDMA_CTLR(slot); | |
776 | slot = EDMA_CHAN_SLOT(slot); | |
777 | ||
3f68b98a SN |
778 | if (slot < edma_cc[ctlr]->num_channels || |
779 | slot >= edma_cc[ctlr]->num_slots) | |
a4768d22 KH |
780 | return; |
781 | ||
60902a2c | 782 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
a4768d22 | 783 | &dummy_paramset, PARM_SIZE); |
3f68b98a | 784 | clear_bit(slot, edma_cc[ctlr]->edma_inuse); |
a4768d22 KH |
785 | } |
786 | EXPORT_SYMBOL(edma_free_slot); | |
787 | ||
213765d7 SP |
788 | |
789 | /** | |
790 | * edma_alloc_cont_slots- alloc contiguous parameter RAM slots | |
791 | * The API will return the starting point of a set of | |
134ce221 | 792 | * contiguous parameter RAM slots that have been requested |
213765d7 SP |
793 | * |
794 | * @id: can only be EDMA_CONT_PARAMS_ANY or EDMA_CONT_PARAMS_FIXED_EXACT | |
795 | * or EDMA_CONT_PARAMS_FIXED_NOT_EXACT | |
134ce221 SP |
796 | * @count: number of contiguous Paramter RAM slots |
797 | * @slot - the start value of Parameter RAM slot that should be passed if id | |
213765d7 SP |
798 | * is EDMA_CONT_PARAMS_FIXED_EXACT or EDMA_CONT_PARAMS_FIXED_NOT_EXACT |
799 | * | |
800 | * If id is EDMA_CONT_PARAMS_ANY then the API starts looking for a set of | |
134ce221 SP |
801 | * contiguous Parameter RAM slots from parameter RAM 64 in the case of |
802 | * DaVinci SOCs and 32 in the case of DA8xx SOCs. | |
213765d7 SP |
803 | * |
804 | * If id is EDMA_CONT_PARAMS_FIXED_EXACT then the API starts looking for a | |
134ce221 | 805 | * set of contiguous parameter RAM slots from the "slot" that is passed as an |
213765d7 SP |
806 | * argument to the API. |
807 | * | |
808 | * If id is EDMA_CONT_PARAMS_FIXED_NOT_EXACT then the API initially tries | |
134ce221 | 809 | * starts looking for a set of contiguous parameter RAMs from the "slot" |
213765d7 | 810 | * that is passed as an argument to the API. On failure the API will try to |
134ce221 SP |
811 | * find a set of contiguous Parameter RAM slots from the remaining Parameter |
812 | * RAM slots | |
213765d7 SP |
813 | */ |
814 | int edma_alloc_cont_slots(unsigned ctlr, unsigned int id, int slot, int count) | |
815 | { | |
816 | /* | |
817 | * The start slot requested should be greater than | |
818 | * the number of channels and lesser than the total number | |
819 | * of slots | |
820 | */ | |
6b0cf4e9 | 821 | if ((id != EDMA_CONT_PARAMS_ANY) && |
3f68b98a SN |
822 | (slot < edma_cc[ctlr]->num_channels || |
823 | slot >= edma_cc[ctlr]->num_slots)) | |
213765d7 SP |
824 | return -EINVAL; |
825 | ||
826 | /* | |
134ce221 | 827 | * The number of parameter RAM slots requested cannot be less than 1 |
213765d7 SP |
828 | * and cannot be more than the number of slots minus the number of |
829 | * channels | |
830 | */ | |
831 | if (count < 1 || count > | |
3f68b98a | 832 | (edma_cc[ctlr]->num_slots - edma_cc[ctlr]->num_channels)) |
213765d7 SP |
833 | return -EINVAL; |
834 | ||
835 | switch (id) { | |
836 | case EDMA_CONT_PARAMS_ANY: | |
134ce221 | 837 | return reserve_contiguous_slots(ctlr, id, count, |
3f68b98a | 838 | edma_cc[ctlr]->num_channels); |
213765d7 SP |
839 | case EDMA_CONT_PARAMS_FIXED_EXACT: |
840 | case EDMA_CONT_PARAMS_FIXED_NOT_EXACT: | |
134ce221 | 841 | return reserve_contiguous_slots(ctlr, id, count, slot); |
213765d7 SP |
842 | default: |
843 | return -EINVAL; | |
844 | } | |
845 | ||
846 | } | |
847 | EXPORT_SYMBOL(edma_alloc_cont_slots); | |
848 | ||
849 | /** | |
134ce221 SP |
850 | * edma_free_cont_slots - deallocate DMA parameter RAM slots |
851 | * @slot: first parameter RAM of a set of parameter RAM slots to be freed | |
852 | * @count: the number of contiguous parameter RAM slots to be freed | |
213765d7 SP |
853 | * |
854 | * This deallocates the parameter RAM slots allocated by | |
855 | * edma_alloc_cont_slots. | |
856 | * Callers/applications need to keep track of sets of contiguous | |
134ce221 | 857 | * parameter RAM slots that have been allocated using the edma_alloc_cont_slots |
213765d7 SP |
858 | * API. |
859 | * Callers are responsible for ensuring the slots are inactive, and will | |
860 | * not be activated. | |
861 | */ | |
862 | int edma_free_cont_slots(unsigned slot, int count) | |
863 | { | |
51c99e04 | 864 | unsigned ctlr, slot_to_free; |
213765d7 SP |
865 | int i; |
866 | ||
867 | ctlr = EDMA_CTLR(slot); | |
868 | slot = EDMA_CHAN_SLOT(slot); | |
869 | ||
3f68b98a SN |
870 | if (slot < edma_cc[ctlr]->num_channels || |
871 | slot >= edma_cc[ctlr]->num_slots || | |
213765d7 SP |
872 | count < 1) |
873 | return -EINVAL; | |
874 | ||
875 | for (i = slot; i < slot + count; ++i) { | |
876 | ctlr = EDMA_CTLR(i); | |
51c99e04 | 877 | slot_to_free = EDMA_CHAN_SLOT(i); |
213765d7 | 878 | |
51c99e04 | 879 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot_to_free), |
213765d7 | 880 | &dummy_paramset, PARM_SIZE); |
3f68b98a | 881 | clear_bit(slot_to_free, edma_cc[ctlr]->edma_inuse); |
213765d7 SP |
882 | } |
883 | ||
884 | return 0; | |
885 | } | |
886 | EXPORT_SYMBOL(edma_free_cont_slots); | |
887 | ||
a4768d22 KH |
888 | /*-----------------------------------------------------------------------*/ |
889 | ||
890 | /* Parameter RAM operations (i) -- read/write partial slots */ | |
891 | ||
892 | /** | |
893 | * edma_set_src - set initial DMA source address in parameter RAM slot | |
894 | * @slot: parameter RAM slot being configured | |
895 | * @src_port: physical address of source (memory, controller FIFO, etc) | |
896 | * @addressMode: INCR, except in very rare cases | |
897 | * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the | |
898 | * width to use when addressing the fifo (e.g. W8BIT, W32BIT) | |
899 | * | |
900 | * Note that the source address is modified during the DMA transfer | |
901 | * according to edma_set_src_index(). | |
902 | */ | |
903 | void edma_set_src(unsigned slot, dma_addr_t src_port, | |
904 | enum address_mode mode, enum fifo_width width) | |
905 | { | |
60902a2c SR |
906 | unsigned ctlr; |
907 | ||
908 | ctlr = EDMA_CTLR(slot); | |
909 | slot = EDMA_CHAN_SLOT(slot); | |
910 | ||
3f68b98a | 911 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 912 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); |
a4768d22 KH |
913 | |
914 | if (mode) { | |
915 | /* set SAM and program FWID */ | |
916 | i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8)); | |
917 | } else { | |
918 | /* clear SAM */ | |
919 | i &= ~SAM; | |
920 | } | |
60902a2c | 921 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
a4768d22 KH |
922 | |
923 | /* set the source port address | |
924 | in source register of param structure */ | |
60902a2c | 925 | edma_parm_write(ctlr, PARM_SRC, slot, src_port); |
a4768d22 KH |
926 | } |
927 | } | |
928 | EXPORT_SYMBOL(edma_set_src); | |
929 | ||
930 | /** | |
931 | * edma_set_dest - set initial DMA destination address in parameter RAM slot | |
932 | * @slot: parameter RAM slot being configured | |
933 | * @dest_port: physical address of destination (memory, controller FIFO, etc) | |
934 | * @addressMode: INCR, except in very rare cases | |
935 | * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the | |
936 | * width to use when addressing the fifo (e.g. W8BIT, W32BIT) | |
937 | * | |
938 | * Note that the destination address is modified during the DMA transfer | |
939 | * according to edma_set_dest_index(). | |
940 | */ | |
941 | void edma_set_dest(unsigned slot, dma_addr_t dest_port, | |
942 | enum address_mode mode, enum fifo_width width) | |
943 | { | |
60902a2c SR |
944 | unsigned ctlr; |
945 | ||
946 | ctlr = EDMA_CTLR(slot); | |
947 | slot = EDMA_CHAN_SLOT(slot); | |
948 | ||
3f68b98a | 949 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 950 | unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot); |
a4768d22 KH |
951 | |
952 | if (mode) { | |
953 | /* set DAM and program FWID */ | |
954 | i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8)); | |
955 | } else { | |
956 | /* clear DAM */ | |
957 | i &= ~DAM; | |
958 | } | |
60902a2c | 959 | edma_parm_write(ctlr, PARM_OPT, slot, i); |
a4768d22 KH |
960 | /* set the destination port address |
961 | in dest register of param structure */ | |
60902a2c | 962 | edma_parm_write(ctlr, PARM_DST, slot, dest_port); |
a4768d22 KH |
963 | } |
964 | } | |
965 | EXPORT_SYMBOL(edma_set_dest); | |
966 | ||
967 | /** | |
968 | * edma_get_position - returns the current transfer points | |
969 | * @slot: parameter RAM slot being examined | |
970 | * @src: pointer to source port position | |
971 | * @dst: pointer to destination port position | |
972 | * | |
973 | * Returns current source and destination addresses for a particular | |
974 | * parameter RAM slot. Its channel should not be active when this is called. | |
975 | */ | |
976 | void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst) | |
977 | { | |
978 | struct edmacc_param temp; | |
60902a2c SR |
979 | unsigned ctlr; |
980 | ||
981 | ctlr = EDMA_CTLR(slot); | |
982 | slot = EDMA_CHAN_SLOT(slot); | |
a4768d22 | 983 | |
60902a2c | 984 | edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp); |
a4768d22 KH |
985 | if (src != NULL) |
986 | *src = temp.src; | |
987 | if (dst != NULL) | |
988 | *dst = temp.dst; | |
989 | } | |
990 | EXPORT_SYMBOL(edma_get_position); | |
991 | ||
992 | /** | |
993 | * edma_set_src_index - configure DMA source address indexing | |
994 | * @slot: parameter RAM slot being configured | |
995 | * @src_bidx: byte offset between source arrays in a frame | |
996 | * @src_cidx: byte offset between source frames in a block | |
997 | * | |
998 | * Offsets are specified to support either contiguous or discontiguous | |
999 | * memory transfers, or repeated access to a hardware register, as needed. | |
1000 | * When accessing hardware registers, both offsets are normally zero. | |
1001 | */ | |
1002 | void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx) | |
1003 | { | |
60902a2c SR |
1004 | unsigned ctlr; |
1005 | ||
1006 | ctlr = EDMA_CTLR(slot); | |
1007 | slot = EDMA_CHAN_SLOT(slot); | |
1008 | ||
3f68b98a | 1009 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 1010 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, |
a4768d22 | 1011 | 0xffff0000, src_bidx); |
60902a2c | 1012 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
a4768d22 KH |
1013 | 0xffff0000, src_cidx); |
1014 | } | |
1015 | } | |
1016 | EXPORT_SYMBOL(edma_set_src_index); | |
1017 | ||
1018 | /** | |
1019 | * edma_set_dest_index - configure DMA destination address indexing | |
1020 | * @slot: parameter RAM slot being configured | |
1021 | * @dest_bidx: byte offset between destination arrays in a frame | |
1022 | * @dest_cidx: byte offset between destination frames in a block | |
1023 | * | |
1024 | * Offsets are specified to support either contiguous or discontiguous | |
1025 | * memory transfers, or repeated access to a hardware register, as needed. | |
1026 | * When accessing hardware registers, both offsets are normally zero. | |
1027 | */ | |
1028 | void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx) | |
1029 | { | |
60902a2c SR |
1030 | unsigned ctlr; |
1031 | ||
1032 | ctlr = EDMA_CTLR(slot); | |
1033 | slot = EDMA_CHAN_SLOT(slot); | |
1034 | ||
3f68b98a | 1035 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 1036 | edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot, |
a4768d22 | 1037 | 0x0000ffff, dest_bidx << 16); |
60902a2c | 1038 | edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot, |
a4768d22 KH |
1039 | 0x0000ffff, dest_cidx << 16); |
1040 | } | |
1041 | } | |
1042 | EXPORT_SYMBOL(edma_set_dest_index); | |
1043 | ||
1044 | /** | |
1045 | * edma_set_transfer_params - configure DMA transfer parameters | |
1046 | * @slot: parameter RAM slot being configured | |
1047 | * @acnt: how many bytes per array (at least one) | |
1048 | * @bcnt: how many arrays per frame (at least one) | |
1049 | * @ccnt: how many frames per block (at least one) | |
1050 | * @bcnt_rld: used only for A-Synchronized transfers; this specifies | |
1051 | * the value to reload into bcnt when it decrements to zero | |
1052 | * @sync_mode: ASYNC or ABSYNC | |
1053 | * | |
1054 | * See the EDMA3 documentation to understand how to configure and link | |
1055 | * transfers using the fields in PaRAM slots. If you are not doing it | |
1056 | * all at once with edma_write_slot(), you will use this routine | |
1057 | * plus two calls each for source and destination, setting the initial | |
1058 | * address and saying how to index that address. | |
1059 | * | |
1060 | * An example of an A-Synchronized transfer is a serial link using a | |
1061 | * single word shift register. In that case, @acnt would be equal to | |
1062 | * that word size; the serial controller issues a DMA synchronization | |
1063 | * event to transfer each word, and memory access by the DMA transfer | |
1064 | * controller will be word-at-a-time. | |
1065 | * | |
1066 | * An example of an AB-Synchronized transfer is a device using a FIFO. | |
1067 | * In that case, @acnt equals the FIFO width and @bcnt equals its depth. | |
1068 | * The controller with the FIFO issues DMA synchronization events when | |
1069 | * the FIFO threshold is reached, and the DMA transfer controller will | |
1070 | * transfer one frame to (or from) the FIFO. It will probably use | |
1071 | * efficient burst modes to access memory. | |
1072 | */ | |
1073 | void edma_set_transfer_params(unsigned slot, | |
1074 | u16 acnt, u16 bcnt, u16 ccnt, | |
1075 | u16 bcnt_rld, enum sync_dimension sync_mode) | |
1076 | { | |
60902a2c SR |
1077 | unsigned ctlr; |
1078 | ||
1079 | ctlr = EDMA_CTLR(slot); | |
1080 | slot = EDMA_CHAN_SLOT(slot); | |
1081 | ||
3f68b98a | 1082 | if (slot < edma_cc[ctlr]->num_slots) { |
60902a2c | 1083 | edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot, |
a4768d22 KH |
1084 | 0x0000ffff, bcnt_rld << 16); |
1085 | if (sync_mode == ASYNC) | |
60902a2c | 1086 | edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM); |
a4768d22 | 1087 | else |
60902a2c | 1088 | edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM); |
a4768d22 | 1089 | /* Set the acount, bcount, ccount registers */ |
60902a2c SR |
1090 | edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt); |
1091 | edma_parm_write(ctlr, PARM_CCNT, slot, ccnt); | |
a4768d22 KH |
1092 | } |
1093 | } | |
1094 | EXPORT_SYMBOL(edma_set_transfer_params); | |
1095 | ||
1096 | /** | |
1097 | * edma_link - link one parameter RAM slot to another | |
1098 | * @from: parameter RAM slot originating the link | |
1099 | * @to: parameter RAM slot which is the link target | |
1100 | * | |
1101 | * The originating slot should not be part of any active DMA transfer. | |
1102 | */ | |
1103 | void edma_link(unsigned from, unsigned to) | |
1104 | { | |
60902a2c SR |
1105 | unsigned ctlr_from, ctlr_to; |
1106 | ||
1107 | ctlr_from = EDMA_CTLR(from); | |
1108 | from = EDMA_CHAN_SLOT(from); | |
1109 | ctlr_to = EDMA_CTLR(to); | |
1110 | to = EDMA_CHAN_SLOT(to); | |
1111 | ||
3f68b98a | 1112 | if (from >= edma_cc[ctlr_from]->num_slots) |
a4768d22 | 1113 | return; |
3f68b98a | 1114 | if (to >= edma_cc[ctlr_to]->num_slots) |
a4768d22 | 1115 | return; |
60902a2c SR |
1116 | edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000, |
1117 | PARM_OFFSET(to)); | |
a4768d22 KH |
1118 | } |
1119 | EXPORT_SYMBOL(edma_link); | |
1120 | ||
1121 | /** | |
1122 | * edma_unlink - cut link from one parameter RAM slot | |
1123 | * @from: parameter RAM slot originating the link | |
1124 | * | |
1125 | * The originating slot should not be part of any active DMA transfer. | |
1126 | * Its link is set to 0xffff. | |
1127 | */ | |
1128 | void edma_unlink(unsigned from) | |
1129 | { | |
60902a2c SR |
1130 | unsigned ctlr; |
1131 | ||
1132 | ctlr = EDMA_CTLR(from); | |
1133 | from = EDMA_CHAN_SLOT(from); | |
1134 | ||
3f68b98a | 1135 | if (from >= edma_cc[ctlr]->num_slots) |
a4768d22 | 1136 | return; |
60902a2c | 1137 | edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff); |
a4768d22 KH |
1138 | } |
1139 | EXPORT_SYMBOL(edma_unlink); | |
1140 | ||
1141 | /*-----------------------------------------------------------------------*/ | |
1142 | ||
1143 | /* Parameter RAM operations (ii) -- read/write whole parameter sets */ | |
1144 | ||
1145 | /** | |
1146 | * edma_write_slot - write parameter RAM data for slot | |
1147 | * @slot: number of parameter RAM slot being modified | |
1148 | * @param: data to be written into parameter RAM slot | |
1149 | * | |
1150 | * Use this to assign all parameters of a transfer at once. This | |
1151 | * allows more efficient setup of transfers than issuing multiple | |
1152 | * calls to set up those parameters in small pieces, and provides | |
1153 | * complete control over all transfer options. | |
1154 | */ | |
1155 | void edma_write_slot(unsigned slot, const struct edmacc_param *param) | |
1156 | { | |
60902a2c SR |
1157 | unsigned ctlr; |
1158 | ||
1159 | ctlr = EDMA_CTLR(slot); | |
1160 | slot = EDMA_CHAN_SLOT(slot); | |
1161 | ||
3f68b98a | 1162 | if (slot >= edma_cc[ctlr]->num_slots) |
a4768d22 | 1163 | return; |
60902a2c SR |
1164 | memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param, |
1165 | PARM_SIZE); | |
a4768d22 KH |
1166 | } |
1167 | EXPORT_SYMBOL(edma_write_slot); | |
1168 | ||
1169 | /** | |
1170 | * edma_read_slot - read parameter RAM data from slot | |
1171 | * @slot: number of parameter RAM slot being copied | |
1172 | * @param: where to store copy of parameter RAM data | |
1173 | * | |
1174 | * Use this to read data from a parameter RAM slot, perhaps to | |
1175 | * save them as a template for later reuse. | |
1176 | */ | |
1177 | void edma_read_slot(unsigned slot, struct edmacc_param *param) | |
1178 | { | |
60902a2c SR |
1179 | unsigned ctlr; |
1180 | ||
1181 | ctlr = EDMA_CTLR(slot); | |
1182 | slot = EDMA_CHAN_SLOT(slot); | |
1183 | ||
3f68b98a | 1184 | if (slot >= edma_cc[ctlr]->num_slots) |
a4768d22 | 1185 | return; |
60902a2c SR |
1186 | memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot), |
1187 | PARM_SIZE); | |
a4768d22 KH |
1188 | } |
1189 | EXPORT_SYMBOL(edma_read_slot); | |
1190 | ||
1191 | /*-----------------------------------------------------------------------*/ | |
1192 | ||
1193 | /* Various EDMA channel control operations */ | |
1194 | ||
1195 | /** | |
1196 | * edma_pause - pause dma on a channel | |
1197 | * @channel: on which edma_start() has been called | |
1198 | * | |
1199 | * This temporarily disables EDMA hardware events on the specified channel, | |
1200 | * preventing them from triggering new transfers on its behalf | |
1201 | */ | |
1202 | void edma_pause(unsigned channel) | |
1203 | { | |
60902a2c SR |
1204 | unsigned ctlr; |
1205 | ||
1206 | ctlr = EDMA_CTLR(channel); | |
1207 | channel = EDMA_CHAN_SLOT(channel); | |
1208 | ||
3f68b98a | 1209 | if (channel < edma_cc[ctlr]->num_channels) { |
d78a9494 | 1210 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 | 1211 | |
60902a2c | 1212 | edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask); |
a4768d22 KH |
1213 | } |
1214 | } | |
1215 | EXPORT_SYMBOL(edma_pause); | |
1216 | ||
1217 | /** | |
1218 | * edma_resume - resumes dma on a paused channel | |
1219 | * @channel: on which edma_pause() has been called | |
1220 | * | |
1221 | * This re-enables EDMA hardware events on the specified channel. | |
1222 | */ | |
1223 | void edma_resume(unsigned channel) | |
1224 | { | |
60902a2c SR |
1225 | unsigned ctlr; |
1226 | ||
1227 | ctlr = EDMA_CTLR(channel); | |
1228 | channel = EDMA_CHAN_SLOT(channel); | |
1229 | ||
3f68b98a | 1230 | if (channel < edma_cc[ctlr]->num_channels) { |
d78a9494 | 1231 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 | 1232 | |
60902a2c | 1233 | edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask); |
a4768d22 KH |
1234 | } |
1235 | } | |
1236 | EXPORT_SYMBOL(edma_resume); | |
1237 | ||
1238 | /** | |
1239 | * edma_start - start dma on a channel | |
1240 | * @channel: channel being activated | |
1241 | * | |
1242 | * Channels with event associations will be triggered by their hardware | |
1243 | * events, and channels without such associations will be triggered by | |
1244 | * software. (At this writing there is no interface for using software | |
1245 | * triggers except with channels that don't support hardware triggers.) | |
1246 | * | |
1247 | * Returns zero on success, else negative errno. | |
1248 | */ | |
1249 | int edma_start(unsigned channel) | |
1250 | { | |
60902a2c SR |
1251 | unsigned ctlr; |
1252 | ||
1253 | ctlr = EDMA_CTLR(channel); | |
1254 | channel = EDMA_CHAN_SLOT(channel); | |
1255 | ||
3f68b98a | 1256 | if (channel < edma_cc[ctlr]->num_channels) { |
a4768d22 | 1257 | int j = channel >> 5; |
d78a9494 | 1258 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 KH |
1259 | |
1260 | /* EDMA channels without event association */ | |
3f68b98a | 1261 | if (test_bit(channel, edma_cc[ctlr]->edma_unused)) { |
a4768d22 | 1262 | pr_debug("EDMA: ESR%d %08x\n", j, |
60902a2c SR |
1263 | edma_shadow0_read_array(ctlr, SH_ESR, j)); |
1264 | edma_shadow0_write_array(ctlr, SH_ESR, j, mask); | |
a4768d22 KH |
1265 | return 0; |
1266 | } | |
1267 | ||
1268 | /* EDMA channel with event association */ | |
1269 | pr_debug("EDMA: ER%d %08x\n", j, | |
60902a2c | 1270 | edma_shadow0_read_array(ctlr, SH_ER, j)); |
bb17ef10 BN |
1271 | /* Clear any pending event or error */ |
1272 | edma_write_array(ctlr, EDMA_ECR, j, mask); | |
60902a2c | 1273 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
a4768d22 | 1274 | /* Clear any SER */ |
60902a2c SR |
1275 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
1276 | edma_shadow0_write_array(ctlr, SH_EESR, j, mask); | |
a4768d22 | 1277 | pr_debug("EDMA: EER%d %08x\n", j, |
60902a2c | 1278 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
a4768d22 KH |
1279 | return 0; |
1280 | } | |
1281 | ||
1282 | return -EINVAL; | |
1283 | } | |
1284 | EXPORT_SYMBOL(edma_start); | |
1285 | ||
1286 | /** | |
1287 | * edma_stop - stops dma on the channel passed | |
1288 | * @channel: channel being deactivated | |
1289 | * | |
1290 | * When @lch is a channel, any active transfer is paused and | |
1291 | * all pending hardware events are cleared. The current transfer | |
1292 | * may not be resumed, and the channel's Parameter RAM should be | |
1293 | * reinitialized before being reused. | |
1294 | */ | |
1295 | void edma_stop(unsigned channel) | |
1296 | { | |
60902a2c SR |
1297 | unsigned ctlr; |
1298 | ||
1299 | ctlr = EDMA_CTLR(channel); | |
1300 | channel = EDMA_CHAN_SLOT(channel); | |
1301 | ||
3f68b98a | 1302 | if (channel < edma_cc[ctlr]->num_channels) { |
a4768d22 | 1303 | int j = channel >> 5; |
d78a9494 | 1304 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 | 1305 | |
60902a2c SR |
1306 | edma_shadow0_write_array(ctlr, SH_EECR, j, mask); |
1307 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); | |
1308 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); | |
1309 | edma_write_array(ctlr, EDMA_EMCR, j, mask); | |
a4768d22 KH |
1310 | |
1311 | pr_debug("EDMA: EER%d %08x\n", j, | |
60902a2c | 1312 | edma_shadow0_read_array(ctlr, SH_EER, j)); |
a4768d22 KH |
1313 | |
1314 | /* REVISIT: consider guarding against inappropriate event | |
1315 | * chaining by overwriting with dummy_paramset. | |
1316 | */ | |
1317 | } | |
1318 | } | |
1319 | EXPORT_SYMBOL(edma_stop); | |
1320 | ||
1321 | /****************************************************************************** | |
1322 | * | |
1323 | * It cleans ParamEntry qand bring back EDMA to initial state if media has | |
1324 | * been removed before EDMA has finished.It is usedful for removable media. | |
1325 | * Arguments: | |
1326 | * ch_no - channel no | |
1327 | * | |
1328 | * Return: zero on success, or corresponding error no on failure | |
1329 | * | |
1330 | * FIXME this should not be needed ... edma_stop() should suffice. | |
1331 | * | |
1332 | *****************************************************************************/ | |
1333 | ||
1334 | void edma_clean_channel(unsigned channel) | |
1335 | { | |
60902a2c SR |
1336 | unsigned ctlr; |
1337 | ||
1338 | ctlr = EDMA_CTLR(channel); | |
1339 | channel = EDMA_CHAN_SLOT(channel); | |
1340 | ||
3f68b98a | 1341 | if (channel < edma_cc[ctlr]->num_channels) { |
a4768d22 | 1342 | int j = (channel >> 5); |
d78a9494 | 1343 | unsigned int mask = BIT(channel & 0x1f); |
a4768d22 KH |
1344 | |
1345 | pr_debug("EDMA: EMR%d %08x\n", j, | |
60902a2c SR |
1346 | edma_read_array(ctlr, EDMA_EMR, j)); |
1347 | edma_shadow0_write_array(ctlr, SH_ECR, j, mask); | |
a4768d22 | 1348 | /* Clear the corresponding EMR bits */ |
60902a2c | 1349 | edma_write_array(ctlr, EDMA_EMCR, j, mask); |
a4768d22 | 1350 | /* Clear any SER */ |
60902a2c | 1351 | edma_shadow0_write_array(ctlr, SH_SECR, j, mask); |
d78a9494 | 1352 | edma_write(ctlr, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0)); |
a4768d22 KH |
1353 | } |
1354 | } | |
1355 | EXPORT_SYMBOL(edma_clean_channel); | |
1356 | ||
1357 | /* | |
1358 | * edma_clear_event - clear an outstanding event on the DMA channel | |
1359 | * Arguments: | |
1360 | * channel - channel number | |
1361 | */ | |
1362 | void edma_clear_event(unsigned channel) | |
1363 | { | |
60902a2c SR |
1364 | unsigned ctlr; |
1365 | ||
1366 | ctlr = EDMA_CTLR(channel); | |
1367 | channel = EDMA_CHAN_SLOT(channel); | |
1368 | ||
3f68b98a | 1369 | if (channel >= edma_cc[ctlr]->num_channels) |
a4768d22 KH |
1370 | return; |
1371 | if (channel < 32) | |
d78a9494 | 1372 | edma_write(ctlr, EDMA_ECR, BIT(channel)); |
a4768d22 | 1373 | else |
d78a9494 | 1374 | edma_write(ctlr, EDMA_ECRH, BIT(channel - 32)); |
a4768d22 KH |
1375 | } |
1376 | EXPORT_SYMBOL(edma_clear_event); | |
1377 | ||
6cba4355 MP |
1378 | #if IS_ENABLED(CONFIG_OF) && IS_ENABLED(CONFIG_DMADEVICES) |
1379 | ||
2646a0e5 MP |
1380 | static int edma_of_read_u32_to_s16_array(const struct device_node *np, |
1381 | const char *propname, s16 *out_values, | |
1382 | size_t sz) | |
1383 | { | |
1384 | int ret; | |
1385 | ||
1386 | ret = of_property_read_u16_array(np, propname, out_values, sz); | |
1387 | if (ret) | |
1388 | return ret; | |
1389 | ||
1390 | /* Terminate it */ | |
1391 | *out_values++ = -1; | |
1392 | *out_values++ = -1; | |
1393 | ||
1394 | return 0; | |
1395 | } | |
1396 | ||
1397 | static int edma_xbar_event_map(struct device *dev, | |
1398 | struct device_node *node, | |
1399 | struct edma_soc_info *pdata, int len) | |
1400 | { | |
1401 | int ret, i; | |
1402 | struct resource res; | |
1403 | void __iomem *xbar; | |
1404 | const s16 (*xbar_chans)[2]; | |
1405 | u32 shift, offset, mux; | |
1406 | ||
1407 | xbar_chans = devm_kzalloc(dev, | |
1408 | len/sizeof(s16) + 2*sizeof(s16), | |
1409 | GFP_KERNEL); | |
1410 | if (!xbar_chans) | |
1411 | return -ENOMEM; | |
1412 | ||
1413 | ret = of_address_to_resource(node, 1, &res); | |
1414 | if (ret) | |
1415 | return -EIO; | |
1416 | ||
1417 | xbar = devm_ioremap(dev, res.start, resource_size(&res)); | |
1418 | if (!xbar) | |
1419 | return -ENOMEM; | |
1420 | ||
1421 | ret = edma_of_read_u32_to_s16_array(node, | |
1422 | "ti,edma-xbar-event-map", | |
1423 | (s16 *)xbar_chans, | |
1424 | len/sizeof(u32)); | |
1425 | if (ret) | |
1426 | return -EIO; | |
1427 | ||
1428 | for (i = 0; xbar_chans[i][0] != -1; i++) { | |
1429 | shift = (xbar_chans[i][1] & 0x03) << 3; | |
1430 | offset = xbar_chans[i][1] & 0xfffffffc; | |
1431 | mux = readl(xbar + offset); | |
1432 | mux &= ~(0xff << shift); | |
1433 | mux |= xbar_chans[i][0] << shift; | |
1434 | writel(mux, (xbar + offset)); | |
1435 | } | |
1436 | ||
1437 | pdata->xbar_chans = xbar_chans; | |
1438 | ||
1439 | return 0; | |
1440 | } | |
1441 | ||
6cba4355 MP |
1442 | static int edma_of_parse_dt(struct device *dev, |
1443 | struct device_node *node, | |
1444 | struct edma_soc_info *pdata) | |
1445 | { | |
1446 | int ret = 0, i; | |
1447 | u32 value; | |
2646a0e5 MP |
1448 | struct property *prop; |
1449 | size_t sz; | |
6cba4355 MP |
1450 | struct edma_rsv_info *rsv_info; |
1451 | s8 (*queue_tc_map)[2], (*queue_priority_map)[2]; | |
1452 | ||
1453 | memset(pdata, 0, sizeof(struct edma_soc_info)); | |
1454 | ||
1455 | ret = of_property_read_u32(node, "dma-channels", &value); | |
1456 | if (ret < 0) | |
1457 | return ret; | |
1458 | pdata->n_channel = value; | |
1459 | ||
1460 | ret = of_property_read_u32(node, "ti,edma-regions", &value); | |
1461 | if (ret < 0) | |
1462 | return ret; | |
1463 | pdata->n_region = value; | |
1464 | ||
1465 | ret = of_property_read_u32(node, "ti,edma-slots", &value); | |
1466 | if (ret < 0) | |
1467 | return ret; | |
1468 | pdata->n_slot = value; | |
1469 | ||
1470 | pdata->n_cc = 1; | |
1471 | ||
1472 | rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL); | |
1473 | if (!rsv_info) | |
1474 | return -ENOMEM; | |
1475 | pdata->rsv = rsv_info; | |
1476 | ||
1477 | queue_tc_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL); | |
1478 | if (!queue_tc_map) | |
1479 | return -ENOMEM; | |
1480 | ||
1481 | for (i = 0; i < 3; i++) { | |
1482 | queue_tc_map[i][0] = i; | |
1483 | queue_tc_map[i][1] = i; | |
1484 | } | |
1485 | queue_tc_map[i][0] = -1; | |
1486 | queue_tc_map[i][1] = -1; | |
1487 | ||
1488 | pdata->queue_tc_mapping = queue_tc_map; | |
1489 | ||
1490 | queue_priority_map = devm_kzalloc(dev, 8*sizeof(s8), GFP_KERNEL); | |
1491 | if (!queue_priority_map) | |
1492 | return -ENOMEM; | |
1493 | ||
1494 | for (i = 0; i < 3; i++) { | |
1495 | queue_priority_map[i][0] = i; | |
1496 | queue_priority_map[i][1] = i; | |
1497 | } | |
1498 | queue_priority_map[i][0] = -1; | |
1499 | queue_priority_map[i][1] = -1; | |
1500 | ||
1501 | pdata->queue_priority_mapping = queue_priority_map; | |
1502 | ||
1503 | pdata->default_queue = 0; | |
a4768d22 | 1504 | |
2646a0e5 MP |
1505 | prop = of_find_property(node, "ti,edma-xbar-event-map", &sz); |
1506 | if (prop) | |
1507 | ret = edma_xbar_event_map(dev, node, pdata, sz); | |
1508 | ||
6cba4355 MP |
1509 | return ret; |
1510 | } | |
1511 | ||
1512 | static struct of_dma_filter_info edma_filter_info = { | |
1513 | .filter_fn = edma_filter_fn, | |
1514 | }; | |
1515 | ||
1516 | static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, | |
1517 | struct device_node *node) | |
1518 | { | |
1519 | struct edma_soc_info *info; | |
1520 | int ret; | |
1521 | ||
1522 | info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL); | |
1523 | if (!info) | |
1524 | return ERR_PTR(-ENOMEM); | |
1525 | ||
1526 | ret = edma_of_parse_dt(dev, node, info); | |
1527 | if (ret) | |
1528 | return ERR_PTR(ret); | |
1529 | ||
1530 | dma_cap_set(DMA_SLAVE, edma_filter_info.dma_cap); | |
1531 | of_dma_controller_register(dev->of_node, of_dma_simple_xlate, | |
1532 | &edma_filter_info); | |
1533 | ||
1534 | return info; | |
1535 | } | |
1536 | #else | |
1537 | static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev, | |
1538 | struct device_node *node) | |
1539 | { | |
1540 | return ERR_PTR(-ENOSYS); | |
1541 | } | |
1542 | #endif | |
1543 | ||
1544 | static int edma_probe(struct platform_device *pdev) | |
a4768d22 | 1545 | { |
bc3ac9f3 | 1546 | struct edma_soc_info **info = pdev->dev.platform_data; |
6cba4355 MP |
1547 | struct edma_soc_info *ninfo[EDMA_MAX_CC] = {NULL}; |
1548 | s8 (*queue_priority_mapping)[2]; | |
1549 | s8 (*queue_tc_mapping)[2]; | |
90bd4e6d | 1550 | int i, j, off, ln, found = 0; |
60902a2c | 1551 | int status = -1; |
90bd4e6d RS |
1552 | const s16 (*rsv_chans)[2]; |
1553 | const s16 (*rsv_slots)[2]; | |
2646a0e5 | 1554 | const s16 (*xbar_chans)[2]; |
60902a2c SR |
1555 | int irq[EDMA_MAX_CC] = {0, 0}; |
1556 | int err_irq[EDMA_MAX_CC] = {0, 0}; | |
1557 | struct resource *r[EDMA_MAX_CC] = {NULL}; | |
6cba4355 | 1558 | struct resource res[EDMA_MAX_CC]; |
60902a2c SR |
1559 | char res_name[10]; |
1560 | char irq_name[10]; | |
6cba4355 MP |
1561 | struct device_node *node = pdev->dev.of_node; |
1562 | struct device *dev = &pdev->dev; | |
1563 | int ret; | |
1564 | ||
1565 | if (node) { | |
1566 | /* Check if this is a second instance registered */ | |
1567 | if (arch_num_cc) { | |
1568 | dev_err(dev, "only one EDMA instance is supported via DT\n"); | |
1569 | return -ENODEV; | |
1570 | } | |
1571 | ||
1572 | ninfo[0] = edma_setup_info_from_dt(dev, node); | |
1573 | if (IS_ERR(ninfo[0])) { | |
1574 | dev_err(dev, "failed to get DT data\n"); | |
1575 | return PTR_ERR(ninfo[0]); | |
1576 | } | |
1577 | ||
1578 | info = ninfo; | |
1579 | } | |
a4768d22 KH |
1580 | |
1581 | if (!info) | |
1582 | return -ENODEV; | |
1583 | ||
6cba4355 MP |
1584 | pm_runtime_enable(dev); |
1585 | ret = pm_runtime_get_sync(dev); | |
1586 | if (ret < 0) { | |
1587 | dev_err(dev, "pm_runtime_get_sync() failed\n"); | |
1588 | return ret; | |
1589 | } | |
1590 | ||
60902a2c | 1591 | for (j = 0; j < EDMA_MAX_CC; j++) { |
6cba4355 MP |
1592 | if (!info[j]) { |
1593 | if (!found) | |
1594 | return -ENODEV; | |
1595 | break; | |
1596 | } | |
1597 | if (node) { | |
1598 | ret = of_address_to_resource(node, j, &res[j]); | |
1599 | if (!ret) | |
1600 | r[j] = &res[j]; | |
1601 | } else { | |
1602 | sprintf(res_name, "edma_cc%d", j); | |
1603 | r[j] = platform_get_resource_byname(pdev, | |
1604 | IORESOURCE_MEM, | |
60902a2c | 1605 | res_name); |
6cba4355 MP |
1606 | } |
1607 | if (!r[j]) { | |
60902a2c SR |
1608 | if (found) |
1609 | break; | |
1610 | else | |
1611 | return -ENODEV; | |
243bc654 | 1612 | } else { |
60902a2c | 1613 | found = 1; |
243bc654 | 1614 | } |
60902a2c | 1615 | |
e7eff702 LP |
1616 | edmacc_regs_base[j] = devm_ioremap_resource(&pdev->dev, r[j]); |
1617 | if (IS_ERR(edmacc_regs_base[j])) | |
1618 | return PTR_ERR(edmacc_regs_base[j]); | |
60902a2c | 1619 | |
e7eff702 LP |
1620 | edma_cc[j] = devm_kzalloc(&pdev->dev, sizeof(struct edma), |
1621 | GFP_KERNEL); | |
1622 | if (!edma_cc[j]) | |
1623 | return -ENOMEM; | |
60902a2c | 1624 | |
bc3ac9f3 | 1625 | edma_cc[j]->num_channels = min_t(unsigned, info[j]->n_channel, |
60902a2c | 1626 | EDMA_MAX_DMACH); |
bc3ac9f3 | 1627 | edma_cc[j]->num_slots = min_t(unsigned, info[j]->n_slot, |
60902a2c | 1628 | EDMA_MAX_PARAMENTRY); |
bc3ac9f3 SN |
1629 | edma_cc[j]->num_cc = min_t(unsigned, info[j]->n_cc, |
1630 | EDMA_MAX_CC); | |
60902a2c | 1631 | |
bc3ac9f3 | 1632 | edma_cc[j]->default_queue = info[j]->default_queue; |
a0f0202e | 1633 | |
60902a2c SR |
1634 | dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n", |
1635 | edmacc_regs_base[j]); | |
1636 | ||
3f68b98a | 1637 | for (i = 0; i < edma_cc[j]->num_slots; i++) |
60902a2c SR |
1638 | memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i), |
1639 | &dummy_paramset, PARM_SIZE); | |
1640 | ||
f900d552 | 1641 | /* Mark all channels as unused */ |
3f68b98a SN |
1642 | memset(edma_cc[j]->edma_unused, 0xff, |
1643 | sizeof(edma_cc[j]->edma_unused)); | |
a4768d22 | 1644 | |
90bd4e6d RS |
1645 | if (info[j]->rsv) { |
1646 | ||
1647 | /* Clear the reserved channels in unused list */ | |
1648 | rsv_chans = info[j]->rsv->rsv_chans; | |
1649 | if (rsv_chans) { | |
1650 | for (i = 0; rsv_chans[i][0] != -1; i++) { | |
1651 | off = rsv_chans[i][0]; | |
1652 | ln = rsv_chans[i][1]; | |
1653 | clear_bits(off, ln, | |
6cba4355 | 1654 | edma_cc[j]->edma_unused); |
90bd4e6d RS |
1655 | } |
1656 | } | |
1657 | ||
1658 | /* Set the reserved slots in inuse list */ | |
1659 | rsv_slots = info[j]->rsv->rsv_slots; | |
1660 | if (rsv_slots) { | |
1661 | for (i = 0; rsv_slots[i][0] != -1; i++) { | |
1662 | off = rsv_slots[i][0]; | |
1663 | ln = rsv_slots[i][1]; | |
1664 | set_bits(off, ln, | |
1665 | edma_cc[j]->edma_inuse); | |
1666 | } | |
1667 | } | |
1668 | } | |
1669 | ||
2646a0e5 MP |
1670 | /* Clear the xbar mapped channels in unused list */ |
1671 | xbar_chans = info[j]->xbar_chans; | |
1672 | if (xbar_chans) { | |
1673 | for (i = 0; xbar_chans[i][1] != -1; i++) { | |
1674 | off = xbar_chans[i][1]; | |
1675 | clear_bits(off, 1, | |
1676 | edma_cc[j]->edma_unused); | |
1677 | } | |
1678 | } | |
6cba4355 MP |
1679 | |
1680 | if (node) { | |
1681 | irq[j] = irq_of_parse_and_map(node, 0); | |
1682 | } else { | |
1683 | sprintf(irq_name, "edma%d", j); | |
1684 | irq[j] = platform_get_irq_byname(pdev, irq_name); | |
1685 | } | |
3f68b98a | 1686 | edma_cc[j]->irq_res_start = irq[j]; |
e7eff702 LP |
1687 | status = devm_request_irq(&pdev->dev, irq[j], |
1688 | dma_irq_handler, 0, "edma", | |
1689 | &pdev->dev); | |
60902a2c | 1690 | if (status < 0) { |
e7eff702 LP |
1691 | dev_dbg(&pdev->dev, |
1692 | "devm_request_irq %d failed --> %d\n", | |
60902a2c | 1693 | irq[j], status); |
e7eff702 | 1694 | return status; |
60902a2c | 1695 | } |
a4768d22 | 1696 | |
6cba4355 MP |
1697 | if (node) { |
1698 | err_irq[j] = irq_of_parse_and_map(node, 2); | |
1699 | } else { | |
1700 | sprintf(irq_name, "edma%d_err", j); | |
1701 | err_irq[j] = platform_get_irq_byname(pdev, irq_name); | |
1702 | } | |
3f68b98a | 1703 | edma_cc[j]->irq_res_end = err_irq[j]; |
e7eff702 LP |
1704 | status = devm_request_irq(&pdev->dev, err_irq[j], |
1705 | dma_ccerr_handler, 0, | |
1706 | "edma_error", &pdev->dev); | |
60902a2c | 1707 | if (status < 0) { |
e7eff702 LP |
1708 | dev_dbg(&pdev->dev, |
1709 | "devm_request_irq %d failed --> %d\n", | |
60902a2c | 1710 | err_irq[j], status); |
e7eff702 | 1711 | return status; |
60902a2c | 1712 | } |
a4768d22 | 1713 | |
3f68b98a | 1714 | for (i = 0; i < edma_cc[j]->num_channels; i++) |
0b7580ba | 1715 | map_dmach_queue(j, i, info[j]->default_queue); |
a4768d22 | 1716 | |
bc3ac9f3 SN |
1717 | queue_tc_mapping = info[j]->queue_tc_mapping; |
1718 | queue_priority_mapping = info[j]->queue_priority_mapping; | |
a4768d22 | 1719 | |
60902a2c SR |
1720 | /* Event queue to TC mapping */ |
1721 | for (i = 0; queue_tc_mapping[i][0] != -1; i++) | |
1722 | map_queue_tc(j, queue_tc_mapping[i][0], | |
1723 | queue_tc_mapping[i][1]); | |
a4768d22 | 1724 | |
60902a2c SR |
1725 | /* Event queue priority mapping */ |
1726 | for (i = 0; queue_priority_mapping[i][0] != -1; i++) | |
1727 | assign_priority_to_queue(j, | |
1728 | queue_priority_mapping[i][0], | |
1729 | queue_priority_mapping[i][1]); | |
1730 | ||
1731 | /* Map the channel to param entry if channel mapping logic | |
1732 | * exist | |
1733 | */ | |
1734 | if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST) | |
1735 | map_dmach_param(j); | |
a4768d22 | 1736 | |
bc3ac9f3 | 1737 | for (i = 0; i < info[j]->n_region; i++) { |
60902a2c SR |
1738 | edma_write_array2(j, EDMA_DRAE, i, 0, 0x0); |
1739 | edma_write_array2(j, EDMA_DRAE, i, 1, 0x0); | |
1740 | edma_write_array(j, EDMA_QRAE, i, 0x0); | |
1741 | } | |
2d517508 | 1742 | arch_num_cc++; |
a4768d22 KH |
1743 | } |
1744 | ||
a4768d22 | 1745 | return 0; |
a4768d22 KH |
1746 | } |
1747 | ||
6cba4355 MP |
1748 | static const struct of_device_id edma_of_ids[] = { |
1749 | { .compatible = "ti,edma3", }, | |
1750 | {} | |
1751 | }; | |
a4768d22 KH |
1752 | |
1753 | static struct platform_driver edma_driver = { | |
6cba4355 MP |
1754 | .driver = { |
1755 | .name = "edma", | |
1756 | .of_match_table = edma_of_ids, | |
1757 | }, | |
1758 | .probe = edma_probe, | |
a4768d22 KH |
1759 | }; |
1760 | ||
1761 | static int __init edma_init(void) | |
1762 | { | |
1763 | return platform_driver_probe(&edma_driver, edma_probe); | |
1764 | } | |
1765 | arch_initcall(edma_init); | |
1766 |