Commit | Line | Data |
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f27ecacc RK |
1 | /* |
2 | * linux/arch/arm/common/gic.c | |
3 | * | |
4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * Interrupt architecture for the GIC: | |
11 | * | |
12 | * o There is one Interrupt Distributor, which receives interrupts | |
13 | * from system devices and sends them to the Interrupt Controllers. | |
14 | * | |
15 | * o There is one CPU Interface per CPU, which sends interrupts sent | |
16 | * by the Distributor, and interrupts generated locally, to the | |
b3a1bde4 CM |
17 | * associated CPU. The base address of the CPU interface is usually |
18 | * aliased so that the same address points to different chips depending | |
19 | * on the CPU it is accessed from. | |
f27ecacc RK |
20 | * |
21 | * Note that IRQs 0-31 are special - they are local to each CPU. | |
22 | * As such, the enable set/clear, pending set/clear and active bit | |
23 | * registers are banked per-cpu for these sources. | |
24 | */ | |
25 | #include <linux/init.h> | |
26 | #include <linux/kernel.h> | |
f37a53cc | 27 | #include <linux/err.h> |
7e1efcf5 | 28 | #include <linux/module.h> |
f27ecacc RK |
29 | #include <linux/list.h> |
30 | #include <linux/smp.h> | |
254056f3 | 31 | #include <linux/cpu_pm.h> |
dcb86e8c | 32 | #include <linux/cpumask.h> |
fced80c7 | 33 | #include <linux/io.h> |
b3f7ed03 RH |
34 | #include <linux/of.h> |
35 | #include <linux/of_address.h> | |
36 | #include <linux/of_irq.h> | |
4294f8ba | 37 | #include <linux/irqdomain.h> |
292b293c MZ |
38 | #include <linux/interrupt.h> |
39 | #include <linux/percpu.h> | |
40 | #include <linux/slab.h> | |
f27ecacc RK |
41 | |
42 | #include <asm/irq.h> | |
f27ecacc RK |
43 | #include <asm/mach/irq.h> |
44 | #include <asm/hardware/gic.h> | |
45 | ||
db0d4db2 MZ |
46 | union gic_base { |
47 | void __iomem *common_base; | |
48 | void __percpu __iomem **percpu_base; | |
49 | }; | |
50 | ||
51 | struct gic_chip_data { | |
52 | unsigned int irq_offset; | |
53 | union gic_base dist_base; | |
54 | union gic_base cpu_base; | |
55 | #ifdef CONFIG_CPU_PM | |
56 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; | |
57 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; | |
58 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; | |
59 | u32 __percpu *saved_ppi_enable; | |
60 | u32 __percpu *saved_ppi_conf; | |
61 | #endif | |
62 | #ifdef CONFIG_IRQ_DOMAIN | |
63 | struct irq_domain domain; | |
64 | #endif | |
65 | unsigned int gic_irqs; | |
66 | #ifdef CONFIG_GIC_NON_BANKED | |
67 | void __iomem *(*get_base)(union gic_base *); | |
68 | #endif | |
69 | }; | |
70 | ||
bd31b859 | 71 | static DEFINE_RAW_SPINLOCK(irq_controller_lock); |
f27ecacc | 72 | |
ff2e27ae | 73 | /* Address of GIC 0 CPU interface */ |
bef8f9ee | 74 | void __iomem *gic_cpu_base_addr __read_mostly; |
ff2e27ae | 75 | |
d7ed36a4 SS |
76 | /* |
77 | * Supported arch specific GIC irq extension. | |
78 | * Default make them NULL. | |
79 | */ | |
80 | struct irq_chip gic_arch_extn = { | |
1a01753e | 81 | .irq_eoi = NULL, |
d7ed36a4 SS |
82 | .irq_mask = NULL, |
83 | .irq_unmask = NULL, | |
84 | .irq_retrigger = NULL, | |
85 | .irq_set_type = NULL, | |
86 | .irq_set_wake = NULL, | |
87 | }; | |
88 | ||
b3a1bde4 CM |
89 | #ifndef MAX_GIC_NR |
90 | #define MAX_GIC_NR 1 | |
91 | #endif | |
92 | ||
bef8f9ee | 93 | static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; |
b3a1bde4 | 94 | |
db0d4db2 MZ |
95 | #ifdef CONFIG_GIC_NON_BANKED |
96 | static void __iomem *gic_get_percpu_base(union gic_base *base) | |
97 | { | |
98 | return *__this_cpu_ptr(base->percpu_base); | |
99 | } | |
100 | ||
101 | static void __iomem *gic_get_common_base(union gic_base *base) | |
102 | { | |
103 | return base->common_base; | |
104 | } | |
105 | ||
106 | static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) | |
107 | { | |
108 | return data->get_base(&data->dist_base); | |
109 | } | |
110 | ||
111 | static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) | |
112 | { | |
113 | return data->get_base(&data->cpu_base); | |
114 | } | |
115 | ||
116 | static inline void gic_set_base_accessor(struct gic_chip_data *data, | |
117 | void __iomem *(*f)(union gic_base *)) | |
118 | { | |
119 | data->get_base = f; | |
120 | } | |
121 | #else | |
122 | #define gic_data_dist_base(d) ((d)->dist_base.common_base) | |
123 | #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) | |
124 | #define gic_set_base_accessor(d,f) | |
125 | #endif | |
126 | ||
7d1f4288 | 127 | static inline void __iomem *gic_dist_base(struct irq_data *d) |
b3a1bde4 | 128 | { |
7d1f4288 | 129 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 130 | return gic_data_dist_base(gic_data); |
b3a1bde4 CM |
131 | } |
132 | ||
7d1f4288 | 133 | static inline void __iomem *gic_cpu_base(struct irq_data *d) |
b3a1bde4 | 134 | { |
7d1f4288 | 135 | struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); |
db0d4db2 | 136 | return gic_data_cpu_base(gic_data); |
b3a1bde4 CM |
137 | } |
138 | ||
7d1f4288 | 139 | static inline unsigned int gic_irq(struct irq_data *d) |
b3a1bde4 | 140 | { |
4294f8ba | 141 | return d->hwirq; |
b3a1bde4 CM |
142 | } |
143 | ||
f27ecacc RK |
144 | /* |
145 | * Routines to acknowledge, disable and enable interrupts | |
f27ecacc | 146 | */ |
7d1f4288 | 147 | static void gic_mask_irq(struct irq_data *d) |
f27ecacc | 148 | { |
4294f8ba | 149 | u32 mask = 1 << (gic_irq(d) % 32); |
c4bfa28a | 150 | |
bd31b859 | 151 | raw_spin_lock(&irq_controller_lock); |
6ac77e46 | 152 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); |
d7ed36a4 SS |
153 | if (gic_arch_extn.irq_mask) |
154 | gic_arch_extn.irq_mask(d); | |
bd31b859 | 155 | raw_spin_unlock(&irq_controller_lock); |
f27ecacc RK |
156 | } |
157 | ||
7d1f4288 | 158 | static void gic_unmask_irq(struct irq_data *d) |
f27ecacc | 159 | { |
4294f8ba | 160 | u32 mask = 1 << (gic_irq(d) % 32); |
c4bfa28a | 161 | |
bd31b859 | 162 | raw_spin_lock(&irq_controller_lock); |
d7ed36a4 SS |
163 | if (gic_arch_extn.irq_unmask) |
164 | gic_arch_extn.irq_unmask(d); | |
6ac77e46 | 165 | writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); |
bd31b859 | 166 | raw_spin_unlock(&irq_controller_lock); |
f27ecacc RK |
167 | } |
168 | ||
1a01753e WD |
169 | static void gic_eoi_irq(struct irq_data *d) |
170 | { | |
171 | if (gic_arch_extn.irq_eoi) { | |
bd31b859 | 172 | raw_spin_lock(&irq_controller_lock); |
1a01753e | 173 | gic_arch_extn.irq_eoi(d); |
bd31b859 | 174 | raw_spin_unlock(&irq_controller_lock); |
1a01753e WD |
175 | } |
176 | ||
6ac77e46 | 177 | writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); |
1a01753e WD |
178 | } |
179 | ||
7d1f4288 | 180 | static int gic_set_type(struct irq_data *d, unsigned int type) |
5c0c1f08 | 181 | { |
7d1f4288 LB |
182 | void __iomem *base = gic_dist_base(d); |
183 | unsigned int gicirq = gic_irq(d); | |
5c0c1f08 RV |
184 | u32 enablemask = 1 << (gicirq % 32); |
185 | u32 enableoff = (gicirq / 32) * 4; | |
186 | u32 confmask = 0x2 << ((gicirq % 16) * 2); | |
187 | u32 confoff = (gicirq / 16) * 4; | |
188 | bool enabled = false; | |
189 | u32 val; | |
190 | ||
191 | /* Interrupt configuration for SGIs can't be changed */ | |
192 | if (gicirq < 16) | |
193 | return -EINVAL; | |
194 | ||
195 | if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) | |
196 | return -EINVAL; | |
197 | ||
bd31b859 | 198 | raw_spin_lock(&irq_controller_lock); |
5c0c1f08 | 199 | |
d7ed36a4 SS |
200 | if (gic_arch_extn.irq_set_type) |
201 | gic_arch_extn.irq_set_type(d, type); | |
202 | ||
6ac77e46 | 203 | val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); |
5c0c1f08 RV |
204 | if (type == IRQ_TYPE_LEVEL_HIGH) |
205 | val &= ~confmask; | |
206 | else if (type == IRQ_TYPE_EDGE_RISING) | |
207 | val |= confmask; | |
208 | ||
209 | /* | |
210 | * As recommended by the spec, disable the interrupt before changing | |
211 | * the configuration | |
212 | */ | |
6ac77e46 SS |
213 | if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { |
214 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); | |
5c0c1f08 RV |
215 | enabled = true; |
216 | } | |
217 | ||
6ac77e46 | 218 | writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); |
5c0c1f08 RV |
219 | |
220 | if (enabled) | |
6ac77e46 | 221 | writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); |
5c0c1f08 | 222 | |
bd31b859 | 223 | raw_spin_unlock(&irq_controller_lock); |
5c0c1f08 RV |
224 | |
225 | return 0; | |
226 | } | |
227 | ||
d7ed36a4 SS |
228 | static int gic_retrigger(struct irq_data *d) |
229 | { | |
230 | if (gic_arch_extn.irq_retrigger) | |
231 | return gic_arch_extn.irq_retrigger(d); | |
232 | ||
233 | return -ENXIO; | |
234 | } | |
235 | ||
a06f5466 | 236 | #ifdef CONFIG_SMP |
c191789c RK |
237 | static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, |
238 | bool force) | |
f27ecacc | 239 | { |
7d1f4288 | 240 | void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); |
4294f8ba | 241 | unsigned int shift = (gic_irq(d) % 4) * 8; |
5dfc54e0 | 242 | unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); |
c191789c | 243 | u32 val, mask, bit; |
f27ecacc | 244 | |
5dfc54e0 | 245 | if (cpu >= 8 || cpu >= nr_cpu_ids) |
87507500 | 246 | return -EINVAL; |
c191789c RK |
247 | |
248 | mask = 0xff << shift; | |
267840f3 | 249 | bit = 1 << (cpu_logical_map(cpu) + shift); |
c191789c | 250 | |
bd31b859 | 251 | raw_spin_lock(&irq_controller_lock); |
6ac77e46 SS |
252 | val = readl_relaxed(reg) & ~mask; |
253 | writel_relaxed(val | bit, reg); | |
bd31b859 | 254 | raw_spin_unlock(&irq_controller_lock); |
d5dedd45 | 255 | |
5dfc54e0 | 256 | return IRQ_SET_MASK_OK; |
f27ecacc | 257 | } |
a06f5466 | 258 | #endif |
f27ecacc | 259 | |
d7ed36a4 SS |
260 | #ifdef CONFIG_PM |
261 | static int gic_set_wake(struct irq_data *d, unsigned int on) | |
262 | { | |
263 | int ret = -ENXIO; | |
264 | ||
265 | if (gic_arch_extn.irq_set_wake) | |
266 | ret = gic_arch_extn.irq_set_wake(d, on); | |
267 | ||
268 | return ret; | |
269 | } | |
270 | ||
271 | #else | |
272 | #define gic_set_wake NULL | |
273 | #endif | |
274 | ||
0f347bb9 | 275 | static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) |
b3a1bde4 | 276 | { |
6845664a TG |
277 | struct gic_chip_data *chip_data = irq_get_handler_data(irq); |
278 | struct irq_chip *chip = irq_get_chip(irq); | |
0f347bb9 | 279 | unsigned int cascade_irq, gic_irq; |
b3a1bde4 CM |
280 | unsigned long status; |
281 | ||
1a01753e | 282 | chained_irq_enter(chip, desc); |
b3a1bde4 | 283 | |
bd31b859 | 284 | raw_spin_lock(&irq_controller_lock); |
db0d4db2 | 285 | status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); |
bd31b859 | 286 | raw_spin_unlock(&irq_controller_lock); |
b3a1bde4 | 287 | |
0f347bb9 RK |
288 | gic_irq = (status & 0x3ff); |
289 | if (gic_irq == 1023) | |
b3a1bde4 | 290 | goto out; |
b3a1bde4 | 291 | |
4294f8ba | 292 | cascade_irq = irq_domain_to_irq(&chip_data->domain, gic_irq); |
0f347bb9 RK |
293 | if (unlikely(gic_irq < 32 || gic_irq > 1020 || cascade_irq >= NR_IRQS)) |
294 | do_bad_IRQ(cascade_irq, desc); | |
295 | else | |
296 | generic_handle_irq(cascade_irq); | |
b3a1bde4 CM |
297 | |
298 | out: | |
1a01753e | 299 | chained_irq_exit(chip, desc); |
b3a1bde4 CM |
300 | } |
301 | ||
38c677cb | 302 | static struct irq_chip gic_chip = { |
7d1f4288 | 303 | .name = "GIC", |
7d1f4288 LB |
304 | .irq_mask = gic_mask_irq, |
305 | .irq_unmask = gic_unmask_irq, | |
1a01753e | 306 | .irq_eoi = gic_eoi_irq, |
7d1f4288 | 307 | .irq_set_type = gic_set_type, |
d7ed36a4 | 308 | .irq_retrigger = gic_retrigger, |
f27ecacc | 309 | #ifdef CONFIG_SMP |
c191789c | 310 | .irq_set_affinity = gic_set_affinity, |
f27ecacc | 311 | #endif |
d7ed36a4 | 312 | .irq_set_wake = gic_set_wake, |
f27ecacc RK |
313 | }; |
314 | ||
b3a1bde4 CM |
315 | void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) |
316 | { | |
317 | if (gic_nr >= MAX_GIC_NR) | |
318 | BUG(); | |
6845664a | 319 | if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) |
b3a1bde4 | 320 | BUG(); |
6845664a | 321 | irq_set_chained_handler(irq, gic_handle_cascade_irq); |
b3a1bde4 CM |
322 | } |
323 | ||
4294f8ba | 324 | static void __init gic_dist_init(struct gic_chip_data *gic) |
f27ecacc | 325 | { |
4294f8ba | 326 | unsigned int i, irq; |
267840f3 | 327 | u32 cpumask; |
4294f8ba RH |
328 | unsigned int gic_irqs = gic->gic_irqs; |
329 | struct irq_domain *domain = &gic->domain; | |
db0d4db2 | 330 | void __iomem *base = gic_data_dist_base(gic); |
267840f3 | 331 | u32 cpu = 0; |
f27ecacc | 332 | |
267840f3 WD |
333 | #ifdef CONFIG_SMP |
334 | cpu = cpu_logical_map(smp_processor_id()); | |
335 | #endif | |
336 | ||
337 | cpumask = 1 << cpu; | |
f27ecacc RK |
338 | cpumask |= cpumask << 8; |
339 | cpumask |= cpumask << 16; | |
340 | ||
6ac77e46 | 341 | writel_relaxed(0, base + GIC_DIST_CTRL); |
f27ecacc | 342 | |
f27ecacc RK |
343 | /* |
344 | * Set all global interrupts to be level triggered, active low. | |
345 | */ | |
e6afec9b | 346 | for (i = 32; i < gic_irqs; i += 16) |
6ac77e46 | 347 | writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16); |
f27ecacc RK |
348 | |
349 | /* | |
350 | * Set all global interrupts to this CPU only. | |
351 | */ | |
e6afec9b | 352 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 353 | writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); |
f27ecacc RK |
354 | |
355 | /* | |
9395f6ea | 356 | * Set priority on all global interrupts. |
f27ecacc | 357 | */ |
e6afec9b | 358 | for (i = 32; i < gic_irqs; i += 4) |
6ac77e46 | 359 | writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); |
f27ecacc RK |
360 | |
361 | /* | |
9395f6ea RK |
362 | * Disable all interrupts. Leave the PPI and SGIs alone |
363 | * as these enables are banked registers. | |
f27ecacc | 364 | */ |
e6afec9b | 365 | for (i = 32; i < gic_irqs; i += 32) |
6ac77e46 | 366 | writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); |
f27ecacc RK |
367 | |
368 | /* | |
369 | * Setup the Linux IRQ subsystem. | |
370 | */ | |
4294f8ba RH |
371 | irq_domain_for_each_irq(domain, i, irq) { |
372 | if (i < 32) { | |
373 | irq_set_percpu_devid(irq); | |
374 | irq_set_chip_and_handler(irq, &gic_chip, | |
375 | handle_percpu_devid_irq); | |
376 | set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); | |
377 | } else { | |
378 | irq_set_chip_and_handler(irq, &gic_chip, | |
379 | handle_fasteoi_irq); | |
380 | set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); | |
381 | } | |
382 | irq_set_chip_data(irq, gic); | |
f27ecacc RK |
383 | } |
384 | ||
6ac77e46 | 385 | writel_relaxed(1, base + GIC_DIST_CTRL); |
f27ecacc RK |
386 | } |
387 | ||
bef8f9ee | 388 | static void __cpuinit gic_cpu_init(struct gic_chip_data *gic) |
f27ecacc | 389 | { |
db0d4db2 MZ |
390 | void __iomem *dist_base = gic_data_dist_base(gic); |
391 | void __iomem *base = gic_data_cpu_base(gic); | |
9395f6ea RK |
392 | int i; |
393 | ||
9395f6ea RK |
394 | /* |
395 | * Deal with the banked PPI and SGI interrupts - disable all | |
396 | * PPI interrupts, ensure all SGI interrupts are enabled. | |
397 | */ | |
6ac77e46 SS |
398 | writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); |
399 | writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); | |
9395f6ea RK |
400 | |
401 | /* | |
402 | * Set priority on PPI and SGI interrupts | |
403 | */ | |
404 | for (i = 0; i < 32; i += 4) | |
6ac77e46 | 405 | writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); |
9395f6ea | 406 | |
6ac77e46 SS |
407 | writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); |
408 | writel_relaxed(1, base + GIC_CPU_CTRL); | |
f27ecacc RK |
409 | } |
410 | ||
254056f3 CC |
411 | #ifdef CONFIG_CPU_PM |
412 | /* | |
413 | * Saves the GIC distributor registers during suspend or idle. Must be called | |
414 | * with interrupts disabled but before powering down the GIC. After calling | |
415 | * this function, no interrupts will be delivered by the GIC, and another | |
416 | * platform-specific wakeup source must be enabled. | |
417 | */ | |
418 | static void gic_dist_save(unsigned int gic_nr) | |
419 | { | |
420 | unsigned int gic_irqs; | |
421 | void __iomem *dist_base; | |
422 | int i; | |
423 | ||
424 | if (gic_nr >= MAX_GIC_NR) | |
425 | BUG(); | |
426 | ||
427 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 428 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
429 | |
430 | if (!dist_base) | |
431 | return; | |
432 | ||
433 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
434 | gic_data[gic_nr].saved_spi_conf[i] = | |
435 | readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
436 | ||
437 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
438 | gic_data[gic_nr].saved_spi_target[i] = | |
439 | readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); | |
440 | ||
441 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
442 | gic_data[gic_nr].saved_spi_enable[i] = | |
443 | readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
444 | } | |
445 | ||
446 | /* | |
447 | * Restores the GIC distributor registers during resume or when coming out of | |
448 | * idle. Must be called before enabling interrupts. If a level interrupt | |
449 | * that occured while the GIC was suspended is still present, it will be | |
450 | * handled normally, but any edge interrupts that occured will not be seen by | |
451 | * the GIC and need to be handled by the platform-specific wakeup source. | |
452 | */ | |
453 | static void gic_dist_restore(unsigned int gic_nr) | |
454 | { | |
455 | unsigned int gic_irqs; | |
456 | unsigned int i; | |
457 | void __iomem *dist_base; | |
458 | ||
459 | if (gic_nr >= MAX_GIC_NR) | |
460 | BUG(); | |
461 | ||
462 | gic_irqs = gic_data[gic_nr].gic_irqs; | |
db0d4db2 | 463 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
254056f3 CC |
464 | |
465 | if (!dist_base) | |
466 | return; | |
467 | ||
468 | writel_relaxed(0, dist_base + GIC_DIST_CTRL); | |
469 | ||
470 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) | |
471 | writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], | |
472 | dist_base + GIC_DIST_CONFIG + i * 4); | |
473 | ||
474 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
475 | writel_relaxed(0xa0a0a0a0, | |
476 | dist_base + GIC_DIST_PRI + i * 4); | |
477 | ||
478 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) | |
479 | writel_relaxed(gic_data[gic_nr].saved_spi_target[i], | |
480 | dist_base + GIC_DIST_TARGET + i * 4); | |
481 | ||
482 | for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) | |
483 | writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], | |
484 | dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
485 | ||
486 | writel_relaxed(1, dist_base + GIC_DIST_CTRL); | |
487 | } | |
488 | ||
489 | static void gic_cpu_save(unsigned int gic_nr) | |
490 | { | |
491 | int i; | |
492 | u32 *ptr; | |
493 | void __iomem *dist_base; | |
494 | void __iomem *cpu_base; | |
495 | ||
496 | if (gic_nr >= MAX_GIC_NR) | |
497 | BUG(); | |
498 | ||
db0d4db2 MZ |
499 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
500 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
501 | |
502 | if (!dist_base || !cpu_base) | |
503 | return; | |
504 | ||
505 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); | |
506 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) | |
507 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
508 | ||
509 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); | |
510 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) | |
511 | ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); | |
512 | ||
513 | } | |
514 | ||
515 | static void gic_cpu_restore(unsigned int gic_nr) | |
516 | { | |
517 | int i; | |
518 | u32 *ptr; | |
519 | void __iomem *dist_base; | |
520 | void __iomem *cpu_base; | |
521 | ||
522 | if (gic_nr >= MAX_GIC_NR) | |
523 | BUG(); | |
524 | ||
db0d4db2 MZ |
525 | dist_base = gic_data_dist_base(&gic_data[gic_nr]); |
526 | cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); | |
254056f3 CC |
527 | |
528 | if (!dist_base || !cpu_base) | |
529 | return; | |
530 | ||
531 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); | |
532 | for (i = 0; i < DIV_ROUND_UP(32, 32); i++) | |
533 | writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); | |
534 | ||
535 | ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); | |
536 | for (i = 0; i < DIV_ROUND_UP(32, 16); i++) | |
537 | writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); | |
538 | ||
539 | for (i = 0; i < DIV_ROUND_UP(32, 4); i++) | |
540 | writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4); | |
541 | ||
542 | writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK); | |
543 | writel_relaxed(1, cpu_base + GIC_CPU_CTRL); | |
544 | } | |
545 | ||
546 | static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) | |
547 | { | |
548 | int i; | |
549 | ||
550 | for (i = 0; i < MAX_GIC_NR; i++) { | |
db0d4db2 MZ |
551 | #ifdef CONFIG_GIC_NON_BANKED |
552 | /* Skip over unused GICs */ | |
553 | if (!gic_data[i].get_base) | |
554 | continue; | |
555 | #endif | |
254056f3 CC |
556 | switch (cmd) { |
557 | case CPU_PM_ENTER: | |
558 | gic_cpu_save(i); | |
559 | break; | |
560 | case CPU_PM_ENTER_FAILED: | |
561 | case CPU_PM_EXIT: | |
562 | gic_cpu_restore(i); | |
563 | break; | |
564 | case CPU_CLUSTER_PM_ENTER: | |
565 | gic_dist_save(i); | |
566 | break; | |
567 | case CPU_CLUSTER_PM_ENTER_FAILED: | |
568 | case CPU_CLUSTER_PM_EXIT: | |
569 | gic_dist_restore(i); | |
570 | break; | |
571 | } | |
572 | } | |
573 | ||
574 | return NOTIFY_OK; | |
575 | } | |
576 | ||
577 | static struct notifier_block gic_notifier_block = { | |
578 | .notifier_call = gic_notifier, | |
579 | }; | |
580 | ||
581 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
582 | { | |
583 | gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, | |
584 | sizeof(u32)); | |
585 | BUG_ON(!gic->saved_ppi_enable); | |
586 | ||
587 | gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, | |
588 | sizeof(u32)); | |
589 | BUG_ON(!gic->saved_ppi_conf); | |
590 | ||
591 | cpu_pm_register_notifier(&gic_notifier_block); | |
592 | } | |
593 | #else | |
594 | static void __init gic_pm_init(struct gic_chip_data *gic) | |
595 | { | |
596 | } | |
597 | #endif | |
598 | ||
b3f7ed03 RH |
599 | #ifdef CONFIG_OF |
600 | static int gic_irq_domain_dt_translate(struct irq_domain *d, | |
601 | struct device_node *controller, | |
602 | const u32 *intspec, unsigned int intsize, | |
603 | unsigned long *out_hwirq, unsigned int *out_type) | |
604 | { | |
605 | if (d->of_node != controller) | |
606 | return -EINVAL; | |
607 | if (intsize < 3) | |
608 | return -EINVAL; | |
609 | ||
610 | /* Get the interrupt number and add 16 to skip over SGIs */ | |
611 | *out_hwirq = intspec[1] + 16; | |
612 | ||
613 | /* For SPIs, we need to add 16 more to get the GIC irq ID number */ | |
614 | if (!intspec[0]) | |
615 | *out_hwirq += 16; | |
616 | ||
617 | *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; | |
618 | return 0; | |
619 | } | |
620 | #endif | |
621 | ||
4294f8ba | 622 | const struct irq_domain_ops gic_irq_domain_ops = { |
b3f7ed03 RH |
623 | #ifdef CONFIG_OF |
624 | .dt_translate = gic_irq_domain_dt_translate, | |
625 | #endif | |
4294f8ba RH |
626 | }; |
627 | ||
db0d4db2 MZ |
628 | void __init gic_init_bases(unsigned int gic_nr, int irq_start, |
629 | void __iomem *dist_base, void __iomem *cpu_base, | |
630 | u32 percpu_offset) | |
b580b899 | 631 | { |
bef8f9ee | 632 | struct gic_chip_data *gic; |
4294f8ba RH |
633 | struct irq_domain *domain; |
634 | int gic_irqs; | |
bef8f9ee RK |
635 | |
636 | BUG_ON(gic_nr >= MAX_GIC_NR); | |
637 | ||
638 | gic = &gic_data[gic_nr]; | |
4294f8ba | 639 | domain = &gic->domain; |
db0d4db2 MZ |
640 | #ifdef CONFIG_GIC_NON_BANKED |
641 | if (percpu_offset) { /* Frankein-GIC without banked registers... */ | |
642 | unsigned int cpu; | |
643 | ||
644 | gic->dist_base.percpu_base = alloc_percpu(void __iomem *); | |
645 | gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); | |
646 | if (WARN_ON(!gic->dist_base.percpu_base || | |
647 | !gic->cpu_base.percpu_base)) { | |
648 | free_percpu(gic->dist_base.percpu_base); | |
649 | free_percpu(gic->cpu_base.percpu_base); | |
650 | return; | |
651 | } | |
652 | ||
653 | for_each_possible_cpu(cpu) { | |
654 | unsigned long offset = percpu_offset * cpu_logical_map(cpu); | |
655 | *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; | |
656 | *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; | |
657 | } | |
658 | ||
659 | gic_set_base_accessor(gic, gic_get_percpu_base); | |
660 | } else | |
661 | #endif | |
662 | { /* Normal, sane GIC... */ | |
663 | WARN(percpu_offset, | |
664 | "GIC_NON_BANKED not enabled, ignoring %08x offset!", | |
665 | percpu_offset); | |
666 | gic->dist_base.common_base = dist_base; | |
667 | gic->cpu_base.common_base = cpu_base; | |
668 | gic_set_base_accessor(gic, gic_get_common_base); | |
669 | } | |
bef8f9ee | 670 | |
4294f8ba RH |
671 | /* |
672 | * For primary GICs, skip over SGIs. | |
673 | * For secondary GICs, skip over PPIs, too. | |
674 | */ | |
675 | if (gic_nr == 0) { | |
ff2e27ae | 676 | gic_cpu_base_addr = cpu_base; |
4294f8ba | 677 | domain->hwirq_base = 16; |
f37a53cc RH |
678 | if (irq_start > 0) |
679 | irq_start = (irq_start & ~31) + 16; | |
4294f8ba RH |
680 | } else |
681 | domain->hwirq_base = 32; | |
682 | ||
683 | /* | |
684 | * Find out how many interrupts are supported. | |
685 | * The GIC only supports up to 1020 interrupt sources. | |
686 | */ | |
db0d4db2 | 687 | gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; |
4294f8ba RH |
688 | gic_irqs = (gic_irqs + 1) * 32; |
689 | if (gic_irqs > 1020) | |
690 | gic_irqs = 1020; | |
691 | gic->gic_irqs = gic_irqs; | |
692 | ||
693 | domain->nr_irq = gic_irqs - domain->hwirq_base; | |
f37a53cc | 694 | domain->irq_base = irq_alloc_descs(irq_start, 16, domain->nr_irq, |
4294f8ba | 695 | numa_node_id()); |
f37a53cc RH |
696 | if (IS_ERR_VALUE(domain->irq_base)) { |
697 | WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", | |
698 | irq_start); | |
699 | domain->irq_base = irq_start; | |
700 | } | |
4294f8ba RH |
701 | domain->priv = gic; |
702 | domain->ops = &gic_irq_domain_ops; | |
703 | irq_domain_add(domain); | |
bef8f9ee | 704 | |
9c12845e | 705 | gic_chip.flags |= gic_arch_extn.flags; |
4294f8ba | 706 | gic_dist_init(gic); |
bef8f9ee | 707 | gic_cpu_init(gic); |
254056f3 | 708 | gic_pm_init(gic); |
b580b899 RK |
709 | } |
710 | ||
38489533 RK |
711 | void __cpuinit gic_secondary_init(unsigned int gic_nr) |
712 | { | |
bef8f9ee RK |
713 | BUG_ON(gic_nr >= MAX_GIC_NR); |
714 | ||
715 | gic_cpu_init(&gic_data[gic_nr]); | |
38489533 RK |
716 | } |
717 | ||
f27ecacc | 718 | #ifdef CONFIG_SMP |
82668104 | 719 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) |
f27ecacc | 720 | { |
267840f3 WD |
721 | int cpu; |
722 | unsigned long map = 0; | |
723 | ||
724 | /* Convert our logical CPU mask into a physical one. */ | |
725 | for_each_cpu(cpu, mask) | |
726 | map |= 1 << cpu_logical_map(cpu); | |
f27ecacc | 727 | |
6ac77e46 SS |
728 | /* |
729 | * Ensure that stores to Normal memory are visible to the | |
730 | * other CPUs before issuing the IPI. | |
731 | */ | |
732 | dsb(); | |
733 | ||
b3a1bde4 | 734 | /* this always happens on GIC0 */ |
db0d4db2 | 735 | writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); |
f27ecacc RK |
736 | } |
737 | #endif | |
b3f7ed03 RH |
738 | |
739 | #ifdef CONFIG_OF | |
740 | static int gic_cnt __initdata = 0; | |
741 | ||
742 | int __init gic_of_init(struct device_node *node, struct device_node *parent) | |
743 | { | |
744 | void __iomem *cpu_base; | |
745 | void __iomem *dist_base; | |
db0d4db2 | 746 | u32 percpu_offset; |
b3f7ed03 RH |
747 | int irq; |
748 | struct irq_domain *domain = &gic_data[gic_cnt].domain; | |
749 | ||
750 | if (WARN_ON(!node)) | |
751 | return -ENODEV; | |
752 | ||
753 | dist_base = of_iomap(node, 0); | |
754 | WARN(!dist_base, "unable to map gic dist registers\n"); | |
755 | ||
756 | cpu_base = of_iomap(node, 1); | |
757 | WARN(!cpu_base, "unable to map gic cpu registers\n"); | |
758 | ||
db0d4db2 MZ |
759 | if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) |
760 | percpu_offset = 0; | |
761 | ||
b3f7ed03 RH |
762 | domain->of_node = of_node_get(node); |
763 | ||
db0d4db2 | 764 | gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset); |
b3f7ed03 RH |
765 | |
766 | if (parent) { | |
767 | irq = irq_of_parse_and_map(node, 0); | |
768 | gic_cascade_irq(gic_cnt, irq); | |
769 | } | |
770 | gic_cnt++; | |
771 | return 0; | |
772 | } | |
773 | #endif |