[deliverable/linux.git] / arch / arm / common / icst.c

/*
 *  linux/arch/arm/common/icst307.c
 *
 *  Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  Support functions for calculating clocks/divisors for the ICST307
 *  clock generators.  See http://www.idt.com/ for more information
 *  on these devices.
 *
 *  This is an almost identical implementation to the ICST525 clock generator.
 *  The s2div and idx2s files are different
 */
#include <linux/module.h>
#include <linux/kernel.h>
#include <asm/div64.h>
#include <asm/hardware/icst.h>

/*
 * Divisors for each OD setting.
 */
const unsigned char icst307_s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 };
const unsigned char icst525_s2div[8] = { 10, 2, 8, 4, 5, 7, 9, 6 };
EXPORT_SYMBOL(icst307_s2div);
EXPORT_SYMBOL(icst525_s2div);

unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco)
{
	u64 dividend = p->ref * 2 * (u64)(vco.v + 8);
	u32 divisor = (vco.r + 2) * p->s2div[vco.s];

	do_div(dividend, divisor);
	return (unsigned long)dividend;
}

EXPORT_SYMBOL(icst_hz);

/*
 * Ascending divisor S values.
 */
const unsigned char icst307_idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 };
const unsigned char icst525_idx2s[8] = { 1, 3, 4, 7, 5, 2, 6, 0 };
EXPORT_SYMBOL(icst307_idx2s);
EXPORT_SYMBOL(icst525_idx2s);

struct icst_vco
icst_hz_to_vco(const struct icst_params *p, unsigned long freq)
{
	struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
	unsigned long f;
	unsigned int i = 0, rd, best = (unsigned int)-1;

	/*
	 * First, find the PLL output divisor such
	 * that the PLL output is within spec.
	 */
	do {
		f = freq * p->s2div[p->idx2s[i]];

		if (f > p->vco_min && f <= p->vco_max)
			break;
		i++;
	} while (i < 8);

	if (i >= 8)
		return vco;

	vco.s = p->idx2s[i];

	/*
	 * Now find the closest divisor combination
	 * which gives a PLL output of 'f'.
	 */
	for (rd = p->rd_min; rd <= p->rd_max; rd++) {
		unsigned long fref_div, f_pll;
		unsigned int vd;
		int f_diff;

		fref_div = (2 * p->ref) / rd;

		vd = (f + fref_div / 2) / fref_div;
		if (vd < p->vd_min || vd > p->vd_max)
			continue;

		f_pll = fref_div * vd;
		f_diff = f_pll - f;
		if (f_diff < 0)
			f_diff = -f_diff;

		if ((unsigned)f_diff < best) {
			vco.v = vd - 8;
			vco.r = rd - 2;
			if (f_diff == 0)
				break;
			best = f_diff;
		}
	}

	return vco;
}

EXPORT_SYMBOL(icst_hz_to_vco);
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/common/icst307.c
	3	*
	4	* Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Support functions for calculating clocks/divisors for the ICST307
50a23e6e	11	* clock generators. See http://www.idt.com/ for more information
1da177e4 LT	12	* on these devices.
	13	*
	14	* This is an almost identical implementation to the ICST525 clock generator.
	15	* The s2div and idx2s files are different
	16	*/
	17	#include <linux/module.h>
	18	#include <linux/kernel.h>
5070fb14	19	#include <asm/div64.h>
c5a0adb5	20	#include <asm/hardware/icst.h>
1da177e4 LT	21
	22	/*
	23	* Divisors for each OD setting.
	24	*/
232eaf7f	25	const unsigned char icst307_s2div[8] = { 10, 2, 8, 4, 5, 7, 3, 6 };
c5a0adb5	26	const unsigned char icst525_s2div[8] = { 10, 2, 8, 4, 5, 7, 9, 6 };
232eaf7f	27	EXPORT_SYMBOL(icst307_s2div);
c5a0adb5	28	EXPORT_SYMBOL(icst525_s2div);
1da177e4	29
c5a0adb5	30	unsigned long icst_hz(const struct icst_params *p, struct icst_vco vco)
1da177e4	31	{
5070fb14 LW	32	u64 dividend = p->ref * 2 * (u64)(vco.v + 8);
	33	u32 divisor = (vco.r + 2) * p->s2div[vco.s];
	34
	35	do_div(dividend, divisor);
	36	return (unsigned long)dividend;
1da177e4 LT	37	}
1da177e4 LT	38
c5a0adb5	39	EXPORT_SYMBOL(icst_hz);
1da177e4 LT	40
	41	/*
	42	* Ascending divisor S values.
	43	*/
232eaf7f	44	const unsigned char icst307_idx2s[8] = { 1, 6, 3, 4, 7, 5, 2, 0 };
c5a0adb5	45	const unsigned char icst525_idx2s[8] = { 1, 3, 4, 7, 5, 2, 6, 0 };
232eaf7f	46	EXPORT_SYMBOL(icst307_idx2s);
c5a0adb5	47	EXPORT_SYMBOL(icst525_idx2s);
1da177e4	48
39c0cb02	49	struct icst_vco
c5a0adb5	50	icst_hz_to_vco(const struct icst_params *p, unsigned long freq)
1da177e4	51	{
39c0cb02	52	struct icst_vco vco = { .s = 1, .v = p->vd_max, .r = p->rd_max };
1da177e4 LT	53	unsigned long f;
	54	unsigned int i = 0, rd, best = (unsigned int)-1;
	55
	56	/*
	57	* First, find the PLL output divisor such
	58	* that the PLL output is within spec.
	59	*/
	60	do {
232eaf7f	61	f = freq * p->s2div[p->idx2s[i]];
1da177e4	62
e73a46a3	63	if (f > p->vco_min && f <= p->vco_max)
1da177e4	64	break;
e972c374	65	i++;
232eaf7f	66	} while (i < 8);
1da177e4	67
232eaf7f	68	if (i >= 8)
1da177e4 LT	69	return vco;
1da177e4 LT	70
232eaf7f	71	vco.s = p->idx2s[i];
1da177e4 LT	72
	73	/*
	74	* Now find the closest divisor combination
	75	* which gives a PLL output of 'f'.
	76	*/
	77	for (rd = p->rd_min; rd <= p->rd_max; rd++) {
	78	unsigned long fref_div, f_pll;
	79	unsigned int vd;
	80	int f_diff;
	81
	82	fref_div = (2 * p->ref) / rd;
	83
	84	vd = (f + fref_div / 2) / fref_div;
	85	if (vd < p->vd_min \|\| vd > p->vd_max)
	86	continue;
	87
	88	f_pll = fref_div * vd;
	89	f_diff = f_pll - f;
	90	if (f_diff < 0)
	91	f_diff = -f_diff;
	92
	93	if ((unsigned)f_diff < best) {
	94	vco.v = vd - 8;
	95	vco.r = rd - 2;
	96	if (f_diff == 0)
	97	break;
	98	best = f_diff;
	99	}
	100	}
	101
	102	return vco;
	103	}
	104
c5a0adb5	105	EXPORT_SYMBOL(icst_hz_to_vco);