[deliverable/linux.git] / arch / arm / common / uengine.c

/*
 * Generic library functions for the microengines found on the Intel
 * IXP2000 series of network processors.
 *
 * Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
 * Dedicated to Marija Kulikova.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU Lesser General Public License as
 * published by the Free Software Foundation; either version 2.1 of the
 * License, or (at your option) any later version.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/string.h>
#include <asm/hardware.h>
#include <asm/arch/hardware.h>
#include <asm/hardware/uengine.h>
#include <asm/io.h>

#if defined(CONFIG_ARCH_IXP2000)
#define IXP_UENGINE_CSR_VIRT_BASE	IXP2000_UENGINE_CSR_VIRT_BASE
#define IXP_PRODUCT_ID			IXP2000_PRODUCT_ID
#define IXP_MISC_CONTROL		IXP2000_MISC_CONTROL
#define IXP_RESET1			IXP2000_RESET1
#else
#if defined(CONFIG_ARCH_IXP23XX)
#define IXP_UENGINE_CSR_VIRT_BASE	IXP23XX_UENGINE_CSR_VIRT_BASE
#define IXP_PRODUCT_ID			IXP23XX_PRODUCT_ID
#define IXP_MISC_CONTROL		IXP23XX_MISC_CONTROL
#define IXP_RESET1			IXP23XX_RESET1
#else
#error unknown platform
#endif
#endif

#define USTORE_ADDRESS			0x000
#define USTORE_DATA_LOWER		0x004
#define USTORE_DATA_UPPER		0x008
#define CTX_ENABLES			0x018
#define CC_ENABLE			0x01c
#define CSR_CTX_POINTER			0x020
#define INDIRECT_CTX_STS		0x040
#define ACTIVE_CTX_STS			0x044
#define INDIRECT_CTX_SIG_EVENTS		0x048
#define INDIRECT_CTX_WAKEUP_EVENTS	0x050
#define NN_PUT				0x080
#define NN_GET				0x084
#define TIMESTAMP_LOW			0x0c0
#define TIMESTAMP_HIGH			0x0c4
#define T_INDEX_BYTE_INDEX		0x0f4
#define LOCAL_CSR_STATUS		0x180

u32 ixp2000_uengine_mask;

static void *ixp2000_uengine_csr_area(int uengine)
{
	return ((void *)IXP_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
}

/*
 * LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR
 * space means that the microengine we tried to access was also trying
 * to access its own CSR space on the same clock cycle as we did.  When
 * this happens, we lose the arbitration process by default, and the
 * read or write we tried to do was not actually performed, so we try
 * again until it succeeds.
 */
u32 ixp2000_uengine_csr_read(int uengine, int offset)
{
	void *uebase;
	u32 *local_csr_status;
	u32 *reg;
	u32 value;

	uebase = ixp2000_uengine_csr_area(uengine);

	local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
	reg = (u32 *)(uebase + offset);
	do {
		value = ixp2000_reg_read(reg);
	} while (ixp2000_reg_read(local_csr_status) & 1);

	return value;
}
EXPORT_SYMBOL(ixp2000_uengine_csr_read);

void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
{
	void *uebase;
	u32 *local_csr_status;
	u32 *reg;

	uebase = ixp2000_uengine_csr_area(uengine);

	local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
	reg = (u32 *)(uebase + offset);
	do {
		ixp2000_reg_write(reg, value);
	} while (ixp2000_reg_read(local_csr_status) & 1);
}
EXPORT_SYMBOL(ixp2000_uengine_csr_write);

void ixp2000_uengine_reset(u32 uengine_mask)
{
	u32 value;

	value = ixp2000_reg_read(IXP_RESET1) & ~ixp2000_uengine_mask;

	uengine_mask &= ixp2000_uengine_mask;
	ixp2000_reg_wrb(IXP_RESET1, value | uengine_mask);
	ixp2000_reg_wrb(IXP_RESET1, value);
}
EXPORT_SYMBOL(ixp2000_uengine_reset);

void ixp2000_uengine_set_mode(int uengine, u32 mode)
{
	/*
	 * CTL_STR_PAR_EN: unconditionally enable parity checking on
	 * control store.
	 */
	mode |= 0x10000000;
	ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);

	/*
	 * Enable updating of condition codes.
	 */
	ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);

	/*
	 * Initialise other per-microengine registers.
	 */
	ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
	ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
	ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
}
EXPORT_SYMBOL(ixp2000_uengine_set_mode);

static int make_even_parity(u32 x)
{
	return hweight32(x) & 1;
}

static void ustore_write(int uengine, u64 insn)
{
	/*
	 * Generate even parity for top and bottom 20 bits.
	 */
	insn |= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41;
	insn |= (u64)make_even_parity(insn & 0x000fffff) << 40;

	/*
	 * Write to microstore.  The second write auto-increments
	 * the USTORE_ADDRESS index register.
	 */
	ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
	ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
}

void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
{
	int i;

	/*
	 * Start writing to microstore at address 0.
	 */
	ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
	for (i = 0; i < insns; i++) {
		u64 insn;

		insn = (((u64)ucode[0]) << 32) |
			(((u64)ucode[1]) << 24) |
			(((u64)ucode[2]) << 16) |
			(((u64)ucode[3]) << 8) |
			((u64)ucode[4]);
		ucode += 5;

		ustore_write(uengine, insn);
	}

	/*
 	 * Pad with a few NOPs at the end (to avoid the microengine
	 * aborting as it prefetches beyond the last instruction), unless
	 * we run off the end of the instruction store first, at which
	 * point the address register will wrap back to zero.
	 */
	for (i = 0; i < 4; i++) {
		u32 addr;

		addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
		if (addr == 0x80000000)
			break;
		ustore_write(uengine, 0xf0000c0300ULL);
	}

	/*
	 * End programming.
	 */
	ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
}
EXPORT_SYMBOL(ixp2000_uengine_load_microcode);

void ixp2000_uengine_init_context(int uengine, int context, int pc)
{
	/*
	 * Select the right context for indirect access.
	 */
	ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);

	/*
	 * Initialise signal masks to immediately go to Ready state.
	 */
	ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
	ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);

	/*
	 * Set program counter.
	 */
	ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
}
EXPORT_SYMBOL(ixp2000_uengine_init_context);

void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
{
	u32 mask;

	/*
	 * Enable the specified context to go to Executing state.
	 */
	mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
	mask |= ctx_mask << 8;
	ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
}
EXPORT_SYMBOL(ixp2000_uengine_start_contexts);

void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
{
	u32 mask;

	/*
	 * Disable the Ready->Executing transition.  Note that this
	 * does not stop the context until it voluntarily yields.
	 */
	mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
	mask &= ~(ctx_mask << 8);
	ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
}
EXPORT_SYMBOL(ixp2000_uengine_stop_contexts);

static int check_ixp_type(struct ixp2000_uengine_code *c)
{
	u32 product_id;
	u32 rev;

	product_id = ixp2000_reg_read(IXP_PRODUCT_ID);
	if (((product_id >> 16) & 0x1f) != 0)
		return 0;

	switch ((product_id >> 8) & 0xff) {
#ifdef CONFIG_ARCH_IXP2000
	case 0:		/* IXP2800 */
		if (!(c->cpu_model_bitmask & 4))
			return 0;
		break;

	case 1:		/* IXP2850 */
		if (!(c->cpu_model_bitmask & 8))
			return 0;
		break;

	case 2:		/* IXP2400 */
		if (!(c->cpu_model_bitmask & 2))
			return 0;
		break;
#endif

#ifdef CONFIG_ARCH_IXP23XX
	case 4:		/* IXP23xx */
		if (!(c->cpu_model_bitmask & 0x3f0))
			return 0;
		break;
#endif

	default:
		return 0;
	}

	rev = product_id & 0xff;
	if (rev < c->cpu_min_revision || rev > c->cpu_max_revision)
		return 0;

	return 1;
}

static void generate_ucode(u8 *ucode, u32 *gpr_a, u32 *gpr_b)
{
	int offset;
	int i;

	offset = 0;

	for (i = 0; i < 128; i++) {
		u8 b3;
		u8 b2;
		u8 b1;
		u8 b0;

		b3 = (gpr_a[i] >> 24) & 0xff;
		b2 = (gpr_a[i] >> 16) & 0xff;
		b1 = (gpr_a[i] >> 8) & 0xff;
		b0 = gpr_a[i] & 0xff;

		// immed[@ai, (b1 << 8) | b0]
		// 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII
		ucode[offset++] = 0xf0;
		ucode[offset++] = (b1 >> 4);
		ucode[offset++] = (b1 << 4) | 0x0c | (b0 >> 6);
		ucode[offset++] = (b0 << 2);
		ucode[offset++] = 0x80 | i;

		// immed_w1[@ai, (b3 << 8) | b2]
		// 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII
		ucode[offset++] = 0xf4;
		ucode[offset++] = 0x40 | (b3 >> 4);
		ucode[offset++] = (b3 << 4) | 0x0c | (b2 >> 6);
		ucode[offset++] = (b2 << 2);
		ucode[offset++] = 0x80 | i;
	}

	for (i = 0; i < 128; i++) {
		u8 b3;
		u8 b2;
		u8 b1;
		u8 b0;

		b3 = (gpr_b[i] >> 24) & 0xff;
		b2 = (gpr_b[i] >> 16) & 0xff;
		b1 = (gpr_b[i] >> 8) & 0xff;
		b0 = gpr_b[i] & 0xff;

		// immed[@bi, (b1 << 8) | b0]
		// 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV
		ucode[offset++] = 0xf0;
		ucode[offset++] = (b1 >> 4);
		ucode[offset++] = (b1 << 4) | 0x02 | (i >> 6);
		ucode[offset++] = (i << 2) | 0x03;
		ucode[offset++] = b0;

		// immed_w1[@bi, (b3 << 8) | b2]
		// 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV
		ucode[offset++] = 0xf4;
		ucode[offset++] = 0x40 | (b3 >> 4);
		ucode[offset++] = (b3 << 4) | 0x02 | (i >> 6);
		ucode[offset++] = (i << 2) | 0x03;
		ucode[offset++] = b2;
	}

	// ctx_arb[kill]
	ucode[offset++] = 0xe0;
	ucode[offset++] = 0x00;
	ucode[offset++] = 0x01;
	ucode[offset++] = 0x00;
	ucode[offset++] = 0x00;
}

static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
{
	int per_ctx_regs;
	u32 *gpr_a;
	u32 *gpr_b;
	u8 *ucode;
	int i;

	gpr_a = kzalloc(128 * sizeof(u32), GFP_KERNEL);
	gpr_b = kzalloc(128 * sizeof(u32), GFP_KERNEL);
	ucode = kmalloc(513 * 5, GFP_KERNEL);
	if (gpr_a == NULL || gpr_b == NULL || ucode == NULL) {
		kfree(ucode);
		kfree(gpr_b);
		kfree(gpr_a);
		return 1;
	}

	per_ctx_regs = 16;
	if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS)
		per_ctx_regs = 32;

	for (i = 0; i < 256; i++) {
		struct ixp2000_reg_value *r = c->initial_reg_values + i;
		u32 *bank;
		int inc;
		int j;

		if (r->reg == -1)
			break;

		bank = (r->reg & 0x400) ? gpr_b : gpr_a;
		inc = (r->reg & 0x80) ? 128 : per_ctx_regs;

		j = r->reg & 0x7f;
		while (j < 128) {
			bank[j] = r->value;
			j += inc;
		}
	}

	generate_ucode(ucode, gpr_a, gpr_b);
	ixp2000_uengine_load_microcode(uengine, ucode, 513);
	ixp2000_uengine_init_context(uengine, 0, 0);
	ixp2000_uengine_start_contexts(uengine, 0x01);
	for (i = 0; i < 100; i++) {
		u32 status;

		status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
		if (!(status & 0x80000000))
			break;
	}
	ixp2000_uengine_stop_contexts(uengine, 0x01);

	kfree(ucode);
	kfree(gpr_b);
	kfree(gpr_a);

	return !!(i == 100);
}

int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
{
	int ctx;

	if (!check_ixp_type(c))
		return 1;

	if (!(ixp2000_uengine_mask & (1 << uengine)))
		return 1;

	ixp2000_uengine_reset(1 << uengine);
	ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
	if (set_initial_registers(uengine, c))
		return 1;
	ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);

	for (ctx = 0; ctx < 8; ctx++)
		ixp2000_uengine_init_context(uengine, ctx, 0);

	return 0;
}
EXPORT_SYMBOL(ixp2000_uengine_load);


static int __init ixp2000_uengine_init(void)
{
	int uengine;
	u32 value;

	/*
	 * Determine number of microengines present.
	 */
	switch ((ixp2000_reg_read(IXP_PRODUCT_ID) >> 8) & 0x1fff) {
#ifdef CONFIG_ARCH_IXP2000
	case 0:		/* IXP2800 */
	case 1:		/* IXP2850 */
		ixp2000_uengine_mask = 0x00ff00ff;
		break;

	case 2:		/* IXP2400 */
		ixp2000_uengine_mask = 0x000f000f;
		break;
#endif

#ifdef CONFIG_ARCH_IXP23XX
	case 4:		/* IXP23xx */
		ixp2000_uengine_mask = (*IXP23XX_EXP_CFG_FUSE >> 8) & 0xf;
		break;
#endif

	default:
		printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n",
			(unsigned int)ixp2000_reg_read(IXP_PRODUCT_ID));
		ixp2000_uengine_mask = 0x00000000;
		break;
	}

	/*
	 * Reset microengines.
	 */
	ixp2000_uengine_reset(ixp2000_uengine_mask);

	/*
	 * Synchronise timestamp counters across all microengines.
	 */
	value = ixp2000_reg_read(IXP_MISC_CONTROL);
	ixp2000_reg_wrb(IXP_MISC_CONTROL, value & ~0x80);
	for (uengine = 0; uengine < 32; uengine++) {
		if (ixp2000_uengine_mask & (1 << uengine)) {
			ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
			ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
		}
	}
	ixp2000_reg_wrb(IXP_MISC_CONTROL, value | 0x80);

	return 0;
}

subsys_initcall(ixp2000_uengine_init);
Commit	Line	Data
d01e8897 LB	1	/*
	2	* Generic library functions for the microengines found on the Intel
	3	* IXP2000 series of network processors.
	4	*
	5	* Copyright (C) 2004, 2005 Lennert Buytenhek <buytenh@wantstofly.org>
	6	* Dedicated to Marija Kulikova.
	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU Lesser General Public License as
	10	* published by the Free Software Foundation; either version 2.1 of the
	11	* License, or (at your option) any later version.
	12	*/
	13
d01e8897 LB	14	#include <linux/kernel.h>
	15	#include <linux/init.h>
	16	#include <linux/slab.h>
	17	#include <linux/module.h>
	18	#include <linux/string.h>
	19	#include <asm/hardware.h>
8b76a68c	20	#include <asm/arch/hardware.h>
18ec5c73	21	#include <asm/hardware/uengine.h>
d01e8897 LB	22	#include <asm/io.h>
d01e8897 LB	23
8b76a68c LB	24	#if defined(CONFIG_ARCH_IXP2000)
	25	#define IXP_UENGINE_CSR_VIRT_BASE IXP2000_UENGINE_CSR_VIRT_BASE
	26	#define IXP_PRODUCT_ID IXP2000_PRODUCT_ID
	27	#define IXP_MISC_CONTROL IXP2000_MISC_CONTROL
	28	#define IXP_RESET1 IXP2000_RESET1
	29	#else
	30	#if defined(CONFIG_ARCH_IXP23XX)
	31	#define IXP_UENGINE_CSR_VIRT_BASE IXP23XX_UENGINE_CSR_VIRT_BASE
	32	#define IXP_PRODUCT_ID IXP23XX_PRODUCT_ID
	33	#define IXP_MISC_CONTROL IXP23XX_MISC_CONTROL
	34	#define IXP_RESET1 IXP23XX_RESET1
	35	#else
	36	#error unknown platform
	37	#endif
	38	#endif
	39
d01e8897 LB	40	#define USTORE_ADDRESS 0x000
	41	#define USTORE_DATA_LOWER 0x004
	42	#define USTORE_DATA_UPPER 0x008
	43	#define CTX_ENABLES 0x018
	44	#define CC_ENABLE 0x01c
	45	#define CSR_CTX_POINTER 0x020
	46	#define INDIRECT_CTX_STS 0x040
	47	#define ACTIVE_CTX_STS 0x044
	48	#define INDIRECT_CTX_SIG_EVENTS 0x048
	49	#define INDIRECT_CTX_WAKEUP_EVENTS 0x050
	50	#define NN_PUT 0x080
	51	#define NN_GET 0x084
	52	#define TIMESTAMP_LOW 0x0c0
	53	#define TIMESTAMP_HIGH 0x0c4
	54	#define T_INDEX_BYTE_INDEX 0x0f4
	55	#define LOCAL_CSR_STATUS 0x180
	56
	57	u32 ixp2000_uengine_mask;
	58
	59	static void *ixp2000_uengine_csr_area(int uengine)
	60	{
8b76a68c	61	return ((void *)IXP_UENGINE_CSR_VIRT_BASE) + (uengine << 10);
d01e8897 LB	62	}
	63
	64	/*
	65	* LOCAL_CSR_STATUS=1 after a read or write to a microengine's CSR
	66	* space means that the microengine we tried to access was also trying
	67	* to access its own CSR space on the same clock cycle as we did. When
	68	* this happens, we lose the arbitration process by default, and the
	69	* read or write we tried to do was not actually performed, so we try
	70	* again until it succeeds.
	71	*/
	72	u32 ixp2000_uengine_csr_read(int uengine, int offset)
	73	{
	74	void *uebase;
	75	u32 *local_csr_status;
	76	u32 *reg;
	77	u32 value;
	78
	79	uebase = ixp2000_uengine_csr_area(uengine);
	80
	81	local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
	82	reg = (u32 *)(uebase + offset);
	83	do {
	84	value = ixp2000_reg_read(reg);
	85	} while (ixp2000_reg_read(local_csr_status) & 1);
	86
	87	return value;
	88	}
	89	EXPORT_SYMBOL(ixp2000_uengine_csr_read);
	90
	91	void ixp2000_uengine_csr_write(int uengine, int offset, u32 value)
	92	{
	93	void *uebase;
	94	u32 *local_csr_status;
	95	u32 *reg;
	96
	97	uebase = ixp2000_uengine_csr_area(uengine);
	98
	99	local_csr_status = (u32 *)(uebase + LOCAL_CSR_STATUS);
	100	reg = (u32 *)(uebase + offset);
	101	do {
	102	ixp2000_reg_write(reg, value);
	103	} while (ixp2000_reg_read(local_csr_status) & 1);
	104	}
	105	EXPORT_SYMBOL(ixp2000_uengine_csr_write);
	106
	107	void ixp2000_uengine_reset(u32 uengine_mask)
	108	{
8b76a68c LB	109	u32 value;
	110
	111	value = ixp2000_reg_read(IXP_RESET1) & ~ixp2000_uengine_mask;
	112
	113	uengine_mask &= ixp2000_uengine_mask;
	114	ixp2000_reg_wrb(IXP_RESET1, value \| uengine_mask);
	115	ixp2000_reg_wrb(IXP_RESET1, value);
d01e8897 LB	116	}
	117	EXPORT_SYMBOL(ixp2000_uengine_reset);
	118
	119	void ixp2000_uengine_set_mode(int uengine, u32 mode)
	120	{
	121	/*
	122	* CTL_STR_PAR_EN: unconditionally enable parity checking on
	123	* control store.
	124	*/
	125	mode \|= 0x10000000;
	126	ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mode);
	127
	128	/*
	129	* Enable updating of condition codes.
	130	*/
	131	ixp2000_uengine_csr_write(uengine, CC_ENABLE, 0x00002000);
	132
	133	/*
	134	* Initialise other per-microengine registers.
	135	*/
	136	ixp2000_uengine_csr_write(uengine, NN_PUT, 0x00);
	137	ixp2000_uengine_csr_write(uengine, NN_GET, 0x00);
	138	ixp2000_uengine_csr_write(uengine, T_INDEX_BYTE_INDEX, 0);
	139	}
	140	EXPORT_SYMBOL(ixp2000_uengine_set_mode);
	141
	142	static int make_even_parity(u32 x)
	143	{
	144	return hweight32(x) & 1;
	145	}
	146
	147	static void ustore_write(int uengine, u64 insn)
	148	{
	149	/*
	150	* Generate even parity for top and bottom 20 bits.
	151	*/
	152	insn \|= (u64)make_even_parity((insn >> 20) & 0x000fffff) << 41;
	153	insn \|= (u64)make_even_parity(insn & 0x000fffff) << 40;
	154
	155	/*
	156	* Write to microstore. The second write auto-increments
	157	* the USTORE_ADDRESS index register.
	158	*/
	159	ixp2000_uengine_csr_write(uengine, USTORE_DATA_LOWER, (u32)insn);
	160	ixp2000_uengine_csr_write(uengine, USTORE_DATA_UPPER, (u32)(insn >> 32));
	161	}
	162
	163	void ixp2000_uengine_load_microcode(int uengine, u8 *ucode, int insns)
	164	{
	165	int i;
	166
	167	/*
	168	* Start writing to microstore at address 0.
	169	*/
	170	ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x80000000);
	171	for (i = 0; i < insns; i++) {
	172	u64 insn;
	173
	174	insn = (((u64)ucode[0]) << 32) \|
	175	(((u64)ucode[1]) << 24) \|
	176	(((u64)ucode[2]) << 16) \|
	177	(((u64)ucode[3]) << 8) \|
	178	((u64)ucode[4]);
	179	ucode += 5;
180
181	ustore_write(uengine, insn);
182	}
183
184	/*
185	* Pad with a few NOPs at the end (to avoid the microengine
186	* aborting as it prefetches beyond the last instruction), unless
187	* we run off the end of the instruction store first, at which
188	* point the address register will wrap back to zero.
189	*/
190	for (i = 0; i < 4; i++) {
191	u32 addr;
192
193	addr = ixp2000_uengine_csr_read(uengine, USTORE_ADDRESS);
194	if (addr == 0x80000000)
195	break;
196	ustore_write(uengine, 0xf0000c0300ULL);
197	}
198
199	/*
200	* End programming.
201	*/
202	ixp2000_uengine_csr_write(uengine, USTORE_ADDRESS, 0x00000000);
203	}
204	EXPORT_SYMBOL(ixp2000_uengine_load_microcode);
205
206	void ixp2000_uengine_init_context(int uengine, int context, int pc)
207	{
208	/*
209	* Select the right context for indirect access.
210	*/
211	ixp2000_uengine_csr_write(uengine, CSR_CTX_POINTER, context);
212
213	/*
214	* Initialise signal masks to immediately go to Ready state.
215	*/
216	ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_SIG_EVENTS, 1);
217	ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_WAKEUP_EVENTS, 1);
218
219	/*
220	* Set program counter.
221	*/
222	ixp2000_uengine_csr_write(uengine, INDIRECT_CTX_STS, pc);
223	}
224	EXPORT_SYMBOL(ixp2000_uengine_init_context);
225
226	void ixp2000_uengine_start_contexts(int uengine, u8 ctx_mask)
227	{
228	u32 mask;
229
230	/*
231	* Enable the specified context to go to Executing state.
232	*/
233	mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
234	mask \|= ctx_mask << 8;
235	ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
236	}
237	EXPORT_SYMBOL(ixp2000_uengine_start_contexts);
238
239	void ixp2000_uengine_stop_contexts(int uengine, u8 ctx_mask)
240	{
241	u32 mask;
242
243	/*
244	* Disable the Ready->Executing transition. Note that this
245	* does not stop the context until it voluntarily yields.
246	*/
247	mask = ixp2000_uengine_csr_read(uengine, CTX_ENABLES);
248	mask &= ~(ctx_mask << 8);
249	ixp2000_uengine_csr_write(uengine, CTX_ENABLES, mask);
250	}
251	EXPORT_SYMBOL(ixp2000_uengine_stop_contexts);
252
253	static int check_ixp_type(struct ixp2000_uengine_code *c)
254	{
255	u32 product_id;
256	u32 rev;
257
8b76a68c	258	product_id = ixp2000_reg_read(IXP_PRODUCT_ID);
d01e8897 LB	259	if (((product_id >> 16) & 0x1f) != 0)
	260	return 0;
	261
	262	switch ((product_id >> 8) & 0xff) {
8b76a68c	263	#ifdef CONFIG_ARCH_IXP2000
d01e8897 LB	264	case 0: /* IXP2800 */
	265	if (!(c->cpu_model_bitmask & 4))
	266	return 0;
	267	break;
	268
	269	case 1: /* IXP2850 */
	270	if (!(c->cpu_model_bitmask & 8))
	271	return 0;
	272	break;
	273
	274	case 2: /* IXP2400 */
	275	if (!(c->cpu_model_bitmask & 2))
	276	return 0;
	277	break;
8b76a68c LB	278	#endif
	279
	280	#ifdef CONFIG_ARCH_IXP23XX
	281	case 4: /* IXP23xx */
	282	if (!(c->cpu_model_bitmask & 0x3f0))
	283	return 0;
	284	break;
	285	#endif
d01e8897 LB	286
	287	default:
	288	return 0;
	289	}
	290
	291	rev = product_id & 0xff;
	292	if (rev < c->cpu_min_revision \|\| rev > c->cpu_max_revision)
	293	return 0;
	294
	295	return 1;
	296	}
	297
	298	static void generate_ucode(u8 ucode, u32 gpr_a, u32 *gpr_b)
	299	{
	300	int offset;
	301	int i;
	302
	303	offset = 0;
	304
	305	for (i = 0; i < 128; i++) {
	306	u8 b3;
	307	u8 b2;
	308	u8 b1;
	309	u8 b0;
	310
	311	b3 = (gpr_a[i] >> 24) & 0xff;
	312	b2 = (gpr_a[i] >> 16) & 0xff;
	313	b1 = (gpr_a[i] >> 8) & 0xff;
	314	b0 = gpr_a[i] & 0xff;
	315
	316	// immed[@ai, (b1 << 8) \| b0]
	317	// 11110000 0000VVVV VVVV11VV VVVVVV00 1IIIIIII
	318	ucode[offset++] = 0xf0;
	319	ucode[offset++] = (b1 >> 4);
	320	ucode[offset++] = (b1 << 4) \| 0x0c \| (b0 >> 6);
	321	ucode[offset++] = (b0 << 2);
	322	ucode[offset++] = 0x80 \| i;
	323
	324	// immed_w1[@ai, (b3 << 8) \| b2]
	325	// 11110100 0100VVVV VVVV11VV VVVVVV00 1IIIIIII
	326	ucode[offset++] = 0xf4;
	327	ucode[offset++] = 0x40 \| (b3 >> 4);
	328	ucode[offset++] = (b3 << 4) \| 0x0c \| (b2 >> 6);
	329	ucode[offset++] = (b2 << 2);
	330	ucode[offset++] = 0x80 \| i;
	331	}
	332
	333	for (i = 0; i < 128; i++) {
	334	u8 b3;
	335	u8 b2;
	336	u8 b1;
	337	u8 b0;
	338
	339	b3 = (gpr_b[i] >> 24) & 0xff;
	340	b2 = (gpr_b[i] >> 16) & 0xff;
	341	b1 = (gpr_b[i] >> 8) & 0xff;
	342	b0 = gpr_b[i] & 0xff;
	343
	344	// immed[@bi, (b1 << 8) \| b0]
	345	// 11110000 0000VVVV VVVV001I IIIIII11 VVVVVVVV
	346	ucode[offset++] = 0xf0;
	347	ucode[offset++] = (b1 >> 4);
	348	ucode[offset++] = (b1 << 4) \| 0x02 \| (i >> 6);
	349	ucode[offset++] = (i << 2) \| 0x03;
350	ucode[offset++] = b0;
351
352	// immed_w1[@bi, (b3 << 8) \| b2]
353	// 11110100 0100VVVV VVVV001I IIIIII11 VVVVVVVV
354	ucode[offset++] = 0xf4;
355	ucode[offset++] = 0x40 \| (b3 >> 4);
356	ucode[offset++] = (b3 << 4) \| 0x02 \| (i >> 6);
357	ucode[offset++] = (i << 2) \| 0x03;
358	ucode[offset++] = b2;
359	}
360
361	// ctx_arb[kill]
362	ucode[offset++] = 0xe0;
363	ucode[offset++] = 0x00;
364	ucode[offset++] = 0x01;
365	ucode[offset++] = 0x00;
366	ucode[offset++] = 0x00;
367	}
368
369	static int set_initial_registers(int uengine, struct ixp2000_uengine_code *c)
370	{
371	int per_ctx_regs;
372	u32 *gpr_a;
373	u32 *gpr_b;
374	u8 *ucode;
375	int i;
376
dc49cb21 LZ	377	gpr_a = kzalloc(128 * sizeof(u32), GFP_KERNEL);
dc49cb21 LZ	378	gpr_b = kzalloc(128 * sizeof(u32), GFP_KERNEL);
d01e8897 LB	379	ucode = kmalloc(513 * 5, GFP_KERNEL);
	380	if (gpr_a == NULL \|\| gpr_b == NULL \|\| ucode == NULL) {
	381	kfree(ucode);
	382	kfree(gpr_b);
	383	kfree(gpr_a);
	384	return 1;
	385	}
	386
	387	per_ctx_regs = 16;
	388	if (c->uengine_parameters & IXP2000_UENGINE_4_CONTEXTS)
	389	per_ctx_regs = 32;
	390
d01e8897 LB	391	for (i = 0; i < 256; i++) {
	392	struct ixp2000_reg_value *r = c->initial_reg_values + i;
	393	u32 *bank;
	394	int inc;
	395	int j;
	396
	397	if (r->reg == -1)
	398	break;
	399
	400	bank = (r->reg & 0x400) ? gpr_b : gpr_a;
	401	inc = (r->reg & 0x80) ? 128 : per_ctx_regs;
	402
	403	j = r->reg & 0x7f;
	404	while (j < 128) {
	405	bank[j] = r->value;
	406	j += inc;
	407	}
	408	}
	409
	410	generate_ucode(ucode, gpr_a, gpr_b);
	411	ixp2000_uengine_load_microcode(uengine, ucode, 513);
	412	ixp2000_uengine_init_context(uengine, 0, 0);
	413	ixp2000_uengine_start_contexts(uengine, 0x01);
	414	for (i = 0; i < 100; i++) {
	415	u32 status;
	416
	417	status = ixp2000_uengine_csr_read(uengine, ACTIVE_CTX_STS);
	418	if (!(status & 0x80000000))
	419	break;
	420	}
	421	ixp2000_uengine_stop_contexts(uengine, 0x01);
	422
	423	kfree(ucode);
	424	kfree(gpr_b);
	425	kfree(gpr_a);
	426
	427	return !!(i == 100);
	428	}
	429
	430	int ixp2000_uengine_load(int uengine, struct ixp2000_uengine_code *c)
	431	{
	432	int ctx;
	433
	434	if (!check_ixp_type(c))
	435	return 1;
	436
	437	if (!(ixp2000_uengine_mask & (1 << uengine)))
	438	return 1;
	439
	440	ixp2000_uengine_reset(1 << uengine);
	441	ixp2000_uengine_set_mode(uengine, c->uengine_parameters);
	442	if (set_initial_registers(uengine, c))
	443	return 1;
	444	ixp2000_uengine_load_microcode(uengine, c->insns, c->num_insns);
	445
	446	for (ctx = 0; ctx < 8; ctx++)
	447	ixp2000_uengine_init_context(uengine, ctx, 0);
	448
	449	return 0;
	450	}
	451	EXPORT_SYMBOL(ixp2000_uengine_load);
	452
	453
	454	static int __init ixp2000_uengine_init(void)
455	{
456	int uengine;
457	u32 value;
458
459	/*
460	* Determine number of microengines present.
461	*/
8b76a68c LB	462	switch ((ixp2000_reg_read(IXP_PRODUCT_ID) >> 8) & 0x1fff) {
8b76a68c LB	463	#ifdef CONFIG_ARCH_IXP2000
d01e8897 LB	464	case 0: /* IXP2800 */
	465	case 1: /* IXP2850 */
	466	ixp2000_uengine_mask = 0x00ff00ff;
	467	break;
	468
	469	case 2: /* IXP2400 */
	470	ixp2000_uengine_mask = 0x000f000f;
	471	break;
8b76a68c LB	472	#endif
	473
	474	#ifdef CONFIG_ARCH_IXP23XX
	475	case 4: /* IXP23xx */
	476	ixp2000_uengine_mask = (*IXP23XX_EXP_CFG_FUSE >> 8) & 0xf;
	477	break;
	478	#endif
d01e8897 LB	479
	480	default:
	481	printk(KERN_INFO "Detected unknown IXP2000 model (%.8x)\n",
8b76a68c	482	(unsigned int)ixp2000_reg_read(IXP_PRODUCT_ID));
d01e8897 LB	483	ixp2000_uengine_mask = 0x00000000;
	484	break;
	485	}
	486
	487	/*
	488	* Reset microengines.
	489	*/
7240f1f1	490	ixp2000_uengine_reset(ixp2000_uengine_mask);
d01e8897 LB	491
	492	/*
	493	* Synchronise timestamp counters across all microengines.
	494	*/
8b76a68c LB	495	value = ixp2000_reg_read(IXP_MISC_CONTROL);
8b76a68c LB	496	ixp2000_reg_wrb(IXP_MISC_CONTROL, value & ~0x80);
d01e8897 LB	497	for (uengine = 0; uengine < 32; uengine++) {
	498	if (ixp2000_uengine_mask & (1 << uengine)) {
	499	ixp2000_uengine_csr_write(uengine, TIMESTAMP_LOW, 0);
	500	ixp2000_uengine_csr_write(uengine, TIMESTAMP_HIGH, 0);
	501	}
	502	}
8b76a68c	503	ixp2000_reg_wrb(IXP_MISC_CONTROL, value \| 0x80);
d01e8897 LB	504
	505	return 0;
	506	}
	507
	508	subsys_initcall(ixp2000_uengine_init);