[deliverable/linux.git] / arch / arm / common / vic.c

/*
 *  linux/arch/arm/common/vic.c
 *
 *  Copyright (C) 1999 - 2003 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 */

#include <linux/export.h>
#include <linux/init.h>
#include <linux/list.h>
#include <linux/io.h>
#include <linux/irqdomain.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/syscore_ops.h>
#include <linux/device.h>
#include <linux/amba/bus.h>

#include <asm/mach/irq.h>
#include <asm/hardware/vic.h>

/**
 * struct vic_device - VIC PM device
 * @irq: The IRQ number for the base of the VIC.
 * @base: The register base for the VIC.
 * @resume_sources: A bitmask of interrupts for resume.
 * @resume_irqs: The IRQs enabled for resume.
 * @int_select: Save for VIC_INT_SELECT.
 * @int_enable: Save for VIC_INT_ENABLE.
 * @soft_int: Save for VIC_INT_SOFT.
 * @protect: Save for VIC_PROTECT.
 * @domain: The IRQ domain for the VIC.
 */
struct vic_device {
	void __iomem	*base;
	int		irq;
	u32		resume_sources;
	u32		resume_irqs;
	u32		int_select;
	u32		int_enable;
	u32		soft_int;
	u32		protect;
	struct irq_domain domain;
};

/* we cannot allocate memory when VICs are initially registered */
static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];

static int vic_id;

/**
 * vic_init2 - common initialisation code
 * @base: Base of the VIC.
 *
 * Common initialisation code for registration
 * and resume.
*/
static void vic_init2(void __iomem *base)
{
	int i;

	for (i = 0; i < 16; i++) {
		void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
		writel(VIC_VECT_CNTL_ENABLE | i, reg);
	}

	writel(32, base + VIC_PL190_DEF_VECT_ADDR);
}

#ifdef CONFIG_PM
static void resume_one_vic(struct vic_device *vic)
{
	void __iomem *base = vic->base;

	printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);

	/* re-initialise static settings */
	vic_init2(base);

	writel(vic->int_select, base + VIC_INT_SELECT);
	writel(vic->protect, base + VIC_PROTECT);

	/* set the enabled ints and then clear the non-enabled */
	writel(vic->int_enable, base + VIC_INT_ENABLE);
	writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);

	/* and the same for the soft-int register */

	writel(vic->soft_int, base + VIC_INT_SOFT);
	writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
}

static void vic_resume(void)
{
	int id;

	for (id = vic_id - 1; id >= 0; id--)
		resume_one_vic(vic_devices + id);
}

static void suspend_one_vic(struct vic_device *vic)
{
	void __iomem *base = vic->base;

	printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);

	vic->int_select = readl(base + VIC_INT_SELECT);
	vic->int_enable = readl(base + VIC_INT_ENABLE);
	vic->soft_int = readl(base + VIC_INT_SOFT);
	vic->protect = readl(base + VIC_PROTECT);

	/* set the interrupts (if any) that are used for
	 * resuming the system */

	writel(vic->resume_irqs, base + VIC_INT_ENABLE);
	writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
}

static int vic_suspend(void)
{
	int id;

	for (id = 0; id < vic_id; id++)
		suspend_one_vic(vic_devices + id);

	return 0;
}

struct syscore_ops vic_syscore_ops = {
	.suspend	= vic_suspend,
	.resume		= vic_resume,
};

/**
 * vic_pm_init - initicall to register VIC pm
 *
 * This is called via late_initcall() to register
 * the resources for the VICs due to the early
 * nature of the VIC's registration.
*/
static int __init vic_pm_init(void)
{
	if (vic_id > 0)
		register_syscore_ops(&vic_syscore_ops);

	return 0;
}
late_initcall(vic_pm_init);
#endif /* CONFIG_PM */

/**
 * vic_register() - Register a VIC.
 * @base: The base address of the VIC.
 * @irq: The base IRQ for the VIC.
 * @resume_sources: bitmask of interrupts allowed for resume sources.
 * @node: The device tree node associated with the VIC.
 *
 * Register the VIC with the system device tree so that it can be notified
 * of suspend and resume requests and ensure that the correct actions are
 * taken to re-instate the settings on resume.
 *
 * This also configures the IRQ domain for the VIC.
 */
static void __init vic_register(void __iomem *base, unsigned int irq,
				u32 resume_sources, struct device_node *node)
{
	struct vic_device *v;

	if (vic_id >= ARRAY_SIZE(vic_devices)) {
		printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
		return;
	}

	v = &vic_devices[vic_id];
	v->base = base;
	v->resume_sources = resume_sources;
	v->irq = irq;
	vic_id++;

	v->domain.irq_base = irq;
	v->domain.nr_irq = 32;
#ifdef CONFIG_OF_IRQ
	v->domain.of_node = of_node_get(node);
	v->domain.ops = &irq_domain_simple_ops;
#endif /* CONFIG_OF */
	irq_domain_add(&v->domain);
}

static void vic_ack_irq(struct irq_data *d)
{
	void __iomem *base = irq_data_get_irq_chip_data(d);
	unsigned int irq = d->hwirq;
	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
	/* moreover, clear the soft-triggered, in case it was the reason */
	writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
}

static void vic_mask_irq(struct irq_data *d)
{
	void __iomem *base = irq_data_get_irq_chip_data(d);
	unsigned int irq = d->hwirq;
	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
}

static void vic_unmask_irq(struct irq_data *d)
{
	void __iomem *base = irq_data_get_irq_chip_data(d);
	unsigned int irq = d->hwirq;
	writel(1 << irq, base + VIC_INT_ENABLE);
}

#if defined(CONFIG_PM)
static struct vic_device *vic_from_irq(unsigned int irq)
{
        struct vic_device *v = vic_devices;
	unsigned int base_irq = irq & ~31;
	int id;

	for (id = 0; id < vic_id; id++, v++) {
		if (v->irq == base_irq)
			return v;
	}

	return NULL;
}

static int vic_set_wake(struct irq_data *d, unsigned int on)
{
	struct vic_device *v = vic_from_irq(d->irq);
	unsigned int off = d->hwirq;
	u32 bit = 1 << off;

	if (!v)
		return -EINVAL;

	if (!(bit & v->resume_sources))
		return -EINVAL;

	if (on)
		v->resume_irqs |= bit;
	else
		v->resume_irqs &= ~bit;

	return 0;
}
#else
#define vic_set_wake NULL
#endif /* CONFIG_PM */

static struct irq_chip vic_chip = {
	.name		= "VIC",
	.irq_ack	= vic_ack_irq,
	.irq_mask	= vic_mask_irq,
	.irq_unmask	= vic_unmask_irq,
	.irq_set_wake	= vic_set_wake,
};

static void __init vic_disable(void __iomem *base)
{
	writel(0, base + VIC_INT_SELECT);
	writel(0, base + VIC_INT_ENABLE);
	writel(~0, base + VIC_INT_ENABLE_CLEAR);
	writel(0, base + VIC_ITCR);
	writel(~0, base + VIC_INT_SOFT_CLEAR);
}

static void __init vic_clear_interrupts(void __iomem *base)
{
	unsigned int i;

	writel(0, base + VIC_PL190_VECT_ADDR);
	for (i = 0; i < 19; i++) {
		unsigned int value;

		value = readl(base + VIC_PL190_VECT_ADDR);
		writel(value, base + VIC_PL190_VECT_ADDR);
	}
}

static void __init vic_set_irq_sources(void __iomem *base,
				unsigned int irq_start, u32 vic_sources)
{
	unsigned int i;

	for (i = 0; i < 32; i++) {
		if (vic_sources & (1 << i)) {
			unsigned int irq = irq_start + i;

			irq_set_chip_and_handler(irq, &vic_chip,
						 handle_level_irq);
			irq_set_chip_data(irq, base);
			set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
		}
	}
}

/*
 * The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
 * The original cell has 32 interrupts, while the modified one has 64,
 * replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
 * the probe function is called twice, with base set to offset 000
 *  and 020 within the page. We call this "second block".
 */
static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
				u32 vic_sources)
{
	unsigned int i;
	int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;

	/* Disable all interrupts initially. */
	vic_disable(base);

	/*
	 * Make sure we clear all existing interrupts. The vector registers
	 * in this cell are after the second block of general registers,
	 * so we can address them using standard offsets, but only from
	 * the second base address, which is 0x20 in the page
	 */
	if (vic_2nd_block) {
		vic_clear_interrupts(base);

		/* ST has 16 vectors as well, but we don't enable them by now */
		for (i = 0; i < 16; i++) {
			void __iomem *reg = base + VIC_VECT_CNTL0 + (i * 4);
			writel(0, reg);
		}

		writel(32, base + VIC_PL190_DEF_VECT_ADDR);
	}

	vic_set_irq_sources(base, irq_start, vic_sources);
}

static void __init __vic_init(void __iomem *base, unsigned int irq_start,
			      u32 vic_sources, u32 resume_sources,
			      struct device_node *node)
{
	unsigned int i;
	u32 cellid = 0;
	enum amba_vendor vendor;

	/* Identify which VIC cell this one is, by reading the ID */
	for (i = 0; i < 4; i++) {
		void __iomem *addr;
		addr = (void __iomem *)((u32)base & PAGE_MASK) + 0xfe0 + (i * 4);
		cellid |= (readl(addr) & 0xff) << (8 * i);
	}
	vendor = (cellid >> 12) & 0xff;
	printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
	       base, cellid, vendor);

	switch(vendor) {
	case AMBA_VENDOR_ST:
		vic_init_st(base, irq_start, vic_sources);
		return;
	default:
		printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
		/* fall through */
	case AMBA_VENDOR_ARM:
		break;
	}

	/* Disable all interrupts initially. */
	vic_disable(base);

	/* Make sure we clear all existing interrupts */
	vic_clear_interrupts(base);

	vic_init2(base);

	vic_set_irq_sources(base, irq_start, vic_sources);

	vic_register(base, irq_start, resume_sources, node);
}

/**
 * vic_init() - initialise a vectored interrupt controller
 * @base: iomem base address
 * @irq_start: starting interrupt number, must be muliple of 32
 * @vic_sources: bitmask of interrupt sources to allow
 * @resume_sources: bitmask of interrupt sources to allow for resume
 */
void __init vic_init(void __iomem *base, unsigned int irq_start,
		     u32 vic_sources, u32 resume_sources)
{
	__vic_init(base, irq_start, vic_sources, resume_sources, NULL);
}

#ifdef CONFIG_OF
int __init vic_of_init(struct device_node *node, struct device_node *parent)
{
	void __iomem *regs;
	int irq_base;

	if (WARN(parent, "non-root VICs are not supported"))
		return -EINVAL;

	regs = of_iomap(node, 0);
	if (WARN_ON(!regs))
		return -EIO;

	irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
	if (WARN_ON(irq_base < 0))
		goto out_unmap;

	__vic_init(regs, irq_base, ~0, ~0, node);

	return 0;

 out_unmap:
	iounmap(regs);

	return -EIO;
}
#endif /* CONFIG OF */
Commit	Line	Data
fa0fe48f RK	1	/*
	2	* linux/arch/arm/common/vic.c
	3	*
	4	* Copyright (C) 1999 - 2003 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License as published by
	9	* the Free Software Foundation; either version 2 of the License, or
	10	* (at your option) any later version.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*
	17	* You should have received a copy of the GNU General Public License
	18	* along with this program; if not, write to the Free Software
	19	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	20	*/
bb06b737	21
f9b28ccb	22	#include <linux/export.h>
fa0fe48f RK	23	#include <linux/init.h>
fa0fe48f RK	24	#include <linux/list.h>
fced80c7	25	#include <linux/io.h>
f9b28ccb JI	26	#include <linux/irqdomain.h>
	27	#include <linux/of.h>
	28	#include <linux/of_address.h>
	29	#include <linux/of_irq.h>
328f5cc3	30	#include <linux/syscore_ops.h>
59fcf48f	31	#include <linux/device.h>
f17a1f06	32	#include <linux/amba/bus.h>
fa0fe48f	33
fa0fe48f RK	34	#include <asm/mach/irq.h>
	35	#include <asm/hardware/vic.h>
	36
c07f87f2 BD	37	/**
c07f87f2 BD	38	* struct vic_device - VIC PM device
c07f87f2 BD	39	* @irq: The IRQ number for the base of the VIC.
	40	* @base: The register base for the VIC.
	41	* @resume_sources: A bitmask of interrupts for resume.
	42	* @resume_irqs: The IRQs enabled for resume.
	43	* @int_select: Save for VIC_INT_SELECT.
	44	* @int_enable: Save for VIC_INT_ENABLE.
	45	* @soft_int: Save for VIC_INT_SOFT.
	46	* @protect: Save for VIC_PROTECT.
f9b28ccb	47	* @domain: The IRQ domain for the VIC.
c07f87f2 BD	48	*/
c07f87f2 BD	49	struct vic_device {
c07f87f2 BD	50	void __iomem *base;
	51	int irq;
	52	u32 resume_sources;
	53	u32 resume_irqs;
	54	u32 int_select;
	55	u32 int_enable;
	56	u32 soft_int;
	57	u32 protect;
f9b28ccb	58	struct irq_domain domain;
c07f87f2 BD	59	};
	60
	61	/* we cannot allocate memory when VICs are initially registered */
	62	static struct vic_device vic_devices[CONFIG_ARM_VIC_NR];
	63
bb06b737	64	static int vic_id;
c07f87f2	65
bb06b737 HS	66	/**
	67	* vic_init2 - common initialisation code
	68	* @base: Base of the VIC.
	69	*
b595076a	70	* Common initialisation code for registration
bb06b737 HS	71	* and resume.
	72	*/
	73	static void vic_init2(void __iomem *base)
	74	{
	75	int i;
	76
	77	for (i = 0; i < 16; i++) {
	78	void __iomem reg = base + VIC_VECT_CNTL0 + (i 4);
	79	writel(VIC_VECT_CNTL_ENABLE \| i, reg);
	80	}
	81
	82	writel(32, base + VIC_PL190_DEF_VECT_ADDR);
	83	}
c07f87f2	84
328f5cc3 RW	85	#ifdef CONFIG_PM
328f5cc3 RW	86	static void resume_one_vic(struct vic_device *vic)
c07f87f2	87	{
c07f87f2 BD	88	void __iomem *base = vic->base;
	89
	90	printk(KERN_DEBUG "%s: resuming vic at %p\n", __func__, base);
	91
	92	/* re-initialise static settings */
	93	vic_init2(base);
	94
	95	writel(vic->int_select, base + VIC_INT_SELECT);
	96	writel(vic->protect, base + VIC_PROTECT);
	97
	98	/* set the enabled ints and then clear the non-enabled */
	99	writel(vic->int_enable, base + VIC_INT_ENABLE);
	100	writel(~vic->int_enable, base + VIC_INT_ENABLE_CLEAR);
	101
	102	/* and the same for the soft-int register */
	103
	104	writel(vic->soft_int, base + VIC_INT_SOFT);
	105	writel(~vic->soft_int, base + VIC_INT_SOFT_CLEAR);
328f5cc3	106	}
c07f87f2	107
328f5cc3 RW	108	static void vic_resume(void)
	109	{
	110	int id;
	111
	112	for (id = vic_id - 1; id >= 0; id--)
	113	resume_one_vic(vic_devices + id);
c07f87f2 BD	114	}
c07f87f2 BD	115
328f5cc3	116	static void suspend_one_vic(struct vic_device *vic)
c07f87f2	117	{
c07f87f2 BD	118	void __iomem *base = vic->base;
	119
	120	printk(KERN_DEBUG "%s: suspending vic at %p\n", __func__, base);
	121
	122	vic->int_select = readl(base + VIC_INT_SELECT);
	123	vic->int_enable = readl(base + VIC_INT_ENABLE);
	124	vic->soft_int = readl(base + VIC_INT_SOFT);
	125	vic->protect = readl(base + VIC_PROTECT);
	126
	127	/* set the interrupts (if any) that are used for
	128	* resuming the system */
	129
	130	writel(vic->resume_irqs, base + VIC_INT_ENABLE);
	131	writel(~vic->resume_irqs, base + VIC_INT_ENABLE_CLEAR);
328f5cc3 RW	132	}
	133
	134	static int vic_suspend(void)
	135	{
	136	int id;
	137
	138	for (id = 0; id < vic_id; id++)
	139	suspend_one_vic(vic_devices + id);
c07f87f2 BD	140
	141	return 0;
	142	}
	143
328f5cc3 RW	144	struct syscore_ops vic_syscore_ops = {
	145	.suspend = vic_suspend,
	146	.resume = vic_resume,
c07f87f2 BD	147	};
c07f87f2 BD	148
c07f87f2 BD	149	/**
	150	* vic_pm_init - initicall to register VIC pm
	151	*
	152	* This is called via late_initcall() to register
	153	* the resources for the VICs due to the early
	154	* nature of the VIC's registration.
	155	*/
	156	static int __init vic_pm_init(void)
	157	{
328f5cc3 RW	158	if (vic_id > 0)
328f5cc3 RW	159	register_syscore_ops(&vic_syscore_ops);
c07f87f2 BD	160
	161	return 0;
	162	}
c07f87f2	163	late_initcall(vic_pm_init);
f9b28ccb	164	#endif /* CONFIG_PM */
c07f87f2	165
bb06b737	166	/**
f9b28ccb	167	* vic_register() - Register a VIC.
bb06b737 HS	168	* @base: The base address of the VIC.
	169	* @irq: The base IRQ for the VIC.
	170	* @resume_sources: bitmask of interrupts allowed for resume sources.
f9b28ccb	171	* @node: The device tree node associated with the VIC.
bb06b737 HS	172	*
	173	* Register the VIC with the system device tree so that it can be notified
	174	* of suspend and resume requests and ensure that the correct actions are
	175	* taken to re-instate the settings on resume.
f9b28ccb JI	176	*
f9b28ccb JI	177	* This also configures the IRQ domain for the VIC.
bb06b737	178	*/
f9b28ccb JI	179	static void __init vic_register(void __iomem *base, unsigned int irq,
f9b28ccb JI	180	u32 resume_sources, struct device_node *node)
bb06b737 HS	181	{
	182	struct vic_device *v;
	183
f9b28ccb	184	if (vic_id >= ARRAY_SIZE(vic_devices)) {
bb06b737	185	printk(KERN_ERR "%s: too few VICs, increase CONFIG_ARM_VIC_NR\n", __func__);
f9b28ccb	186	return;
bb06b737	187	}
f9b28ccb JI	188
	189	v = &vic_devices[vic_id];
	190	v->base = base;
	191	v->resume_sources = resume_sources;
	192	v->irq = irq;
	193	vic_id++;
	194
	195	v->domain.irq_base = irq;
	196	v->domain.nr_irq = 32;
	197	#ifdef CONFIG_OF_IRQ
	198	v->domain.of_node = of_node_get(node);
	199	v->domain.ops = &irq_domain_simple_ops;
	200	#endif /* CONFIG_OF */
	201	irq_domain_add(&v->domain);
bb06b737	202	}
bb06b737	203
f013c98d	204	static void vic_ack_irq(struct irq_data *d)
bb06b737	205	{
f013c98d	206	void __iomem *base = irq_data_get_irq_chip_data(d);
f9b28ccb	207	unsigned int irq = d->hwirq;
bb06b737 HS	208	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
	209	/* moreover, clear the soft-triggered, in case it was the reason */
	210	writel(1 << irq, base + VIC_INT_SOFT_CLEAR);
	211	}
	212
f013c98d	213	static void vic_mask_irq(struct irq_data *d)
bb06b737	214	{
f013c98d	215	void __iomem *base = irq_data_get_irq_chip_data(d);
f9b28ccb	216	unsigned int irq = d->hwirq;
bb06b737 HS	217	writel(1 << irq, base + VIC_INT_ENABLE_CLEAR);
	218	}
	219
f013c98d	220	static void vic_unmask_irq(struct irq_data *d)
bb06b737	221	{
f013c98d	222	void __iomem *base = irq_data_get_irq_chip_data(d);
f9b28ccb	223	unsigned int irq = d->hwirq;
bb06b737 HS	224	writel(1 << irq, base + VIC_INT_ENABLE);
	225	}
	226
	227	#if defined(CONFIG_PM)
c07f87f2 BD	228	static struct vic_device *vic_from_irq(unsigned int irq)
	229	{
	230	struct vic_device *v = vic_devices;
	231	unsigned int base_irq = irq & ~31;
	232	int id;
	233
	234	for (id = 0; id < vic_id; id++, v++) {
	235	if (v->irq == base_irq)
	236	return v;
	237	}
	238
	239	return NULL;
	240	}
	241
f013c98d	242	static int vic_set_wake(struct irq_data *d, unsigned int on)
c07f87f2	243	{
f013c98d	244	struct vic_device *v = vic_from_irq(d->irq);
f9b28ccb	245	unsigned int off = d->hwirq;
3f1a567d	246	u32 bit = 1 << off;
c07f87f2 BD	247
	248	if (!v)
	249	return -EINVAL;
	250
3f1a567d BD	251	if (!(bit & v->resume_sources))
	252	return -EINVAL;
	253
c07f87f2	254	if (on)
3f1a567d	255	v->resume_irqs \|= bit;
c07f87f2	256	else
3f1a567d	257	v->resume_irqs &= ~bit;
c07f87f2 BD	258
	259	return 0;
	260	}
c07f87f2	261	#else
c07f87f2 BD	262	#define vic_set_wake NULL
	263	#endif /* CONFIG_PM */
	264
38c677cb	265	static struct irq_chip vic_chip = {
b0c4c898	266	.name = "VIC",
f013c98d LB	267	.irq_ack = vic_ack_irq,
	268	.irq_mask = vic_mask_irq,
	269	.irq_unmask = vic_unmask_irq,
	270	.irq_set_wake = vic_set_wake,
fa0fe48f RK	271	};
fa0fe48f RK	272
b0c4c898 HS	273	static void __init vic_disable(void __iomem *base)
	274	{
	275	writel(0, base + VIC_INT_SELECT);
	276	writel(0, base + VIC_INT_ENABLE);
	277	writel(~0, base + VIC_INT_ENABLE_CLEAR);
b0c4c898 HS	278	writel(0, base + VIC_ITCR);
	279	writel(~0, base + VIC_INT_SOFT_CLEAR);
	280	}
	281
	282	static void __init vic_clear_interrupts(void __iomem *base)
	283	{
	284	unsigned int i;
	285
	286	writel(0, base + VIC_PL190_VECT_ADDR);
	287	for (i = 0; i < 19; i++) {
	288	unsigned int value;
	289
	290	value = readl(base + VIC_PL190_VECT_ADDR);
	291	writel(value, base + VIC_PL190_VECT_ADDR);
	292	}
	293	}
	294
	295	static void __init vic_set_irq_sources(void __iomem *base,
	296	unsigned int irq_start, u32 vic_sources)
	297	{
	298	unsigned int i;
	299
	300	for (i = 0; i < 32; i++) {
	301	if (vic_sources & (1 << i)) {
	302	unsigned int irq = irq_start + i;
	303
f38c02f3 TG	304	irq_set_chip_and_handler(irq, &vic_chip,
f38c02f3 TG	305	handle_level_irq);
9323f261	306	irq_set_chip_data(irq, base);
b0c4c898 HS	307	set_irq_flags(irq, IRQF_VALID \| IRQF_PROBE);
	308	}
	309	}
	310	}
	311
bb06b737 HS	312	/*
	313	* The PL190 cell from ARM has been modified by ST to handle 64 interrupts.
	314	* The original cell has 32 interrupts, while the modified one has 64,
	315	* replocating two blocks 0x00..0x1f in 0x20..0x3f. In that case
	316	* the probe function is called twice, with base set to offset 000
	317	* and 020 within the page. We call this "second block".
	318	*/
	319	static void __init vic_init_st(void __iomem *base, unsigned int irq_start,
	320	u32 vic_sources)
	321	{
	322	unsigned int i;
	323	int vic_2nd_block = ((unsigned long)base & ~PAGE_MASK) != 0;
	324
	325	/* Disable all interrupts initially. */
b0c4c898	326	vic_disable(base);
bb06b737 HS	327
	328	/*
	329	* Make sure we clear all existing interrupts. The vector registers
	330	* in this cell are after the second block of general registers,
	331	* so we can address them using standard offsets, but only from
	332	* the second base address, which is 0x20 in the page
	333	*/
	334	if (vic_2nd_block) {
b0c4c898	335	vic_clear_interrupts(base);
bb06b737	336
bb06b737 HS	337	/* ST has 16 vectors as well, but we don't enable them by now */
	338	for (i = 0; i < 16; i++) {
	339	void __iomem reg = base + VIC_VECT_CNTL0 + (i 4);
	340	writel(0, reg);
	341	}
	342
	343	writel(32, base + VIC_PL190_DEF_VECT_ADDR);
	344	}
	345
b0c4c898	346	vic_set_irq_sources(base, irq_start, vic_sources);
bb06b737	347	}
87e8824b	348
f9b28ccb JI	349	static void __init __vic_init(void __iomem *base, unsigned int irq_start,
	350	u32 vic_sources, u32 resume_sources,
	351	struct device_node *node)
fa0fe48f RK	352	{
fa0fe48f RK	353	unsigned int i;
87e8824b	354	u32 cellid = 0;
f17a1f06	355	enum amba_vendor vendor;
87e8824b AR	356
	357	/* Identify which VIC cell this one is, by reading the ID */
	358	for (i = 0; i < 4; i++) {
d4f3add2 AB	359	void __iomem *addr;
d4f3add2 AB	360	addr = (void __iomem )((u32)base & PAGE_MASK) + 0xfe0 + (i 4);
87e8824b AR	361	cellid \|= (readl(addr) & 0xff) << (8 * i);
	362	}
	363	vendor = (cellid >> 12) & 0xff;
	364	printk(KERN_INFO "VIC @%p: id 0x%08x, vendor 0x%02x\n",
	365	base, cellid, vendor);
	366
	367	switch(vendor) {
f17a1f06	368	case AMBA_VENDOR_ST:
bb06b737	369	vic_init_st(base, irq_start, vic_sources);
87e8824b AR	370	return;
	371	default:
	372	printk(KERN_WARNING "VIC: unknown vendor, continuing anyways\n");
	373	/* fall through */
f17a1f06	374	case AMBA_VENDOR_ARM:
87e8824b AR	375	break;
87e8824b AR	376	}
fa0fe48f	377
fa0fe48f	378	/* Disable all interrupts initially. */
b0c4c898	379	vic_disable(base);
fa0fe48f	380
b0c4c898 HS	381	/* Make sure we clear all existing interrupts */
b0c4c898 HS	382	vic_clear_interrupts(base);
fa0fe48f	383
c07f87f2	384	vic_init2(base);
fa0fe48f	385
b0c4c898	386	vic_set_irq_sources(base, irq_start, vic_sources);
c07f87f2	387
f9b28ccb JI	388	vic_register(base, irq_start, resume_sources, node);
	389	}
	390
	391	/**
	392	* vic_init() - initialise a vectored interrupt controller
	393	* @base: iomem base address
	394	* @irq_start: starting interrupt number, must be muliple of 32
	395	* @vic_sources: bitmask of interrupt sources to allow
	396	* @resume_sources: bitmask of interrupt sources to allow for resume
	397	*/
	398	void __init vic_init(void __iomem *base, unsigned int irq_start,
	399	u32 vic_sources, u32 resume_sources)
	400	{
	401	__vic_init(base, irq_start, vic_sources, resume_sources, NULL);
	402	}
	403
	404	#ifdef CONFIG_OF
	405	int __init vic_of_init(struct device_node node, struct device_node parent)
	406	{
	407	void __iomem *regs;
	408	int irq_base;
	409
	410	if (WARN(parent, "non-root VICs are not supported"))
	411	return -EINVAL;
	412
	413	regs = of_iomap(node, 0);
	414	if (WARN_ON(!regs))
	415	return -EIO;
	416
	417	irq_base = irq_alloc_descs(-1, 0, 32, numa_node_id());
	418	if (WARN_ON(irq_base < 0))
	419	goto out_unmap;
	420
	421	__vic_init(regs, irq_base, ~0, ~0, node);
	422
	423	return 0;
	424
	425	out_unmap:
	426	iounmap(regs);
	427
	428	return -EIO;
fa0fe48f	429	}
f9b28ccb	430	#endif /* CONFIG OF */