[deliverable/linux.git] / arch / arm / include / asm / assembler.h

/*
 *  arch/arm/include/asm/assembler.h
 *
 *  Copyright (C) 1996-2000 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  This file contains arm architecture specific defines
 *  for the different processors.
 *
 *  Do not include any C declarations in this file - it is included by
 *  assembler source.
 */
#ifndef __ASM_ASSEMBLER_H__
#define __ASM_ASSEMBLER_H__

#ifndef __ASSEMBLY__
#error "Only include this from assembly code"
#endif

#include <asm/ptrace.h>
#include <asm/domain.h>
#include <asm/opcodes-virt.h>
#include <asm/asm-offsets.h>
#include <asm/page.h>
#include <asm/thread_info.h>

#define IOMEM(x)	(x)

/*
 * Endian independent macros for shifting bytes within registers.
 */
#ifndef __ARMEB__
#define lspull          lsr
#define lspush          lsl
#define get_byte_0      lsl #0
#define get_byte_1	lsr #8
#define get_byte_2	lsr #16
#define get_byte_3	lsr #24
#define put_byte_0      lsl #0
#define put_byte_1	lsl #8
#define put_byte_2	lsl #16
#define put_byte_3	lsl #24
#else
#define lspull          lsl
#define lspush          lsr
#define get_byte_0	lsr #24
#define get_byte_1	lsr #16
#define get_byte_2	lsr #8
#define get_byte_3      lsl #0
#define put_byte_0	lsl #24
#define put_byte_1	lsl #16
#define put_byte_2	lsl #8
#define put_byte_3      lsl #0
#endif

/* Select code for any configuration running in BE8 mode */
#ifdef CONFIG_CPU_ENDIAN_BE8
#define ARM_BE8(code...) code
#else
#define ARM_BE8(code...)
#endif

/*
 * Data preload for architectures that support it
 */
#if __LINUX_ARM_ARCH__ >= 5
#define PLD(code...)	code
#else
#define PLD(code...)
#endif

/*
 * This can be used to enable code to cacheline align the destination
 * pointer when bulk writing to memory.  Experiments on StrongARM and
 * XScale didn't show this a worthwhile thing to do when the cache is not
 * set to write-allocate (this would need further testing on XScale when WA
 * is used).
 *
 * On Feroceon there is much to gain however, regardless of cache mode.
 */
#ifdef CONFIG_CPU_FEROCEON
#define CALGN(code...) code
#else
#define CALGN(code...)
#endif

/*
 * Enable and disable interrupts
 */
#if __LINUX_ARM_ARCH__ >= 6
	.macro	disable_irq_notrace
	cpsid	i
	.endm

	.macro	enable_irq_notrace
	cpsie	i
	.endm
#else
	.macro	disable_irq_notrace
	msr	cpsr_c, #PSR_I_BIT | SVC_MODE
	.endm

	.macro	enable_irq_notrace
	msr	cpsr_c, #SVC_MODE
	.endm
#endif

	.macro asm_trace_hardirqs_off
#if defined(CONFIG_TRACE_IRQFLAGS)
	stmdb   sp!, {r0-r3, ip, lr}
	bl	trace_hardirqs_off
	ldmia	sp!, {r0-r3, ip, lr}
#endif
	.endm

	.macro asm_trace_hardirqs_on_cond, cond
#if defined(CONFIG_TRACE_IRQFLAGS)
	/*
	 * actually the registers should be pushed and pop'd conditionally, but
	 * after bl the flags are certainly clobbered
	 */
	stmdb   sp!, {r0-r3, ip, lr}
	bl\cond	trace_hardirqs_on
	ldmia	sp!, {r0-r3, ip, lr}
#endif
	.endm

	.macro asm_trace_hardirqs_on
	asm_trace_hardirqs_on_cond al
	.endm

	.macro disable_irq
	disable_irq_notrace
	asm_trace_hardirqs_off
	.endm

	.macro enable_irq
	asm_trace_hardirqs_on
	enable_irq_notrace
	.endm
/*
 * Save the current IRQ state and disable IRQs.  Note that this macro
 * assumes FIQs are enabled, and that the processor is in SVC mode.
 */
	.macro	save_and_disable_irqs, oldcpsr
#ifdef CONFIG_CPU_V7M
	mrs	\oldcpsr, primask
#else
	mrs	\oldcpsr, cpsr
#endif
	disable_irq
	.endm

	.macro	save_and_disable_irqs_notrace, oldcpsr
	mrs	\oldcpsr, cpsr
	disable_irq_notrace
	.endm

/*
 * Restore interrupt state previously stored in a register.  We don't
 * guarantee that this will preserve the flags.
 */
	.macro	restore_irqs_notrace, oldcpsr
#ifdef CONFIG_CPU_V7M
	msr	primask, \oldcpsr
#else
	msr	cpsr_c, \oldcpsr
#endif
	.endm

	.macro restore_irqs, oldcpsr
	tst	\oldcpsr, #PSR_I_BIT
	asm_trace_hardirqs_on_cond eq
	restore_irqs_notrace \oldcpsr
	.endm

/*
 * Assembly version of "adr rd, BSYM(sym)".  This should only be used to
 * reference local symbols in the same assembly file which are to be
 * resolved by the assembler.  Other usage is undefined.
 */
	.irp	c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
	.macro	badr\c, rd, sym
#ifdef CONFIG_THUMB2_KERNEL
	adr\c	\rd, \sym + 1
#else
	adr\c	\rd, \sym
#endif
	.endm
	.endr

/*
 * Get current thread_info.
 */
	.macro	get_thread_info, rd
 ARM(	mov	\rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT	)
 THUMB(	mov	\rd, sp			)
 THUMB(	lsr	\rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT	)
	mov	\rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
	.endm

/*
 * Increment/decrement the preempt count.
 */
#ifdef CONFIG_PREEMPT_COUNT
	.macro	inc_preempt_count, ti, tmp
	ldr	\tmp, [\ti, #TI_PREEMPT]	@ get preempt count
	add	\tmp, \tmp, #1			@ increment it
	str	\tmp, [\ti, #TI_PREEMPT]
	.endm

	.macro	dec_preempt_count, ti, tmp
	ldr	\tmp, [\ti, #TI_PREEMPT]	@ get preempt count
	sub	\tmp, \tmp, #1			@ decrement it
	str	\tmp, [\ti, #TI_PREEMPT]
	.endm

	.macro	dec_preempt_count_ti, ti, tmp
	get_thread_info \ti
	dec_preempt_count \ti, \tmp
	.endm
#else
	.macro	inc_preempt_count, ti, tmp
	.endm

	.macro	dec_preempt_count, ti, tmp
	.endm

	.macro	dec_preempt_count_ti, ti, tmp
	.endm
#endif

#define USER(x...)				\
9999:	x;					\
	.pushsection __ex_table,"a";		\
	.align	3;				\
	.long	9999b,9001f;			\
	.popsection

#ifdef CONFIG_SMP
#define ALT_SMP(instr...)					\
9998:	instr
/*
 * Note: if you get assembler errors from ALT_UP() when building with
 * CONFIG_THUMB2_KERNEL, you almost certainly need to use
 * ALT_SMP( W(instr) ... )
 */
#define ALT_UP(instr...)					\
	.pushsection ".alt.smp.init", "a"			;\
	.long	9998b						;\
9997:	instr							;\
	.if . - 9997b == 2					;\
		nop						;\
	.endif							;\
	.if . - 9997b != 4					;\
		.error "ALT_UP() content must assemble to exactly 4 bytes";\
	.endif							;\
	.popsection
#define ALT_UP_B(label)					\
	.equ	up_b_offset, label - 9998b			;\
	.pushsection ".alt.smp.init", "a"			;\
	.long	9998b						;\
	W(b)	. + up_b_offset					;\
	.popsection
#else
#define ALT_SMP(instr...)
#define ALT_UP(instr...) instr
#define ALT_UP_B(label) b label
#endif

/*
 * Instruction barrier
 */
	.macro	instr_sync
#if __LINUX_ARM_ARCH__ >= 7
	isb
#elif __LINUX_ARM_ARCH__ == 6
	mcr	p15, 0, r0, c7, c5, 4
#endif
	.endm

/*
 * SMP data memory barrier
 */
	.macro	smp_dmb mode
#ifdef CONFIG_SMP
#if __LINUX_ARM_ARCH__ >= 7
	.ifeqs "\mode","arm"
	ALT_SMP(dmb	ish)
	.else
	ALT_SMP(W(dmb)	ish)
	.endif
#elif __LINUX_ARM_ARCH__ == 6
	ALT_SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb
#else
#error Incompatible SMP platform
#endif
	.ifeqs "\mode","arm"
	ALT_UP(nop)
	.else
	ALT_UP(W(nop))
	.endif
#endif
	.endm

#if defined(CONFIG_CPU_V7M)
	/*
	 * setmode is used to assert to be in svc mode during boot. For v7-M
	 * this is done in __v7m_setup, so setmode can be empty here.
	 */
	.macro	setmode, mode, reg
	.endm
#elif defined(CONFIG_THUMB2_KERNEL)
	.macro	setmode, mode, reg
	mov	\reg, #\mode
	msr	cpsr_c, \reg
	.endm
#else
	.macro	setmode, mode, reg
	msr	cpsr_c, #\mode
	.endm
#endif

/*
 * Helper macro to enter SVC mode cleanly and mask interrupts. reg is
 * a scratch register for the macro to overwrite.
 *
 * This macro is intended for forcing the CPU into SVC mode at boot time.
 * you cannot return to the original mode.
 */
.macro safe_svcmode_maskall reg:req
#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
	mrs	\reg , cpsr
	eor	\reg, \reg, #HYP_MODE
	tst	\reg, #MODE_MASK
	bic	\reg , \reg , #MODE_MASK
	orr	\reg , \reg , #PSR_I_BIT | PSR_F_BIT | SVC_MODE
THUMB(	orr	\reg , \reg , #PSR_T_BIT	)
	bne	1f
	orr	\reg, \reg, #PSR_A_BIT
	badr	lr, 2f
	msr	spsr_cxsf, \reg
	__MSR_ELR_HYP(14)
	__ERET
1:	msr	cpsr_c, \reg
2:
#else
/*
 * workaround for possibly broken pre-v6 hardware
 * (akita, Sharp Zaurus C-1000, PXA270-based)
 */
	setmode	PSR_F_BIT | PSR_I_BIT | SVC_MODE, \reg
#endif
.endm

/*
 * STRT/LDRT access macros with ARM and Thumb-2 variants
 */
#ifdef CONFIG_THUMB2_KERNEL

	.macro	usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
9999:
	.if	\inc == 1
	\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
	.elseif	\inc == 4
	\instr\cond\()\t\().w \reg, [\ptr, #\off]
	.else
	.error	"Unsupported inc macro argument"
	.endif

	.pushsection __ex_table,"a"
	.align	3
	.long	9999b, \abort
	.popsection
	.endm

	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort
	@ explicit IT instruction needed because of the label
	@ introduced by the USER macro
	.ifnc	\cond,al
	.if	\rept == 1
	itt	\cond
	.elseif	\rept == 2
	ittt	\cond
	.else
	.error	"Unsupported rept macro argument"
	.endif
	.endif

	@ Slightly optimised to avoid incrementing the pointer twice
	usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
	.if	\rept == 2
	usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
	.endif

	add\cond \ptr, #\rept * \inc
	.endm

#else	/* !CONFIG_THUMB2_KERNEL */

	.macro	usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
	.rept	\rept
9999:
	.if	\inc == 1
	\instr\cond\()b\()\t \reg, [\ptr], #\inc
	.elseif	\inc == 4
	\instr\cond\()\t \reg, [\ptr], #\inc
	.else
	.error	"Unsupported inc macro argument"
	.endif

	.pushsection __ex_table,"a"
	.align	3
	.long	9999b, \abort
	.popsection
	.endr
	.endm

#endif	/* CONFIG_THUMB2_KERNEL */

	.macro	strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
	usracc	str, \reg, \ptr, \inc, \cond, \rept, \abort
	.endm

	.macro	ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
	usracc	ldr, \reg, \ptr, \inc, \cond, \rept, \abort
	.endm

/* Utility macro for declaring string literals */
	.macro	string name:req, string
	.type \name , #object
\name:
	.asciz "\string"
	.size \name , . - \name
	.endm

	.macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
#ifndef CONFIG_CPU_USE_DOMAINS
	adds	\tmp, \addr, #\size - 1
	sbcccs	\tmp, \tmp, \limit
	bcs	\bad
#endif
	.endm

	.irp	c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
	.macro	ret\c, reg
#if __LINUX_ARM_ARCH__ < 6
	mov\c	pc, \reg
#else
	.ifeqs	"\reg", "lr"
	bx\c	\reg
	.else
	mov\c	pc, \reg
	.endif
#endif
	.endm
	.endr

	.macro	ret.w, reg
	ret	\reg
#ifdef CONFIG_THUMB2_KERNEL
	nop
#endif
	.endm

#endif /* __ASM_ASSEMBLER_H__ */
Commit	Line	Data
1da177e4	1	/*
4baa9922	2	* arch/arm/include/asm/assembler.h
1da177e4 LT	3	*
	4	* Copyright (C) 1996-2000 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* This file contains arm architecture specific defines
	11	* for the different processors.
	12	*
	13	* Do not include any C declarations in this file - it is included by
	14	* assembler source.
	15	*/
2bc58a6f MD	16	#ifndef __ASM_ASSEMBLER_H__
	17	#define __ASM_ASSEMBLER_H__
	18
1da177e4 LT	19	#ifndef __ASSEMBLY__
	20	#error "Only include this from assembly code"
	21	#endif
	22
	23	#include <asm/ptrace.h>
247055aa	24	#include <asm/domain.h>
80c59daf	25	#include <asm/opcodes-virt.h>
0b1f68e8	26	#include <asm/asm-offsets.h>
9a2b51b6 AR	27	#include <asm/page.h>
9a2b51b6 AR	28	#include <asm/thread_info.h>
1da177e4	29
6f6f6a70 RH	30	#define IOMEM(x) (x)
6f6f6a70 RH	31
1da177e4 LT	32	/*
	33	* Endian independent macros for shifting bytes within registers.
	34	*/
	35	#ifndef __ARMEB__
d98b90ea VK	36	#define lspull lsr
d98b90ea VK	37	#define lspush lsl
1da177e4 LT	38	#define get_byte_0 lsl #0
	39	#define get_byte_1 lsr #8
	40	#define get_byte_2 lsr #16
	41	#define get_byte_3 lsr #24
	42	#define put_byte_0 lsl #0
	43	#define put_byte_1 lsl #8
	44	#define put_byte_2 lsl #16
	45	#define put_byte_3 lsl #24
	46	#else
d98b90ea VK	47	#define lspull lsl
d98b90ea VK	48	#define lspush lsr
1da177e4 LT	49	#define get_byte_0 lsr #24
	50	#define get_byte_1 lsr #16
	51	#define get_byte_2 lsr #8
	52	#define get_byte_3 lsl #0
	53	#define put_byte_0 lsl #24
	54	#define put_byte_1 lsl #16
	55	#define put_byte_2 lsl #8
	56	#define put_byte_3 lsl #0
	57	#endif
	58
457c2403 BD	59	/* Select code for any configuration running in BE8 mode */
	60	#ifdef CONFIG_CPU_ENDIAN_BE8
	61	#define ARM_BE8(code...) code
	62	#else
	63	#define ARM_BE8(code...)
	64	#endif
	65
1da177e4 LT	66	/*
	67	* Data preload for architectures that support it
	68	*/
	69	#if __LINUX_ARM_ARCH__ >= 5
	70	#define PLD(code...) code
	71	#else
	72	#define PLD(code...)
	73	#endif
	74
2239aff6 NP	75	/*
	76	* This can be used to enable code to cacheline align the destination
	77	* pointer when bulk writing to memory. Experiments on StrongARM and
	78	* XScale didn't show this a worthwhile thing to do when the cache is not
	79	* set to write-allocate (this would need further testing on XScale when WA
	80	* is used).
	81	*
	82	* On Feroceon there is much to gain however, regardless of cache mode.
	83	*/
	84	#ifdef CONFIG_CPU_FEROCEON
	85	#define CALGN(code...) code
	86	#else
	87	#define CALGN(code...)
	88	#endif
	89
1da177e4	90	/*
9c42954d	91	* Enable and disable interrupts
1da177e4	92	*/
59d1ff3b	93	#if __LINUX_ARM_ARCH__ >= 6
0d928b0b	94	.macro disable_irq_notrace
59d1ff3b	95	cpsid i
9c42954d RK	96	.endm
9c42954d RK	97
0d928b0b	98	.macro enable_irq_notrace
9c42954d RK	99	cpsie i
9c42954d RK	100	.endm
59d1ff3b	101	#else
0d928b0b	102	.macro disable_irq_notrace
9c42954d RK	103	msr cpsr_c, #PSR_I_BIT \| SVC_MODE
	104	.endm
	105
0d928b0b	106	.macro enable_irq_notrace
9c42954d RK	107	msr cpsr_c, #SVC_MODE
9c42954d RK	108	.endm
59d1ff3b	109	#endif
9c42954d	110
0d928b0b UKK	111	.macro asm_trace_hardirqs_off
	112	#if defined(CONFIG_TRACE_IRQFLAGS)
	113	stmdb sp!, {r0-r3, ip, lr}
	114	bl trace_hardirqs_off
	115	ldmia sp!, {r0-r3, ip, lr}
	116	#endif
	117	.endm
	118
	119	.macro asm_trace_hardirqs_on_cond, cond
	120	#if defined(CONFIG_TRACE_IRQFLAGS)
	121	/*
	122	* actually the registers should be pushed and pop'd conditionally, but
	123	* after bl the flags are certainly clobbered
	124	*/
	125	stmdb sp!, {r0-r3, ip, lr}
	126	bl\cond trace_hardirqs_on
	127	ldmia sp!, {r0-r3, ip, lr}
	128	#endif
	129	.endm
	130
	131	.macro asm_trace_hardirqs_on
	132	asm_trace_hardirqs_on_cond al
	133	.endm
	134
	135	.macro disable_irq
	136	disable_irq_notrace
	137	asm_trace_hardirqs_off
	138	.endm
	139
	140	.macro enable_irq
	141	asm_trace_hardirqs_on
	142	enable_irq_notrace
	143	.endm
9c42954d RK	144	/*
	145	* Save the current IRQ state and disable IRQs. Note that this macro
	146	* assumes FIQs are enabled, and that the processor is in SVC mode.
	147	*/
	148	.macro save_and_disable_irqs, oldcpsr
55bdd694 CM	149	#ifdef CONFIG_CPU_V7M
	150	mrs \oldcpsr, primask
	151	#else
9c42954d	152	mrs \oldcpsr, cpsr
55bdd694	153	#endif
9c42954d	154	disable_irq
1da177e4 LT	155	.endm
1da177e4 LT	156
8e43a905 RV	157	.macro save_and_disable_irqs_notrace, oldcpsr
	158	mrs \oldcpsr, cpsr
	159	disable_irq_notrace
	160	.endm
	161
1da177e4 LT	162	/*
	163	* Restore interrupt state previously stored in a register. We don't
	164	* guarantee that this will preserve the flags.
	165	*/
0d928b0b	166	.macro restore_irqs_notrace, oldcpsr
55bdd694 CM	167	#ifdef CONFIG_CPU_V7M
	168	msr primask, \oldcpsr
	169	#else
1da177e4	170	msr cpsr_c, \oldcpsr
55bdd694	171	#endif
1da177e4 LT	172	.endm
1da177e4 LT	173
0d928b0b UKK	174	.macro restore_irqs, oldcpsr
	175	tst \oldcpsr, #PSR_I_BIT
	176	asm_trace_hardirqs_on_cond eq
	177	restore_irqs_notrace \oldcpsr
	178	.endm
	179
14327c66 RK	180	/*
	181	* Assembly version of "adr rd, BSYM(sym)". This should only be used to
	182	* reference local symbols in the same assembly file which are to be
	183	* resolved by the assembler. Other usage is undefined.
	184	*/
	185	.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
	186	.macro badr\c, rd, sym
	187	#ifdef CONFIG_THUMB2_KERNEL
	188	adr\c \rd, \sym + 1
	189	#else
	190	adr\c \rd, \sym
	191	#endif
	192	.endm
	193	.endr
	194
39ad04cc CM	195	/*
	196	* Get current thread_info.
	197	*/
	198	.macro get_thread_info, rd
9a2b51b6	199	ARM( mov \rd, sp, lsr #THREAD_SIZE_ORDER + PAGE_SHIFT )
39ad04cc	200	THUMB( mov \rd, sp )
9a2b51b6 AR	201	THUMB( lsr \rd, \rd, #THREAD_SIZE_ORDER + PAGE_SHIFT )
9a2b51b6 AR	202	mov \rd, \rd, lsl #THREAD_SIZE_ORDER + PAGE_SHIFT
39ad04cc CM	203	.endm
39ad04cc CM	204
0b1f68e8 CM	205	/*
	206	* Increment/decrement the preempt count.
	207	*/
	208	#ifdef CONFIG_PREEMPT_COUNT
	209	.macro inc_preempt_count, ti, tmp
	210	ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
	211	add \tmp, \tmp, #1 @ increment it
	212	str \tmp, [\ti, #TI_PREEMPT]
	213	.endm
	214
	215	.macro dec_preempt_count, ti, tmp
	216	ldr \tmp, [\ti, #TI_PREEMPT] @ get preempt count
	217	sub \tmp, \tmp, #1 @ decrement it
	218	str \tmp, [\ti, #TI_PREEMPT]
	219	.endm
	220
	221	.macro dec_preempt_count_ti, ti, tmp
	222	get_thread_info \ti
	223	dec_preempt_count \ti, \tmp
	224	.endm
	225	#else
	226	.macro inc_preempt_count, ti, tmp
	227	.endm
	228
	229	.macro dec_preempt_count, ti, tmp
	230	.endm
	231
	232	.macro dec_preempt_count_ti, ti, tmp
	233	.endm
	234	#endif
	235
1da177e4 LT	236	#define USER(x...) \
1da177e4 LT	237	9999: x; \
4260415f	238	.pushsection __ex_table,"a"; \
1da177e4 LT	239	.align 3; \
1da177e4 LT	240	.long 9999b,9001f; \
4260415f	241	.popsection
bac4e960	242
f00ec48f RK	243	#ifdef CONFIG_SMP
	244	#define ALT_SMP(instr...) \
	245	9998: instr
ed3768a8 DM	246	/*
	247	* Note: if you get assembler errors from ALT_UP() when building with
	248	* CONFIG_THUMB2_KERNEL, you almost certainly need to use
	249	* ALT_SMP( W(instr) ... )
	250	*/
f00ec48f RK	251	#define ALT_UP(instr...) \
	252	.pushsection ".alt.smp.init", "a" ;\
	253	.long 9998b ;\
ed3768a8	254	9997: instr ;\
89c6bc58 RK	255	.if . - 9997b == 2 ;\
	256	nop ;\
	257	.endif ;\
ed3768a8 DM	258	.if . - 9997b != 4 ;\
	259	.error "ALT_UP() content must assemble to exactly 4 bytes";\
	260	.endif ;\
f00ec48f RK	261	.popsection
	262	#define ALT_UP_B(label) \
	263	.equ up_b_offset, label - 9998b ;\
	264	.pushsection ".alt.smp.init", "a" ;\
	265	.long 9998b ;\
ed3768a8	266	W(b) . + up_b_offset ;\
f00ec48f RK	267	.popsection
	268	#else
	269	#define ALT_SMP(instr...)
	270	#define ALT_UP(instr...) instr
	271	#define ALT_UP_B(label) b label
	272	#endif
	273
d675d0bc WD	274	/*
	275	* Instruction barrier
	276	*/
	277	.macro instr_sync
	278	#if __LINUX_ARM_ARCH__ >= 7
	279	isb
	280	#elif __LINUX_ARM_ARCH__ == 6
	281	mcr p15, 0, r0, c7, c5, 4
	282	#endif
	283	.endm
	284
bac4e960 RK	285	/*
	286	* SMP data memory barrier
	287	*/
ed3768a8	288	.macro smp_dmb mode
bac4e960 RK	289	#ifdef CONFIG_SMP
bac4e960 RK	290	#if __LINUX_ARM_ARCH__ >= 7
ed3768a8	291	.ifeqs "\mode","arm"
3ea12806	292	ALT_SMP(dmb ish)
ed3768a8	293	.else
3ea12806	294	ALT_SMP(W(dmb) ish)
ed3768a8	295	.endif
bac4e960	296	#elif __LINUX_ARM_ARCH__ == 6
f00ec48f RK	297	ALT_SMP(mcr p15, 0, r0, c7, c10, 5) @ dmb
	298	#else
	299	#error Incompatible SMP platform
bac4e960	300	#endif
ed3768a8	301	.ifeqs "\mode","arm"
f00ec48f	302	ALT_UP(nop)
ed3768a8 DM	303	.else
	304	ALT_UP(W(nop))
	305	.endif
bac4e960 RK	306	#endif
bac4e960 RK	307	.endm
b86040a5	308
55bdd694 CM	309	#if defined(CONFIG_CPU_V7M)
	310	/*
	311	* setmode is used to assert to be in svc mode during boot. For v7-M
	312	* this is done in __v7m_setup, so setmode can be empty here.
	313	*/
	314	.macro setmode, mode, reg
	315	.endm
	316	#elif defined(CONFIG_THUMB2_KERNEL)
b86040a5 CM	317	.macro setmode, mode, reg
	318	mov \reg, #\mode
	319	msr cpsr_c, \reg
	320	.endm
	321	#else
	322	.macro setmode, mode, reg
	323	msr cpsr_c, #\mode
	324	.endm
	325	#endif
8b592783	326
80c59daf DM	327	/*
	328	* Helper macro to enter SVC mode cleanly and mask interrupts. reg is
	329	* a scratch register for the macro to overwrite.
	330	*
	331	* This macro is intended for forcing the CPU into SVC mode at boot time.
	332	* you cannot return to the original mode.
80c59daf DM	333	*/
80c59daf DM	334	.macro safe_svcmode_maskall reg:req
0e0779da	335	#if __LINUX_ARM_ARCH__ >= 6 && !defined(CONFIG_CPU_V7M)
80c59daf	336	mrs \reg , cpsr
8e9c24a2 RK	337	eor \reg, \reg, #HYP_MODE
8e9c24a2 RK	338	tst \reg, #MODE_MASK
80c59daf	339	bic \reg , \reg , #MODE_MASK
8e9c24a2	340	orr \reg , \reg , #PSR_I_BIT \| PSR_F_BIT \| SVC_MODE
80c59daf	341	THUMB( orr \reg , \reg , #PSR_T_BIT )
80c59daf	342	bne 1f
2a552d5e	343	orr \reg, \reg, #PSR_A_BIT
14327c66	344	badr lr, 2f
2a552d5e	345	msr spsr_cxsf, \reg
80c59daf DM	346	__MSR_ELR_HYP(14)
80c59daf DM	347	__ERET
2a552d5e	348	1: msr cpsr_c, \reg
80c59daf	349	2:
1ecec696 DM	350	#else
	351	/*
	352	* workaround for possibly broken pre-v6 hardware
	353	* (akita, Sharp Zaurus C-1000, PXA270-based)
	354	*/
	355	setmode PSR_F_BIT \| PSR_I_BIT \| SVC_MODE, \reg
	356	#endif
80c59daf DM	357	.endm
80c59daf DM	358
8b592783 CM	359	/*
	360	* STRT/LDRT access macros with ARM and Thumb-2 variants
	361	*/
	362	#ifdef CONFIG_THUMB2_KERNEL
	363
4e7682d0	364	.macro usraccoff, instr, reg, ptr, inc, off, cond, abort, t=TUSER()
8b592783 CM	365	9999:
8b592783 CM	366	.if \inc == 1
247055aa	367	\instr\cond\()b\()\t\().w \reg, [\ptr, #\off]
8b592783	368	.elseif \inc == 4
247055aa	369	\instr\cond\()\t\().w \reg, [\ptr, #\off]
8b592783 CM	370	.else
	371	.error "Unsupported inc macro argument"
	372	.endif
	373
4260415f	374	.pushsection __ex_table,"a"
8b592783 CM	375	.align 3
8b592783 CM	376	.long 9999b, \abort
4260415f	377	.popsection
8b592783 CM	378	.endm
	379
	380	.macro usracc, instr, reg, ptr, inc, cond, rept, abort
	381	@ explicit IT instruction needed because of the label
	382	@ introduced by the USER macro
	383	.ifnc \cond,al
	384	.if \rept == 1
	385	itt \cond
	386	.elseif \rept == 2
	387	ittt \cond
	388	.else
	389	.error "Unsupported rept macro argument"
	390	.endif
	391	.endif
	392
	393	@ Slightly optimised to avoid incrementing the pointer twice
	394	usraccoff \instr, \reg, \ptr, \inc, 0, \cond, \abort
	395	.if \rept == 2
1142b71d	396	usraccoff \instr, \reg, \ptr, \inc, \inc, \cond, \abort
8b592783 CM	397	.endif
	398
	399	add\cond \ptr, #\rept * \inc
	400	.endm
	401
	402	#else /* !CONFIG_THUMB2_KERNEL */
	403
4e7682d0	404	.macro usracc, instr, reg, ptr, inc, cond, rept, abort, t=TUSER()
8b592783 CM	405	.rept \rept
	406	9999:
	407	.if \inc == 1
247055aa	408	\instr\cond\()b\()\t \reg, [\ptr], #\inc
8b592783	409	.elseif \inc == 4
247055aa	410	\instr\cond\()\t \reg, [\ptr], #\inc
8b592783 CM	411	.else
	412	.error "Unsupported inc macro argument"
	413	.endif
	414
4260415f	415	.pushsection __ex_table,"a"
8b592783 CM	416	.align 3
8b592783 CM	417	.long 9999b, \abort
4260415f	418	.popsection
8b592783 CM	419	.endr
	420	.endm
	421
	422	#endif /* CONFIG_THUMB2_KERNEL */
	423
	424	.macro strusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
	425	usracc str, \reg, \ptr, \inc, \cond, \rept, \abort
	426	.endm
	427
	428	.macro ldrusr, reg, ptr, inc, cond=al, rept=1, abort=9001f
	429	usracc ldr, \reg, \ptr, \inc, \cond, \rept, \abort
	430	.endm
8f51965e DM	431
	432	/* Utility macro for declaring string literals */
	433	.macro string name:req, string
	434	.type \name , #object
	435	\name:
	436	.asciz "\string"
	437	.size \name , . - \name
	438	.endm
	439
8404663f RK	440	.macro check_uaccess, addr:req, size:req, limit:req, tmp:req, bad:req
	441	#ifndef CONFIG_CPU_USE_DOMAINS
	442	adds \tmp, \addr, #\size - 1
	443	sbcccs \tmp, \tmp, \limit
	444	bcs \bad
	445	#endif
	446	.endm
	447
6ebbf2ce RK	448	.irp c,,eq,ne,cs,cc,mi,pl,vs,vc,hi,ls,ge,lt,gt,le,hs,lo
	449	.macro ret\c, reg
	450	#if __LINUX_ARM_ARCH__ < 6
	451	mov\c pc, \reg
	452	#else
	453	.ifeqs "\reg", "lr"
	454	bx\c \reg
	455	.else
	456	mov\c pc, \reg
	457	.endif
	458	#endif
	459	.endm
	460	.endr
	461
	462	.macro ret.w, reg
	463	ret \reg
	464	#ifdef CONFIG_THUMB2_KERNEL
	465	nop
	466	#endif
	467	.endm
	468
2bc58a6f	469	#endif /* __ASM_ASSEMBLER_H__ */