[deliverable/linux.git] / arch / arm / include / asm / bitops.h

/*
 * Copyright 1995, Russell King.
 * Various bits and pieces copyrights include:
 *  Linus Torvalds (test_bit).
 * Big endian support: Copyright 2001, Nicolas Pitre
 *  reworked by rmk.
 *
 * bit 0 is the LSB of an "unsigned long" quantity.
 *
 * Please note that the code in this file should never be included
 * from user space.  Many of these are not implemented in assembler
 * since they would be too costly.  Also, they require privileged
 * instructions (which are not available from user mode) to ensure
 * that they are atomic.
 */

#ifndef __ASM_ARM_BITOPS_H
#define __ASM_ARM_BITOPS_H

#ifdef __KERNEL__

#ifndef _LINUX_BITOPS_H
#error only <linux/bitops.h> can be included directly
#endif

#include <linux/compiler.h>
#include <linux/irqflags.h>
#include <asm/barrier.h>

/*
 * These functions are the basis of our bit ops.
 *
 * First, the atomic bitops. These use native endian.
 */
static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p)
{
	unsigned long flags;
	unsigned long mask = 1UL << (bit & 31);

	p += bit >> 5;

	raw_local_irq_save(flags);
	*p |= mask;
	raw_local_irq_restore(flags);
}

static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
{
	unsigned long flags;
	unsigned long mask = 1UL << (bit & 31);

	p += bit >> 5;

	raw_local_irq_save(flags);
	*p &= ~mask;
	raw_local_irq_restore(flags);
}

static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
{
	unsigned long flags;
	unsigned long mask = 1UL << (bit & 31);

	p += bit >> 5;

	raw_local_irq_save(flags);
	*p ^= mask;
	raw_local_irq_restore(flags);
}

static inline int
____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
{
	unsigned long flags;
	unsigned int res;
	unsigned long mask = 1UL << (bit & 31);

	p += bit >> 5;

	raw_local_irq_save(flags);
	res = *p;
	*p = res | mask;
	raw_local_irq_restore(flags);

	return (res & mask) != 0;
}

static inline int
____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
{
	unsigned long flags;
	unsigned int res;
	unsigned long mask = 1UL << (bit & 31);

	p += bit >> 5;

	raw_local_irq_save(flags);
	res = *p;
	*p = res & ~mask;
	raw_local_irq_restore(flags);

	return (res & mask) != 0;
}

static inline int
____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
{
	unsigned long flags;
	unsigned int res;
	unsigned long mask = 1UL << (bit & 31);

	p += bit >> 5;

	raw_local_irq_save(flags);
	res = *p;
	*p = res ^ mask;
	raw_local_irq_restore(flags);

	return (res & mask) != 0;
}

#include <asm-generic/bitops/non-atomic.h>

/*
 *  A note about Endian-ness.
 *  -------------------------
 *
 * When the ARM is put into big endian mode via CR15, the processor
 * merely swaps the order of bytes within words, thus:
 *
 *          ------------ physical data bus bits -----------
 *          D31 ... D24  D23 ... D16  D15 ... D8  D7 ... D0
 * little     byte 3       byte 2       byte 1      byte 0
 * big        byte 0       byte 1       byte 2      byte 3
 *
 * This means that reading a 32-bit word at address 0 returns the same
 * value irrespective of the endian mode bit.
 *
 * Peripheral devices should be connected with the data bus reversed in
 * "Big Endian" mode.  ARM Application Note 61 is applicable, and is
 * available from http://www.arm.com/.
 *
 * The following assumes that the data bus connectivity for big endian
 * mode has been followed.
 *
 * Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0.
 */

/*
 * Native endian assembly bitops.  nr = 0 -> word 0 bit 0.
 */
extern void _set_bit(int nr, volatile unsigned long * p);
extern void _clear_bit(int nr, volatile unsigned long * p);
extern void _change_bit(int nr, volatile unsigned long * p);
extern int _test_and_set_bit(int nr, volatile unsigned long * p);
extern int _test_and_clear_bit(int nr, volatile unsigned long * p);
extern int _test_and_change_bit(int nr, volatile unsigned long * p);

/*
 * Little endian assembly bitops.  nr = 0 -> byte 0 bit 0.
 */
extern int _find_first_zero_bit_le(const void * p, unsigned size);
extern int _find_next_zero_bit_le(const void * p, int size, int offset);
extern int _find_first_bit_le(const unsigned long *p, unsigned size);
extern int _find_next_bit_le(const unsigned long *p, int size, int offset);

/*
 * Big endian assembly bitops.  nr = 0 -> byte 3 bit 0.
 */
extern int _find_first_zero_bit_be(const void * p, unsigned size);
extern int _find_next_zero_bit_be(const void * p, int size, int offset);
extern int _find_first_bit_be(const unsigned long *p, unsigned size);
extern int _find_next_bit_be(const unsigned long *p, int size, int offset);

#ifndef CONFIG_SMP
/*
 * The __* form of bitops are non-atomic and may be reordered.
 */
#define ATOMIC_BITOP(name,nr,p)			\
	(__builtin_constant_p(nr) ? ____atomic_##name(nr, p) : _##name(nr,p))
#else
#define ATOMIC_BITOP(name,nr,p)		_##name(nr,p)
#endif

/*
 * Native endian atomic definitions.
 */
#define set_bit(nr,p)			ATOMIC_BITOP(set_bit,nr,p)
#define clear_bit(nr,p)			ATOMIC_BITOP(clear_bit,nr,p)
#define change_bit(nr,p)		ATOMIC_BITOP(change_bit,nr,p)
#define test_and_set_bit(nr,p)		ATOMIC_BITOP(test_and_set_bit,nr,p)
#define test_and_clear_bit(nr,p)	ATOMIC_BITOP(test_and_clear_bit,nr,p)
#define test_and_change_bit(nr,p)	ATOMIC_BITOP(test_and_change_bit,nr,p)

#ifndef __ARMEB__
/*
 * These are the little endian, atomic definitions.
 */
#define find_first_zero_bit(p,sz)	_find_first_zero_bit_le(p,sz)
#define find_next_zero_bit(p,sz,off)	_find_next_zero_bit_le(p,sz,off)
#define find_first_bit(p,sz)		_find_first_bit_le(p,sz)
#define find_next_bit(p,sz,off)		_find_next_bit_le(p,sz,off)

#else
/*
 * These are the big endian, atomic definitions.
 */
#define find_first_zero_bit(p,sz)	_find_first_zero_bit_be(p,sz)
#define find_next_zero_bit(p,sz,off)	_find_next_zero_bit_be(p,sz,off)
#define find_first_bit(p,sz)		_find_first_bit_be(p,sz)
#define find_next_bit(p,sz,off)		_find_next_bit_be(p,sz,off)

#endif

#if __LINUX_ARM_ARCH__ < 5

#include <asm-generic/bitops/ffz.h>
#include <asm-generic/bitops/__fls.h>
#include <asm-generic/bitops/__ffs.h>
#include <asm-generic/bitops/fls.h>
#include <asm-generic/bitops/ffs.h>

#else

static inline int constant_fls(int x)
{
	int r = 32;

	if (!x)
		return 0;
	if (!(x & 0xffff0000u)) {
		x <<= 16;
		r -= 16;
	}
	if (!(x & 0xff000000u)) {
		x <<= 8;
		r -= 8;
	}
	if (!(x & 0xf0000000u)) {
		x <<= 4;
		r -= 4;
	}
	if (!(x & 0xc0000000u)) {
		x <<= 2;
		r -= 2;
	}
	if (!(x & 0x80000000u)) {
		x <<= 1;
		r -= 1;
	}
	return r;
}

/*
 * On ARMv5 and above those functions can be implemented around the
 * clz instruction for much better code efficiency.  __clz returns
 * the number of leading zeros, zero input will return 32, and
 * 0x80000000 will return 0.
 */
static inline unsigned int __clz(unsigned int x)
{
	unsigned int ret;

	asm("clz\t%0, %1" : "=r" (ret) : "r" (x));

	return ret;
}

/*
 * fls() returns zero if the input is zero, otherwise returns the bit
 * position of the last set bit, where the LSB is 1 and MSB is 32.
 */
static inline int fls(int x)
{
	if (__builtin_constant_p(x))
	       return constant_fls(x);

	return 32 - __clz(x);
}

/*
 * __fls() returns the bit position of the last bit set, where the
 * LSB is 0 and MSB is 31.  Zero input is undefined.
 */
static inline unsigned long __fls(unsigned long x)
{
	return fls(x) - 1;
}

/*
 * ffs() returns zero if the input was zero, otherwise returns the bit
 * position of the first set bit, where the LSB is 1 and MSB is 32.
 */
static inline int ffs(int x)
{
	return fls(x & -x);
}

/*
 * __ffs() returns the bit position of the first bit set, where the
 * LSB is 0 and MSB is 31.  Zero input is undefined.
 */
static inline unsigned long __ffs(unsigned long x)
{
	return ffs(x) - 1;
}

#define ffz(x) __ffs( ~(x) )

#endif

#include <asm-generic/bitops/fls64.h>

#include <asm-generic/bitops/sched.h>
#include <asm-generic/bitops/hweight.h>
#include <asm-generic/bitops/lock.h>

#ifdef __ARMEB__

static inline int find_first_zero_bit_le(const void *p, unsigned size)
{
	return _find_first_zero_bit_le(p, size);
}
#define find_first_zero_bit_le find_first_zero_bit_le

static inline int find_next_zero_bit_le(const void *p, int size, int offset)
{
	return _find_next_zero_bit_le(p, size, offset);
}
#define find_next_zero_bit_le find_next_zero_bit_le

static inline int find_next_bit_le(const void *p, int size, int offset)
{
	return _find_next_bit_le(p, size, offset);
}
#define find_next_bit_le find_next_bit_le

#endif

#include <asm-generic/bitops/le.h>

/*
 * Ext2 is defined to use little-endian byte ordering.
 */
#include <asm-generic/bitops/ext2-atomic-setbit.h>

#endif /* __KERNEL__ */

#endif /* _ARM_BITOPS_H */
Commit	Line	Data
1da177e4 LT	1	/*
	2	* Copyright 1995, Russell King.
	3	* Various bits and pieces copyrights include:
	4	* Linus Torvalds (test_bit).
	5	* Big endian support: Copyright 2001, Nicolas Pitre
	6	* reworked by rmk.
	7	*
	8	* bit 0 is the LSB of an "unsigned long" quantity.
	9	*
	10	* Please note that the code in this file should never be included
	11	* from user space. Many of these are not implemented in assembler
	12	* since they would be too costly. Also, they require privileged
	13	* instructions (which are not available from user mode) to ensure
	14	* that they are atomic.
	15	*/
	16
	17	#ifndef __ASM_ARM_BITOPS_H
	18	#define __ASM_ARM_BITOPS_H
	19
	20	#ifdef __KERNEL__
	21
0624517d JS	22	#ifndef _LINUX_BITOPS_H
	23	#error only <linux/bitops.h> can be included directly
	24	#endif
	25
8dc39b88	26	#include <linux/compiler.h>
9f97da78	27	#include <linux/irqflags.h>
030d0178	28	#include <asm/barrier.h>
1da177e4 LT	29
	30	/*
	31	* These functions are the basis of our bit ops.
	32	*
	33	* First, the atomic bitops. These use native endian.
	34	*/
	35	static inline void ____atomic_set_bit(unsigned int bit, volatile unsigned long *p)
	36	{
	37	unsigned long flags;
	38	unsigned long mask = 1UL << (bit & 31);
	39
	40	p += bit >> 5;
	41
e7cc2c59	42	raw_local_irq_save(flags);
1da177e4	43	*p \|= mask;
e7cc2c59	44	raw_local_irq_restore(flags);
1da177e4 LT	45	}
	46
	47	static inline void ____atomic_clear_bit(unsigned int bit, volatile unsigned long *p)
	48	{
	49	unsigned long flags;
	50	unsigned long mask = 1UL << (bit & 31);
	51
	52	p += bit >> 5;
	53
e7cc2c59	54	raw_local_irq_save(flags);
1da177e4	55	*p &= ~mask;
e7cc2c59	56	raw_local_irq_restore(flags);
1da177e4 LT	57	}
	58
	59	static inline void ____atomic_change_bit(unsigned int bit, volatile unsigned long *p)
	60	{
	61	unsigned long flags;
	62	unsigned long mask = 1UL << (bit & 31);
	63
	64	p += bit >> 5;
	65
e7cc2c59	66	raw_local_irq_save(flags);
1da177e4	67	*p ^= mask;
e7cc2c59	68	raw_local_irq_restore(flags);
1da177e4 LT	69	}
	70
	71	static inline int
	72	____atomic_test_and_set_bit(unsigned int bit, volatile unsigned long *p)
	73	{
	74	unsigned long flags;
	75	unsigned int res;
	76	unsigned long mask = 1UL << (bit & 31);
	77
	78	p += bit >> 5;
	79
e7cc2c59	80	raw_local_irq_save(flags);
1da177e4 LT	81	res = *p;
1da177e4 LT	82	*p = res \| mask;
e7cc2c59	83	raw_local_irq_restore(flags);
1da177e4	84
e9ac8291	85	return (res & mask) != 0;
1da177e4 LT	86	}
	87
	88	static inline int
	89	____atomic_test_and_clear_bit(unsigned int bit, volatile unsigned long *p)
	90	{
	91	unsigned long flags;
	92	unsigned int res;
	93	unsigned long mask = 1UL << (bit & 31);
	94
	95	p += bit >> 5;
	96
e7cc2c59	97	raw_local_irq_save(flags);
1da177e4 LT	98	res = *p;
1da177e4 LT	99	*p = res & ~mask;
e7cc2c59	100	raw_local_irq_restore(flags);
1da177e4	101
e9ac8291	102	return (res & mask) != 0;
1da177e4 LT	103	}
	104
	105	static inline int
	106	____atomic_test_and_change_bit(unsigned int bit, volatile unsigned long *p)
	107	{
	108	unsigned long flags;
	109	unsigned int res;
	110	unsigned long mask = 1UL << (bit & 31);
	111
	112	p += bit >> 5;
	113
e7cc2c59	114	raw_local_irq_save(flags);
1da177e4 LT	115	res = *p;
1da177e4 LT	116	*p = res ^ mask;
e7cc2c59	117	raw_local_irq_restore(flags);
1da177e4	118
e9ac8291	119	return (res & mask) != 0;
1da177e4 LT	120	}
1da177e4 LT	121
b89c3b16	122	#include <asm-generic/bitops/non-atomic.h>
1da177e4 LT	123
	124	/*
	125	* A note about Endian-ness.
	126	* -------------------------
	127	*
	128	* When the ARM is put into big endian mode via CR15, the processor
	129	* merely swaps the order of bytes within words, thus:
	130	*
	131	* ------------ physical data bus bits -----------
	132	* D31 ... D24 D23 ... D16 D15 ... D8 D7 ... D0
	133	* little byte 3 byte 2 byte 1 byte 0
	134	* big byte 0 byte 1 byte 2 byte 3
	135	*
	136	* This means that reading a 32-bit word at address 0 returns the same
	137	* value irrespective of the endian mode bit.
	138	*
	139	* Peripheral devices should be connected with the data bus reversed in
	140	* "Big Endian" mode. ARM Application Note 61 is applicable, and is
	141	* available from http://www.arm.com/.
	142	*
	143	* The following assumes that the data bus connectivity for big endian
	144	* mode has been followed.
	145	*
	146	* Note that bit 0 is defined to be 32-bit word bit 0, not byte 0 bit 0.
	147	*/
	148
6323f0cc RK	149	/*
	150	* Native endian assembly bitops. nr = 0 -> word 0 bit 0.
	151	*/
	152	extern void _set_bit(int nr, volatile unsigned long * p);
	153	extern void _clear_bit(int nr, volatile unsigned long * p);
	154	extern void _change_bit(int nr, volatile unsigned long * p);
	155	extern int _test_and_set_bit(int nr, volatile unsigned long * p);
	156	extern int _test_and_clear_bit(int nr, volatile unsigned long * p);
	157	extern int _test_and_change_bit(int nr, volatile unsigned long * p);
	158
1da177e4 LT	159	/*
	160	* Little endian assembly bitops. nr = 0 -> byte 0 bit 0.
	161	*/
1da177e4 LT	162	extern int _find_first_zero_bit_le(const void * p, unsigned size);
	163	extern int _find_next_zero_bit_le(const void * p, int size, int offset);
	164	extern int _find_first_bit_le(const unsigned long *p, unsigned size);
	165	extern int _find_next_bit_le(const unsigned long *p, int size, int offset);
	166
	167	/*
	168	* Big endian assembly bitops. nr = 0 -> byte 3 bit 0.
	169	*/
1da177e4 LT	170	extern int _find_first_zero_bit_be(const void * p, unsigned size);
	171	extern int _find_next_zero_bit_be(const void * p, int size, int offset);
	172	extern int _find_first_bit_be(const unsigned long *p, unsigned size);
	173	extern int _find_next_bit_be(const unsigned long *p, int size, int offset);
	174
e7ec0293	175	#ifndef CONFIG_SMP
1da177e4 LT	176	/*
	177	* The __* form of bitops are non-atomic and may be reordered.
	178	*/
6323f0cc RK	179	#define ATOMIC_BITOP(name,nr,p) \
6323f0cc RK	180	(__builtin_constant_p(nr) ? ____atomic_##name(nr, p) : _##name(nr,p))
e7ec0293	181	#else
6323f0cc	182	#define ATOMIC_BITOP(name,nr,p) _##name(nr,p)
e7ec0293	183	#endif
1da177e4	184
6323f0cc RK	185	/*
	186	* Native endian atomic definitions.
	187	*/
	188	#define set_bit(nr,p) ATOMIC_BITOP(set_bit,nr,p)
	189	#define clear_bit(nr,p) ATOMIC_BITOP(clear_bit,nr,p)
	190	#define change_bit(nr,p) ATOMIC_BITOP(change_bit,nr,p)
	191	#define test_and_set_bit(nr,p) ATOMIC_BITOP(test_and_set_bit,nr,p)
	192	#define test_and_clear_bit(nr,p) ATOMIC_BITOP(test_and_clear_bit,nr,p)
	193	#define test_and_change_bit(nr,p) ATOMIC_BITOP(test_and_change_bit,nr,p)
1da177e4 LT	194
	195	#ifndef __ARMEB__
	196	/*
	197	* These are the little endian, atomic definitions.
	198	*/
1da177e4 LT	199	#define find_first_zero_bit(p,sz) _find_first_zero_bit_le(p,sz)
	200	#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_le(p,sz,off)
	201	#define find_first_bit(p,sz) _find_first_bit_le(p,sz)
	202	#define find_next_bit(p,sz,off) _find_next_bit_le(p,sz,off)
	203
1da177e4	204	#else
1da177e4 LT	205	/*
	206	* These are the big endian, atomic definitions.
	207	*/
1da177e4 LT	208	#define find_first_zero_bit(p,sz) _find_first_zero_bit_be(p,sz)
	209	#define find_next_zero_bit(p,sz,off) _find_next_zero_bit_be(p,sz,off)
	210	#define find_first_bit(p,sz) _find_first_bit_be(p,sz)
	211	#define find_next_bit(p,sz,off) _find_next_bit_be(p,sz,off)
	212
1da177e4 LT	213	#endif
	214
	215	#if __LINUX_ARM_ARCH__ < 5
	216
b89c3b16	217	#include <asm-generic/bitops/ffz.h>
94fc7336	218	#include <asm-generic/bitops/__fls.h>
b89c3b16 AM	219	#include <asm-generic/bitops/__ffs.h>
	220	#include <asm-generic/bitops/fls.h>
	221	#include <asm-generic/bitops/ffs.h>
1da177e4 LT	222
	223	#else
	224
93635133 AM	225	static inline int constant_fls(int x)
	226	{
	227	int r = 32;
	228
	229	if (!x)
	230	return 0;
	231	if (!(x & 0xffff0000u)) {
	232	x <<= 16;
	233	r -= 16;
	234	}
	235	if (!(x & 0xff000000u)) {
	236	x <<= 8;
	237	r -= 8;
	238	}
	239	if (!(x & 0xf0000000u)) {
	240	x <<= 4;
	241	r -= 4;
	242	}
	243	if (!(x & 0xc0000000u)) {
	244	x <<= 2;
	245	r -= 2;
	246	}
	247	if (!(x & 0x80000000u)) {
	248	x <<= 1;
	249	r -= 1;
	250	}
	251	return r;
	252	}
	253
1da177e4	254	/*
23f6620a RK	255	* On ARMv5 and above those functions can be implemented around the
	256	* clz instruction for much better code efficiency. __clz returns
	257	* the number of leading zeros, zero input will return 32, and
	258	* 0x80000000 will return 0.
1da177e4	259	*/
23f6620a RK	260	static inline unsigned int __clz(unsigned int x)
	261	{
	262	unsigned int ret;
	263
	264	asm("clz\t%0, %1" : "=r" (ret) : "r" (x));
1da177e4	265
23f6620a RK	266	return ret;
	267	}
	268
	269	/*
	270	* fls() returns zero if the input is zero, otherwise returns the bit
	271	* position of the last set bit, where the LSB is 1 and MSB is 32.
	272	*/
0c65f459 AM	273	static inline int fls(int x)
0c65f459 AM	274	{
94fc7336 NP	275	if (__builtin_constant_p(x))
	276	return constant_fls(x);
	277
23f6620a RK	278	return 32 - __clz(x);
	279	}
	280
	281	/*
	282	* __fls() returns the bit position of the last bit set, where the
	283	* LSB is 0 and MSB is 31. Zero input is undefined.
	284	*/
	285	static inline unsigned long __fls(unsigned long x)
	286	{
	287	return fls(x) - 1;
	288	}
	289
	290	/*
	291	* ffs() returns zero if the input was zero, otherwise returns the bit
	292	* position of the first set bit, where the LSB is 1 and MSB is 32.
	293	*/
	294	static inline int ffs(int x)
	295	{
	296	return fls(x & -x);
	297	}
	298
	299	/*
	300	* __ffs() returns the bit position of the first bit set, where the
	301	* LSB is 0 and MSB is 31. Zero input is undefined.
	302	*/
	303	static inline unsigned long __ffs(unsigned long x)
	304	{
	305	return ffs(x) - 1;
0c65f459 AM	306	}
0c65f459 AM	307
1da177e4 LT	308	#define ffz(x) __ffs( ~(x) )
	309
	310	#endif
	311
b89c3b16	312	#include <asm-generic/bitops/fls64.h>
1da177e4	313
b89c3b16 AM	314	#include <asm-generic/bitops/sched.h>
b89c3b16 AM	315	#include <asm-generic/bitops/hweight.h>
26333576	316	#include <asm-generic/bitops/lock.h>
1da177e4	317
04b18ff9	318	#ifdef __ARMEB__
f6b57e32 AM	319
	320	static inline int find_first_zero_bit_le(const void *p, unsigned size)
	321	{
	322	return _find_first_zero_bit_le(p, size);
	323	}
a2812e17	324	#define find_first_zero_bit_le find_first_zero_bit_le
f6b57e32 AM	325
	326	static inline int find_next_zero_bit_le(const void *p, int size, int offset)
	327	{
	328	return _find_next_zero_bit_le(p, size, offset);
	329	}
a2812e17	330	#define find_next_zero_bit_le find_next_zero_bit_le
f6b57e32 AM	331
	332	static inline int find_next_bit_le(const void *p, int size, int offset)
	333	{
	334	return _find_next_bit_le(p, size, offset);
	335	}
a2812e17	336	#define find_next_bit_le find_next_bit_le
f6b57e32	337
04b18ff9 AM	338	#endif
	339
	340	#include <asm-generic/bitops/le.h>
	341
1da177e4 LT	342	/*
1da177e4 LT	343	* Ext2 is defined to use little-endian byte ordering.
1da177e4	344	*/
148817ba	345	#include <asm-generic/bitops/ext2-atomic-setbit.h>
1da177e4	346
1da177e4 LT	347	#endif /* __KERNEL__ */
	348
	349	#endif /* _ARM_BITOPS_H */