[deliverable/linux.git] / arch / arm / include / asm / cputype.h

#ifndef __ASM_ARM_CPUTYPE_H
#define __ASM_ARM_CPUTYPE_H

#include <linux/stringify.h>
#include <linux/kernel.h>

#define CPUID_ID	0
#define CPUID_CACHETYPE	1
#define CPUID_TCM	2
#define CPUID_TLBTYPE	3
#define CPUID_MPUIR	4
#define CPUID_MPIDR	5
#define CPUID_REVIDR	6

#ifdef CONFIG_CPU_V7M
#define CPUID_EXT_PFR0	0x40
#define CPUID_EXT_PFR1	0x44
#define CPUID_EXT_DFR0	0x48
#define CPUID_EXT_AFR0	0x4c
#define CPUID_EXT_MMFR0	0x50
#define CPUID_EXT_MMFR1	0x54
#define CPUID_EXT_MMFR2	0x58
#define CPUID_EXT_MMFR3	0x5c
#define CPUID_EXT_ISAR0	0x60
#define CPUID_EXT_ISAR1	0x64
#define CPUID_EXT_ISAR2	0x68
#define CPUID_EXT_ISAR3	0x6c
#define CPUID_EXT_ISAR4	0x70
#define CPUID_EXT_ISAR5	0x74
#else
#define CPUID_EXT_PFR0	"c1, 0"
#define CPUID_EXT_PFR1	"c1, 1"
#define CPUID_EXT_DFR0	"c1, 2"
#define CPUID_EXT_AFR0	"c1, 3"
#define CPUID_EXT_MMFR0	"c1, 4"
#define CPUID_EXT_MMFR1	"c1, 5"
#define CPUID_EXT_MMFR2	"c1, 6"
#define CPUID_EXT_MMFR3	"c1, 7"
#define CPUID_EXT_ISAR0	"c2, 0"
#define CPUID_EXT_ISAR1	"c2, 1"
#define CPUID_EXT_ISAR2	"c2, 2"
#define CPUID_EXT_ISAR3	"c2, 3"
#define CPUID_EXT_ISAR4	"c2, 4"
#define CPUID_EXT_ISAR5	"c2, 5"
#endif

#define MPIDR_SMP_BITMASK (0x3 << 30)
#define MPIDR_SMP_VALUE (0x2 << 30)

#define MPIDR_MT_BITMASK (0x1 << 24)

#define MPIDR_HWID_BITMASK 0xFFFFFF

#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)

#define MPIDR_LEVEL_BITS 8
#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)

#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
	((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)

#define ARM_CPU_IMP_ARM			0x41
#define ARM_CPU_IMP_INTEL		0x69

/* ARM implemented processors */
#define ARM_CPU_PART_ARM1136		0x4100b360
#define ARM_CPU_PART_ARM1156		0x4100b560
#define ARM_CPU_PART_ARM1176		0x4100b760
#define ARM_CPU_PART_ARM11MPCORE	0x4100b020
#define ARM_CPU_PART_CORTEX_A8		0x4100c080
#define ARM_CPU_PART_CORTEX_A9		0x4100c090
#define ARM_CPU_PART_CORTEX_A5		0x4100c050
#define ARM_CPU_PART_CORTEX_A7		0x4100c070
#define ARM_CPU_PART_CORTEX_A12		0x4100c0d0
#define ARM_CPU_PART_CORTEX_A17		0x4100c0e0
#define ARM_CPU_PART_CORTEX_A15		0x4100c0f0
#define ARM_CPU_PART_MASK		0xff00fff0

#define ARM_CPU_XSCALE_ARCH_MASK	0xe000
#define ARM_CPU_XSCALE_ARCH_V1		0x2000
#define ARM_CPU_XSCALE_ARCH_V2		0x4000
#define ARM_CPU_XSCALE_ARCH_V3		0x6000

extern unsigned int processor_id;

#ifdef CONFIG_CPU_CP15
#define read_cpuid(reg)							\
	({								\
		unsigned int __val;					\
		asm("mrc	p15, 0, %0, c0, c0, " __stringify(reg)	\
		    : "=r" (__val)					\
		    :							\
		    : "cc");						\
		__val;							\
	})

/*
 * The memory clobber prevents gcc 4.5 from reordering the mrc before
 * any is_smp() tests, which can cause undefined instruction aborts on
 * ARM1136 r0 due to the missing extended CP15 registers.
 */
#define read_cpuid_ext(ext_reg)						\
	({								\
		unsigned int __val;					\
		asm("mrc	p15, 0, %0, c0, " ext_reg		\
		    : "=r" (__val)					\
		    :							\
		    : "memory");					\
		__val;							\
	})

#elif defined(CONFIG_CPU_V7M)

#include <asm/io.h>
#include <asm/v7m.h>

#define read_cpuid(reg)							\
	({								\
		WARN_ON_ONCE(1);					\
		0;							\
	})

static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
{
	return readl(BASEADDR_V7M_SCB + offset);
}

#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */

/*
 * read_cpuid and read_cpuid_ext should only ever be called on machines that
 * have cp15 so warn on other usages.
 */
#define read_cpuid(reg)							\
	({								\
		WARN_ON_ONCE(1);					\
		0;							\
	})

#define read_cpuid_ext(reg) read_cpuid(reg)

#endif /* ifdef CONFIG_CPU_CP15 / else */

#ifdef CONFIG_CPU_CP15
/*
 * The CPU ID never changes at run time, so we might as well tell the
 * compiler that it's constant.  Use this function to read the CPU ID
 * rather than directly reading processor_id or read_cpuid() directly.
 */
static inline unsigned int __attribute_const__ read_cpuid_id(void)
{
	return read_cpuid(CPUID_ID);
}

#elif defined(CONFIG_CPU_V7M)

static inline unsigned int __attribute_const__ read_cpuid_id(void)
{
	return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
}

#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */

static inline unsigned int __attribute_const__ read_cpuid_id(void)
{
	return processor_id;
}

#endif /* ifdef CONFIG_CPU_CP15 / else */

static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
{
	return (read_cpuid_id() & 0xFF000000) >> 24;
}

/*
 * The CPU part number is meaningless without referring to the CPU
 * implementer: implementers are free to define their own part numbers
 * which are permitted to clash with other implementer part numbers.
 */
static inline unsigned int __attribute_const__ read_cpuid_part(void)
{
	return read_cpuid_id() & ARM_CPU_PART_MASK;
}

static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
{
	return read_cpuid_id() & 0xFFF0;
}

static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
{
	return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
}

static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
{
	return read_cpuid(CPUID_CACHETYPE);
}

static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
{
	return read_cpuid(CPUID_TCM);
}

static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
{
	return read_cpuid(CPUID_MPIDR);
}

/*
 * Intel's XScale3 core supports some v6 features (supersections, L2)
 * but advertises itself as v5 as it does not support the v6 ISA.  For
 * this reason, we need a way to explicitly test for this type of CPU.
 */
#ifndef CONFIG_CPU_XSC3
#define cpu_is_xsc3()	0
#else
static inline int cpu_is_xsc3(void)
{
	unsigned int id;
	id = read_cpuid_id() & 0xffffe000;
	/* It covers both Intel ID and Marvell ID */
	if ((id == 0x69056000) || (id == 0x56056000))
		return 1;

	return 0;
}
#endif

#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
    !defined(CONFIG_CPU_MOHAWK)
#define	cpu_is_xscale_family() 0
#else
static inline int cpu_is_xscale_family(void)
{
	unsigned int id;
	id = read_cpuid_id() & 0xffffe000;

	switch (id) {
	case 0x69052000: /* Intel XScale 1 */
	case 0x69054000: /* Intel XScale 2 */
	case 0x69056000: /* Intel XScale 3 */
	case 0x56056000: /* Marvell XScale 3 */
	case 0x56158000: /* Marvell Mohawk */
		return 1;
	}

	return 0;
}
#endif

/*
 * Marvell's PJ4 and PJ4B cores are based on V7 version,
 * but require a specical sequence for enabling coprocessors.
 * For this reason, we need a way to distinguish them.
 */
#if defined(CONFIG_CPU_PJ4) || defined(CONFIG_CPU_PJ4B)
static inline int cpu_is_pj4(void)
{
	unsigned int id;

	id = read_cpuid_id();
	if ((id & 0xff0fff00) == 0x560f5800)
		return 1;

	return 0;
}
#else
#define cpu_is_pj4()	0
#endif

static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
								  int field)
{
	int feature = (features >> field) & 15;

	/* feature registers are signed values */
	if (feature > 8)
		feature -= 16;

	return feature;
}

#define cpuid_feature_extract(reg, field) \
	cpuid_feature_extract_field(read_cpuid_ext(reg), field)

#endif
Commit	Line	Data
0ba8b9b2 RK	1	#ifndef __ASM_ARM_CPUTYPE_H
	2	#define __ASM_ARM_CPUTYPE_H
	3
	4	#include <linux/stringify.h>
e9569c15	5	#include <linux/kernel.h>
0ba8b9b2 RK	6
	7	#define CPUID_ID 0
	8	#define CPUID_CACHETYPE 1
	9	#define CPUID_TCM 2
	10	#define CPUID_TLBTYPE 3
aca7e592	11	#define CPUID_MPUIR 4
c9018aab	12	#define CPUID_MPIDR 5
92871b94	13	#define CPUID_REVIDR 6
0ba8b9b2	14
6fae9cda UKK	15	#ifdef CONFIG_CPU_V7M
	16	#define CPUID_EXT_PFR0 0x40
	17	#define CPUID_EXT_PFR1 0x44
	18	#define CPUID_EXT_DFR0 0x48
	19	#define CPUID_EXT_AFR0 0x4c
	20	#define CPUID_EXT_MMFR0 0x50
	21	#define CPUID_EXT_MMFR1 0x54
	22	#define CPUID_EXT_MMFR2 0x58
	23	#define CPUID_EXT_MMFR3 0x5c
	24	#define CPUID_EXT_ISAR0 0x60
	25	#define CPUID_EXT_ISAR1 0x64
	26	#define CPUID_EXT_ISAR2 0x68
	27	#define CPUID_EXT_ISAR3 0x6c
	28	#define CPUID_EXT_ISAR4 0x70
	29	#define CPUID_EXT_ISAR5 0x74
	30	#else
faa7bc51 CM	31	#define CPUID_EXT_PFR0 "c1, 0"
	32	#define CPUID_EXT_PFR1 "c1, 1"
	33	#define CPUID_EXT_DFR0 "c1, 2"
	34	#define CPUID_EXT_AFR0 "c1, 3"
	35	#define CPUID_EXT_MMFR0 "c1, 4"
	36	#define CPUID_EXT_MMFR1 "c1, 5"
	37	#define CPUID_EXT_MMFR2 "c1, 6"
	38	#define CPUID_EXT_MMFR3 "c1, 7"
	39	#define CPUID_EXT_ISAR0 "c2, 0"
	40	#define CPUID_EXT_ISAR1 "c2, 1"
	41	#define CPUID_EXT_ISAR2 "c2, 2"
	42	#define CPUID_EXT_ISAR3 "c2, 3"
	43	#define CPUID_EXT_ISAR4 "c2, 4"
	44	#define CPUID_EXT_ISAR5 "c2, 5"
6fae9cda	45	#endif
faa7bc51	46
dca463da LP	47	#define MPIDR_SMP_BITMASK (0x3 << 30)
	48	#define MPIDR_SMP_VALUE (0x2 << 30)
	49
	50	#define MPIDR_MT_BITMASK (0x1 << 24)
	51
	52	#define MPIDR_HWID_BITMASK 0xFFFFFF
	53
18d7f152 LP	54	#define MPIDR_INVALID (~MPIDR_HWID_BITMASK)
18d7f152 LP	55
dca463da LP	56	#define MPIDR_LEVEL_BITS 8
	57	#define MPIDR_LEVEL_MASK ((1 << MPIDR_LEVEL_BITS) - 1)
	58
	59	#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
	60	((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
	61
73a09d21 RK	62	#define ARM_CPU_IMP_ARM 0x41
	63	#define ARM_CPU_IMP_INTEL 0x69
	64
af040ffc RK	65	/* ARM implemented processors */
	66	#define ARM_CPU_PART_ARM1136 0x4100b360
	67	#define ARM_CPU_PART_ARM1156 0x4100b560
	68	#define ARM_CPU_PART_ARM1176 0x4100b760
	69	#define ARM_CPU_PART_ARM11MPCORE 0x4100b020
	70	#define ARM_CPU_PART_CORTEX_A8 0x4100c080
	71	#define ARM_CPU_PART_CORTEX_A9 0x4100c090
	72	#define ARM_CPU_PART_CORTEX_A5 0x4100c050
	73	#define ARM_CPU_PART_CORTEX_A7 0x4100c070
	74	#define ARM_CPU_PART_CORTEX_A12 0x4100c0d0
	75	#define ARM_CPU_PART_CORTEX_A17 0x4100c0e0
	76	#define ARM_CPU_PART_CORTEX_A15 0x4100c0f0
eba1c718	77	#define ARM_CPU_PART_MASK 0xff00fff0
73a09d21 RK	78
	79	#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
	80	#define ARM_CPU_XSCALE_ARCH_V1 0x2000
	81	#define ARM_CPU_XSCALE_ARCH_V2 0x4000
	82	#define ARM_CPU_XSCALE_ARCH_V3 0x6000
	83
2bbd7e9b RK	84	extern unsigned int processor_id;
2bbd7e9b RK	85
0ba8b9b2 RK	86	#ifdef CONFIG_CPU_CP15
	87	#define read_cpuid(reg) \
	88	({ \
	89	unsigned int __val; \
	90	asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \
	91	: "=r" (__val) \
	92	: \
	93	: "cc"); \
	94	__val; \
	95	})
6ebd4d03	96
067e710b PW	97	/*
	98	* The memory clobber prevents gcc 4.5 from reordering the mrc before
	99	* any is_smp() tests, which can cause undefined instruction aborts on
	100	* ARM1136 r0 due to the missing extended CP15 registers.
	101	*/
faa7bc51 CM	102	#define read_cpuid_ext(ext_reg) \
	103	({ \
	104	unsigned int __val; \
	105	asm("mrc p15, 0, %0, c0, " ext_reg \
	106	: "=r" (__val) \
	107	: \
067e710b	108	: "memory"); \
faa7bc51 CM	109	__val; \
faa7bc51 CM	110	})
0ba8b9b2	111
6fae9cda UKK	112	#elif defined(CONFIG_CPU_V7M)
	113
	114	#include <asm/io.h>
	115	#include <asm/v7m.h>
	116
	117	#define read_cpuid(reg) \
	118	({ \
	119	WARN_ON_ONCE(1); \
	120	0; \
	121	})
	122
	123	static inline unsigned int __attribute_const__ read_cpuid_ext(unsigned offset)
	124	{
	125	return readl(BASEADDR_V7M_SCB + offset);
	126	}
	127
	128	#else /* ifdef CONFIG_CPU_CP15 / elif defined (CONFIG_CPU_V7M) */
59530adc	129
6ebd4d03 UKK	130	/*
	131	* read_cpuid and read_cpuid_ext should only ever be called on machines that
	132	* have cp15 so warn on other usages.
	133	*/
	134	#define read_cpuid(reg) \
	135	({ \
	136	WARN_ON_ONCE(1); \
	137	0; \
	138	})
59530adc	139
6ebd4d03	140	#define read_cpuid_ext(reg) read_cpuid(reg)
59530adc	141
6ebd4d03 UKK	142	#endif /* ifdef CONFIG_CPU_CP15 / else */
	143
	144	#ifdef CONFIG_CPU_CP15
0ba8b9b2 RK	145	/*
	146	* The CPU ID never changes at run time, so we might as well tell the
	147	* compiler that it's constant. Use this function to read the CPU ID
	148	* rather than directly reading processor_id or read_cpuid() directly.
	149	*/
	150	static inline unsigned int __attribute_const__ read_cpuid_id(void)
	151	{
	152	return read_cpuid(CPUID_ID);
	153	}
	154
55bdd694 CM	155	#elif defined(CONFIG_CPU_V7M)
55bdd694 CM	156
55bdd694 CM	157	static inline unsigned int __attribute_const__ read_cpuid_id(void)
	158	{
	159	return readl(BASEADDR_V7M_SCB + V7M_SCB_CPUID);
	160	}
	161
	162	#else /* ifdef CONFIG_CPU_CP15 / elif defined(CONFIG_CPU_V7M) */
6ebd4d03 UKK	163
	164	static inline unsigned int __attribute_const__ read_cpuid_id(void)
	165	{
	166	return processor_id;
	167	}
	168
	169	#endif /* ifdef CONFIG_CPU_CP15 / else */
	170
59530adc CD	171	static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
	172	{
	173	return (read_cpuid_id() & 0xFF000000) >> 24;
	174	}
	175
af040ffc RK	176	/*
	177	* The CPU part number is meaningless without referring to the CPU
	178	* implementer: implementers are free to define their own part numbers
	179	* which are permitted to clash with other implementer part numbers.
	180	*/
	181	static inline unsigned int __attribute_const__ read_cpuid_part(void)
	182	{
eba1c718	183	return read_cpuid_id() & ARM_CPU_PART_MASK;
af040ffc RK	184	}
	185
	186	static inline unsigned int __attribute_const__ __deprecated read_cpuid_part_number(void)
59530adc CD	187	{
	188	return read_cpuid_id() & 0xFFF0;
	189	}
	190
	191	static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
	192	{
af040ffc	193	return read_cpuid_id() & ARM_CPU_XSCALE_ARCH_MASK;
59530adc CD	194	}
59530adc CD	195
0ba8b9b2 RK	196	static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
	197	{
	198	return read_cpuid(CPUID_CACHETYPE);
	199	}
	200
bc581770 LW	201	static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void)
	202	{
	203	return read_cpuid(CPUID_TCM);
	204	}
	205
c9018aab VG	206	static inline unsigned int __attribute_const__ read_cpuid_mpidr(void)
	207	{
	208	return read_cpuid(CPUID_MPIDR);
	209	}
	210
0ba8b9b2 RK	211	/*
	212	* Intel's XScale3 core supports some v6 features (supersections, L2)
	213	* but advertises itself as v5 as it does not support the v6 ISA. For
	214	* this reason, we need a way to explicitly test for this type of CPU.
	215	*/
	216	#ifndef CONFIG_CPU_XSC3
	217	#define cpu_is_xsc3() 0
	218	#else
	219	static inline int cpu_is_xsc3(void)
	220	{
337c1db6 HZ	221	unsigned int id;
	222	id = read_cpuid_id() & 0xffffe000;
	223	/* It covers both Intel ID and Marvell ID */
	224	if ((id == 0x69056000) \|\| (id == 0x56056000))
0ba8b9b2 RK	225	return 1;
	226
	227	return 0;
	228	}
	229	#endif
	230
d33c43ac AB	231	#if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) && \
	232	!defined(CONFIG_CPU_MOHAWK)
	233	#define cpu_is_xscale_family() 0
0ba8b9b2	234	#else
d33c43ac AB	235	static inline int cpu_is_xscale_family(void)
	236	{
	237	unsigned int id;
	238	id = read_cpuid_id() & 0xffffe000;
	239
	240	switch (id) {
	241	case 0x69052000: /* Intel XScale 1 */
	242	case 0x69054000: /* Intel XScale 2 */
	243	case 0x69056000: /* Intel XScale 3 */
	244	case 0x56056000: /* Marvell XScale 3 */
	245	case 0x56158000: /* Marvell Mohawk */
	246	return 1;
	247	}
	248
	249	return 0;
	250	}
0ba8b9b2 RK	251	#endif
0ba8b9b2 RK	252
fdb487f5	253	/*
cd171170 SH	254	* Marvell's PJ4 and PJ4B cores are based on V7 version,
	255	* but require a specical sequence for enabling coprocessors.
	256	* For this reason, we need a way to distinguish them.
fdb487f5	257	*/
cd171170	258	#if defined(CONFIG_CPU_PJ4) \|\| defined(CONFIG_CPU_PJ4B)
fdb487f5 CXL	259	static inline int cpu_is_pj4(void)
	260	{
	261	unsigned int id;
	262
	263	id = read_cpuid_id();
cd171170	264	if ((id & 0xff0fff00) == 0x560f5800)
fdb487f5 CXL	265	return 1;
	266
	267	return 0;
	268	}
cd171170 SH	269	#else
cd171170 SH	270	#define cpu_is_pj4() 0
fdb487f5	271	#endif
b8c9592b AB	272
	273	static inline int __attribute_const__ cpuid_feature_extract_field(u32 features,
	274	int field)
	275	{
	276	int feature = (features >> field) & 15;
	277
	278	/* feature registers are signed values */
	279	if (feature > 8)
	280	feature -= 16;
	281
	282	return feature;
	283	}
	284
	285	#define cpuid_feature_extract(reg, field) \
	286	cpuid_feature_extract_field(read_cpuid_ext(reg), field)
	287
0ba8b9b2	288	#endif