Commit | Line | Data |
---|---|---|
0ba8b9b2 RK |
1 | #ifndef __ASM_ARM_CPUTYPE_H |
2 | #define __ASM_ARM_CPUTYPE_H | |
3 | ||
4 | #include <linux/stringify.h> | |
e9569c15 | 5 | #include <linux/kernel.h> |
0ba8b9b2 RK |
6 | |
7 | #define CPUID_ID 0 | |
8 | #define CPUID_CACHETYPE 1 | |
9 | #define CPUID_TCM 2 | |
10 | #define CPUID_TLBTYPE 3 | |
11 | ||
faa7bc51 CM |
12 | #define CPUID_EXT_PFR0 "c1, 0" |
13 | #define CPUID_EXT_PFR1 "c1, 1" | |
14 | #define CPUID_EXT_DFR0 "c1, 2" | |
15 | #define CPUID_EXT_AFR0 "c1, 3" | |
16 | #define CPUID_EXT_MMFR0 "c1, 4" | |
17 | #define CPUID_EXT_MMFR1 "c1, 5" | |
18 | #define CPUID_EXT_MMFR2 "c1, 6" | |
19 | #define CPUID_EXT_MMFR3 "c1, 7" | |
20 | #define CPUID_EXT_ISAR0 "c2, 0" | |
21 | #define CPUID_EXT_ISAR1 "c2, 1" | |
22 | #define CPUID_EXT_ISAR2 "c2, 2" | |
23 | #define CPUID_EXT_ISAR3 "c2, 3" | |
24 | #define CPUID_EXT_ISAR4 "c2, 4" | |
25 | #define CPUID_EXT_ISAR5 "c2, 5" | |
26 | ||
2bbd7e9b RK |
27 | extern unsigned int processor_id; |
28 | ||
0ba8b9b2 RK |
29 | #ifdef CONFIG_CPU_CP15 |
30 | #define read_cpuid(reg) \ | |
31 | ({ \ | |
32 | unsigned int __val; \ | |
33 | asm("mrc p15, 0, %0, c0, c0, " __stringify(reg) \ | |
34 | : "=r" (__val) \ | |
35 | : \ | |
36 | : "cc"); \ | |
37 | __val; \ | |
38 | }) | |
faa7bc51 CM |
39 | #define read_cpuid_ext(ext_reg) \ |
40 | ({ \ | |
41 | unsigned int __val; \ | |
42 | asm("mrc p15, 0, %0, c0, " ext_reg \ | |
43 | : "=r" (__val) \ | |
44 | : \ | |
45 | : "cc"); \ | |
46 | __val; \ | |
47 | }) | |
0ba8b9b2 | 48 | #else |
0ba8b9b2 | 49 | #define read_cpuid(reg) (processor_id) |
faa7bc51 | 50 | #define read_cpuid_ext(reg) 0 |
0ba8b9b2 RK |
51 | #endif |
52 | ||
53 | /* | |
54 | * The CPU ID never changes at run time, so we might as well tell the | |
55 | * compiler that it's constant. Use this function to read the CPU ID | |
56 | * rather than directly reading processor_id or read_cpuid() directly. | |
57 | */ | |
58 | static inline unsigned int __attribute_const__ read_cpuid_id(void) | |
59 | { | |
60 | return read_cpuid(CPUID_ID); | |
61 | } | |
62 | ||
63 | static inline unsigned int __attribute_const__ read_cpuid_cachetype(void) | |
64 | { | |
65 | return read_cpuid(CPUID_CACHETYPE); | |
66 | } | |
67 | ||
bc581770 LW |
68 | static inline unsigned int __attribute_const__ read_cpuid_tcmstatus(void) |
69 | { | |
70 | return read_cpuid(CPUID_TCM); | |
71 | } | |
72 | ||
0ba8b9b2 RK |
73 | /* |
74 | * Intel's XScale3 core supports some v6 features (supersections, L2) | |
75 | * but advertises itself as v5 as it does not support the v6 ISA. For | |
76 | * this reason, we need a way to explicitly test for this type of CPU. | |
77 | */ | |
78 | #ifndef CONFIG_CPU_XSC3 | |
79 | #define cpu_is_xsc3() 0 | |
80 | #else | |
81 | static inline int cpu_is_xsc3(void) | |
82 | { | |
337c1db6 HZ |
83 | unsigned int id; |
84 | id = read_cpuid_id() & 0xffffe000; | |
85 | /* It covers both Intel ID and Marvell ID */ | |
86 | if ((id == 0x69056000) || (id == 0x56056000)) | |
0ba8b9b2 RK |
87 | return 1; |
88 | ||
89 | return 0; | |
90 | } | |
91 | #endif | |
92 | ||
93 | #if !defined(CONFIG_CPU_XSCALE) && !defined(CONFIG_CPU_XSC3) | |
94 | #define cpu_is_xscale() 0 | |
95 | #else | |
96 | #define cpu_is_xscale() 1 | |
97 | #endif | |
98 | ||
99 | #endif |