[deliverable/linux.git] / arch / arm / include / asm / domain.h

/*
 *  arch/arm/include/asm/domain.h
 *
 *  Copyright (C) 1999 Russell King.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef __ASM_PROC_DOMAIN_H
#define __ASM_PROC_DOMAIN_H

#ifndef __ASSEMBLY__
#include <asm/barrier.h>
#endif

/*
 * Domain numbers
 *
 *  DOMAIN_IO     - domain 2 includes all IO only
 *  DOMAIN_USER   - domain 1 includes all user memory only
 *  DOMAIN_KERNEL - domain 0 includes all kernel memory only
 *
 * The domain numbering depends on whether we support 36 physical
 * address for I/O or not.  Addresses above the 32 bit boundary can
 * only be mapped using supersections and supersections can only
 * be set for domain 0.  We could just default to DOMAIN_IO as zero,
 * but there may be systems with supersection support and no 36-bit
 * addressing.  In such cases, we want to map system memory with
 * supersections to reduce TLB misses and footprint.
 *
 * 36-bit addressing and supersections are only available on
 * CPUs based on ARMv6+ or the Intel XSC3 core.
 */
#ifndef CONFIG_IO_36
#define DOMAIN_KERNEL	0
#define DOMAIN_TABLE	0
#define DOMAIN_USER	1
#define DOMAIN_IO	2
#else
#define DOMAIN_KERNEL	2
#define DOMAIN_TABLE	2
#define DOMAIN_USER	1
#define DOMAIN_IO	0
#endif

/*
 * Domain types
 */
#define DOMAIN_NOACCESS	0
#define DOMAIN_CLIENT	1
#ifdef CONFIG_CPU_USE_DOMAINS
#define DOMAIN_MANAGER	3
#else
#define DOMAIN_MANAGER	1
#endif

#define domain_val(dom,type)	((type) << (2*(dom)))

#ifndef __ASSEMBLY__

#ifdef CONFIG_CPU_USE_DOMAINS
static inline void set_domain(unsigned val)
{
	asm volatile(
	"mcr	p15, 0, %0, c3, c0	@ set domain"
	  : : "r" (val));
	isb();
}

#define modify_domain(dom,type)					\
	do {							\
	struct thread_info *thread = current_thread_info();	\
	unsigned int domain = thread->cpu_domain;		\
	domain &= ~domain_val(dom, DOMAIN_MANAGER);		\
	thread->cpu_domain = domain | domain_val(dom, type);	\
	set_domain(thread->cpu_domain);				\
	} while (0)

#else
static inline void set_domain(unsigned val) { }
static inline void modify_domain(unsigned dom, unsigned type)	{ }
#endif

/*
 * Generate the T (user) versions of the LDR/STR and related
 * instructions (inline assembly)
 */
#ifdef CONFIG_CPU_USE_DOMAINS
#define TUSER(instr)	#instr "t"
#else
#define TUSER(instr)	#instr
#endif

#else /* __ASSEMBLY__ */

/*
 * Generate the T (user) versions of the LDR/STR and related
 * instructions
 */
#ifdef CONFIG_CPU_USE_DOMAINS
#define TUSER(instr)	instr ## t
#else
#define TUSER(instr)	instr
#endif

#endif /* __ASSEMBLY__ */

#endif /* !__ASM_PROC_DOMAIN_H */
Commit	Line	Data
1da177e4	1	/*
4baa9922	2	* arch/arm/include/asm/domain.h
1da177e4 LT	3	*
	4	* Copyright (C) 1999 Russell King.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#ifndef __ASM_PROC_DOMAIN_H
	11	#define __ASM_PROC_DOMAIN_H
	12
9f97da78 DH	13	#ifndef __ASSEMBLY__
	14	#include <asm/barrier.h>
	15	#endif
	16
1da177e4 LT	17	/*
	18	* Domain numbers
	19	*
	20	* DOMAIN_IO - domain 2 includes all IO only
	21	* DOMAIN_USER - domain 1 includes all user memory only
	22	* DOMAIN_KERNEL - domain 0 includes all kernel memory only
23bdf86a LB	23	*
	24	* The domain numbering depends on whether we support 36 physical
	25	* address for I/O or not. Addresses above the 32 bit boundary can
	26	* only be mapped using supersections and supersections can only
	27	* be set for domain 0. We could just default to DOMAIN_IO as zero,
	28	* but there may be systems with supersection support and no 36-bit
	29	* addressing. In such cases, we want to map system memory with
	30	* supersections to reduce TLB misses and footprint.
	31	*
	32	* 36-bit addressing and supersections are only available on
	33	* CPUs based on ARMv6+ or the Intel XSC3 core.
1da177e4	34	*/
23bdf86a	35	#ifndef CONFIG_IO_36
1da177e4 LT	36	#define DOMAIN_KERNEL 0
	37	#define DOMAIN_TABLE 0
	38	#define DOMAIN_USER 1
	39	#define DOMAIN_IO 2
23bdf86a LB	40	#else
	41	#define DOMAIN_KERNEL 2
	42	#define DOMAIN_TABLE 2
	43	#define DOMAIN_USER 1
	44	#define DOMAIN_IO 0
	45	#endif
1da177e4 LT	46
	47	/*
	48	* Domain types
	49	*/
	50	#define DOMAIN_NOACCESS 0
	51	#define DOMAIN_CLIENT 1
247055aa	52	#ifdef CONFIG_CPU_USE_DOMAINS
1da177e4	53	#define DOMAIN_MANAGER 3
247055aa CM	54	#else
	55	#define DOMAIN_MANAGER 1
	56	#endif
1da177e4 LT	57
	58	#define domain_val(dom,type) ((type) << (2*(dom)))
	59
	60	#ifndef __ASSEMBLY__
002547b4	61
247055aa	62	#ifdef CONFIG_CPU_USE_DOMAINS
82401bf1 RK	63	static inline void set_domain(unsigned val)
	64	{
	65	asm volatile(
	66	"mcr p15, 0, %0, c3, c0 @ set domain"
	67	: : "r" (val));
	68	isb();
	69	}
1da177e4 LT	70
	71	#define modify_domain(dom,type) \
	72	do { \
	73	struct thread_info *thread = current_thread_info(); \
	74	unsigned int domain = thread->cpu_domain; \
	75	domain &= ~domain_val(dom, DOMAIN_MANAGER); \
	76	thread->cpu_domain = domain \| domain_val(dom, type); \
	77	set_domain(thread->cpu_domain); \
	78	} while (0)
	79
002547b4	80	#else
82401bf1 RK	81	static inline void set_domain(unsigned val) { }
82401bf1 RK	82	static inline void modify_domain(unsigned dom, unsigned type) { }
002547b4 RK	83	#endif
002547b4 RK	84
247055aa CM	85	/*
	86	* Generate the T (user) versions of the LDR/STR and related
	87	* instructions (inline assembly)
	88	*/
	89	#ifdef CONFIG_CPU_USE_DOMAINS
4e7682d0	90	#define TUSER(instr) #instr "t"
247055aa	91	#else
4e7682d0	92	#define TUSER(instr) #instr
1da177e4	93	#endif
247055aa CM	94
	95	#else /* __ASSEMBLY__ */
	96
	97	/*
	98	* Generate the T (user) versions of the LDR/STR and related
	99	* instructions
	100	*/
	101	#ifdef CONFIG_CPU_USE_DOMAINS
4e7682d0	102	#define TUSER(instr) instr ## t
247055aa	103	#else
4e7682d0	104	#define TUSER(instr) instr
247055aa CM	105	#endif
	106
	107	#endif /* __ASSEMBLY__ */
	108
	109	#endif /* !__ASM_PROC_DOMAIN_H */