projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| f27ecacc | 1 | /* |
| 4baa9922 | 2 | * arch/arm/include/asm/hardware/gic.h |
| f27ecacc RK |
3 | * |
| 4 | * Copyright (C) 2002 ARM Limited, All Rights Reserved. | |
| 5 | * | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | */ | |
| 10 | #ifndef __ASM_ARM_HARDWARE_GIC_H | |
| 11 | #define __ASM_ARM_HARDWARE_GIC_H | |
| 12 | ||
| 13 | #include <linux/compiler.h> | |
| 14 | ||
| 15 | #define GIC_CPU_CTRL 0x00 | |
| 16 | #define GIC_CPU_PRIMASK 0x04 | |
| 17 | #define GIC_CPU_BINPOINT 0x08 | |
| 18 | #define GIC_CPU_INTACK 0x0c | |
| 19 | #define GIC_CPU_EOI 0x10 | |
| 20 | #define GIC_CPU_RUNNINGPRI 0x14 | |
| 21 | #define GIC_CPU_HIGHPRI 0x18 | |
| 22 | ||
| 23 | #define GIC_DIST_CTRL 0x000 | |
| 24 | #define GIC_DIST_CTR 0x004 | |
| 25 | #define GIC_DIST_ENABLE_SET 0x100 | |
| 26 | #define GIC_DIST_ENABLE_CLEAR 0x180 | |
| 27 | #define GIC_DIST_PENDING_SET 0x200 | |
| 28 | #define GIC_DIST_PENDING_CLEAR 0x280 | |
| 29 | #define GIC_DIST_ACTIVE_BIT 0x300 | |
| 30 | #define GIC_DIST_PRI 0x400 | |
| 31 | #define GIC_DIST_TARGET 0x800 | |
| 32 | #define GIC_DIST_CONFIG 0xc00 | |
| 33 | #define GIC_DIST_SOFTINT 0xf00 | |
| 34 | ||
| 35 | #ifndef __ASSEMBLY__ | |
| ff2e27ae | 36 | extern void __iomem *gic_cpu_base_addr; |
| d7ed36a4 | 37 | extern struct irq_chip gic_arch_extn; |
| ff2e27ae | 38 | |
| b580b899 | 39 | void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *); |
| 38489533 | 40 | void gic_secondary_init(unsigned int); |
| b3a1bde4 | 41 | void gic_cascade_irq(unsigned int gic_nr, unsigned int irq); |
| 82668104 | 42 | void gic_raise_softirq(const struct cpumask *mask, unsigned int irq); |
| e807acbc CY |
43 | |
| 44 | struct gic_chip_data { | |
| 45 | unsigned int irq_offset; | |
| 46 | void __iomem *dist_base; | |
| 47 | void __iomem *cpu_base; | |
| 254056f3 CC |
48 | #ifdef CONFIG_CPU_PM |
| 49 | u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; | |
| 50 | u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; | |
| 51 | u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; | |
| 52 | u32 __percpu *saved_ppi_enable; | |
| 53 | u32 __percpu *saved_ppi_conf; | |
| 54 | #endif | |
| 55 | unsigned int gic_irqs; | |
| e807acbc | 56 | }; |
| f27ecacc RK |
57 | #endif |
| 58 | ||
| 59 | #endif |