projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| ff37f6e5 | 1 | /* |
| 2 | * arch/arm/include/asm/hardware/sp810.h | |
| 3 | * | |
| 4 | * ARM PrimeXsys System Controller SP810 header file | |
| 5 | * | |
| 6 | * Copyright (C) 2009 ST Microelectronics | |
| 10d8935f | 7 | * Viresh Kumar <viresh.linux@gmail.com> |
| ff37f6e5 | 8 | * |
| 9 | * This file is licensed under the terms of the GNU General Public | |
| 10 | * License version 2. This program is licensed "as is" without any | |
| 11 | * warranty of any kind, whether express or implied. | |
| 12 | */ | |
| 13 | ||
| 14 | #ifndef __ASM_ARM_SP810_H | |
| 15 | #define __ASM_ARM_SP810_H | |
| 16 | ||
| 17 | #include <linux/io.h> | |
| 18 | ||
| 19 | /* sysctl registers offset */ | |
| 20 | #define SCCTRL 0x000 | |
| 21 | #define SCSYSSTAT 0x004 | |
| 22 | #define SCIMCTRL 0x008 | |
| 23 | #define SCIMSTAT 0x00C | |
| 24 | #define SCXTALCTRL 0x010 | |
| 25 | #define SCPLLCTRL 0x014 | |
| 26 | #define SCPLLFCTRL 0x018 | |
| 27 | #define SCPERCTRL0 0x01C | |
| 28 | #define SCPERCTRL1 0x020 | |
| 29 | #define SCPEREN 0x024 | |
| 30 | #define SCPERDIS 0x028 | |
| 31 | #define SCPERCLKEN 0x02C | |
| 32 | #define SCPERSTAT 0x030 | |
| 33 | #define SCSYSID0 0xEE0 | |
| 34 | #define SCSYSID1 0xEE4 | |
| 35 | #define SCSYSID2 0xEE8 | |
| 36 | #define SCSYSID3 0xEEC | |
| 37 | #define SCITCR 0xF00 | |
| 38 | #define SCITIR0 0xF04 | |
| 39 | #define SCITIR1 0xF08 | |
| 40 | #define SCITOR 0xF0C | |
| 41 | #define SCCNTCTRL 0xF10 | |
| 42 | #define SCCNTDATA 0xF14 | |
| 43 | #define SCCNTSTEP 0xF18 | |
| 44 | #define SCPERIPHID0 0xFE0 | |
| 45 | #define SCPERIPHID1 0xFE4 | |
| 46 | #define SCPERIPHID2 0xFE8 | |
| 47 | #define SCPERIPHID3 0xFEC | |
| 48 | #define SCPCELLID0 0xFF0 | |
| 49 | #define SCPCELLID1 0xFF4 | |
| 50 | #define SCPCELLID2 0xFF8 | |
| 51 | #define SCPCELLID3 0xFFC | |
| 52 | ||
| baaece22 PM |
53 | #define SCCTRL_TIMEREN0SEL_REFCLK (0 << 15) |
| 54 | #define SCCTRL_TIMEREN0SEL_TIMCLK (1 << 15) | |
| 55 | ||
| 56 | #define SCCTRL_TIMEREN1SEL_REFCLK (0 << 17) | |
| 57 | #define SCCTRL_TIMEREN1SEL_TIMCLK (1 << 17) | |
| 58 | ||
| ff37f6e5 | 59 | static inline void sysctl_soft_reset(void __iomem *base) |
| 60 | { | |
| b8272a61 SH |
61 | /* switch to slow mode */ |
| 62 | writel(0x2, base + SCCTRL); | |
| 63 | ||
| ff37f6e5 | 64 | /* writing any value to SCSYSSTAT reg will reset system */ |
| 65 | writel(0, base + SCSYSSTAT); | |
| 66 | } | |
| 67 | ||
| 68 | #endif /* __ASM_ARM_SP810_H */ |