[deliverable/linux.git] / arch / arm / include / asm / io.h

/*
 *  arch/arm/include/asm/io.h
 *
 *  Copyright (C) 1996-2000 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * Modifications:
 *  16-Sep-1996	RMK	Inlined the inx/outx functions & optimised for both
 *			constant addresses and variable addresses.
 *  04-Dec-1997	RMK	Moved a lot of this stuff to the new architecture
 *			specific IO header files.
 *  27-Mar-1999	PJB	Second parameter of memcpy_toio is const..
 *  04-Apr-1999	PJB	Added check_signature.
 *  12-Dec-1999	RMK	More cleanups
 *  18-Jun-2000 RMK	Removed virt_to_* and friends definitions
 *  05-Oct-2004 BJD     Moved memory string functions to use void __iomem
 */
#ifndef __ASM_ARM_IO_H
#define __ASM_ARM_IO_H

#ifdef __KERNEL__

#include <linux/types.h>
#include <asm/byteorder.h>
#include <asm/memory.h>

/*
 * ISA I/O bus memory addresses are 1:1 with the physical address.
 */
#define isa_virt_to_bus virt_to_phys
#define isa_page_to_bus page_to_phys
#define isa_bus_to_virt phys_to_virt

/*
 * Generic IO read/write.  These perform native-endian accesses.  Note
 * that some architectures will want to re-define __raw_{read,write}w.
 */
extern void __raw_writesb(void __iomem *addr, const void *data, int bytelen);
extern void __raw_writesw(void __iomem *addr, const void *data, int wordlen);
extern void __raw_writesl(void __iomem *addr, const void *data, int longlen);

extern void __raw_readsb(const void __iomem *addr, void *data, int bytelen);
extern void __raw_readsw(const void __iomem *addr, void *data, int wordlen);
extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);

#define __raw_writeb(v,a)	(__chk_io_ptr(a), *(volatile unsigned char __force  *)(a) = (v))
#define __raw_writew(v,a)	(__chk_io_ptr(a), *(volatile unsigned short __force *)(a) = (v))
#define __raw_writel(v,a)	(__chk_io_ptr(a), *(volatile unsigned int __force   *)(a) = (v))

#define __raw_readb(a)		(__chk_io_ptr(a), *(volatile unsigned char __force  *)(a))
#define __raw_readw(a)		(__chk_io_ptr(a), *(volatile unsigned short __force *)(a))
#define __raw_readl(a)		(__chk_io_ptr(a), *(volatile unsigned int __force   *)(a))

/*
 * Architecture ioremap implementation.
 */
#define MT_DEVICE		0
#define MT_DEVICE_NONSHARED	1
#define MT_DEVICE_CACHED	2
#define MT_DEVICE_WC		3
/*
 * types 4 onwards can be found in asm/mach/map.h and are undefined
 * for ioremap
 */

/*
 * __arm_ioremap takes CPU physical address.
 * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
 */
extern void __iomem * __arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
extern void __iomem * __arm_ioremap(unsigned long, size_t, unsigned int);
extern void __iounmap(volatile void __iomem *addr);

/*
 * Bad read/write accesses...
 */
extern void __readwrite_bug(const char *fn);

/*
 * A typesafe __io() helper
 */
static inline void __iomem *__typesafe_io(unsigned long addr)
{
	return (void __iomem *)addr;
}

/*
 * Now, pick up the machine-defined IO definitions
 */
#include <mach/io.h>

/*
 *  IO port access primitives
 *  -------------------------
 *
 * The ARM doesn't have special IO access instructions; all IO is memory
 * mapped.  Note that these are defined to perform little endian accesses
 * only.  Their primary purpose is to access PCI and ISA peripherals.
 *
 * Note that for a big endian machine, this implies that the following
 * big endian mode connectivity is in place, as described by numerous
 * ARM documents:
 *
 *    PCI:  D0-D7   D8-D15 D16-D23 D24-D31
 *    ARM: D24-D31 D16-D23  D8-D15  D0-D7
 *
 * The machine specific io.h include defines __io to translate an "IO"
 * address to a memory address.
 *
 * Note that we prevent GCC re-ordering or caching values in expressions
 * by introducing sequence points into the in*() definitions.  Note that
 * __raw_* do not guarantee this behaviour.
 *
 * The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
 */
#ifdef __io
#define outb(v,p)		__raw_writeb(v,__io(p))
#define outw(v,p)		__raw_writew((__force __u16) \
					cpu_to_le16(v),__io(p))
#define outl(v,p)		__raw_writel((__force __u32) \
					cpu_to_le32(v),__io(p))

#define inb(p)	({ __u8 __v = __raw_readb(__io(p)); __v; })
#define inw(p)	({ __u16 __v = le16_to_cpu((__force __le16) \
			__raw_readw(__io(p))); __v; })
#define inl(p)	({ __u32 __v = le32_to_cpu((__force __le32) \
			__raw_readl(__io(p))); __v; })

#define outsb(p,d,l)		__raw_writesb(__io(p),d,l)
#define outsw(p,d,l)		__raw_writesw(__io(p),d,l)
#define outsl(p,d,l)		__raw_writesl(__io(p),d,l)

#define insb(p,d,l)		__raw_readsb(__io(p),d,l)
#define insw(p,d,l)		__raw_readsw(__io(p),d,l)
#define insl(p,d,l)		__raw_readsl(__io(p),d,l)
#endif

#define outb_p(val,port)	outb((val),(port))
#define outw_p(val,port)	outw((val),(port))
#define outl_p(val,port)	outl((val),(port))
#define inb_p(port)		inb((port))
#define inw_p(port)		inw((port))
#define inl_p(port)		inl((port))

#define outsb_p(port,from,len)	outsb(port,from,len)
#define outsw_p(port,from,len)	outsw(port,from,len)
#define outsl_p(port,from,len)	outsl(port,from,len)
#define insb_p(port,to,len)	insb(port,to,len)
#define insw_p(port,to,len)	insw(port,to,len)
#define insl_p(port,to,len)	insl(port,to,len)

/*
 * String version of IO memory access ops:
 */
extern void _memcpy_fromio(void *, const volatile void __iomem *, size_t);
extern void _memcpy_toio(volatile void __iomem *, const void *, size_t);
extern void _memset_io(volatile void __iomem *, int, size_t);

#define mmiowb()

/*
 *  Memory access primitives
 *  ------------------------
 *
 * These perform PCI memory accesses via an ioremap region.  They don't
 * take an address as such, but a cookie.
 *
 * Again, this are defined to perform little endian accesses.  See the
 * IO port primitives for more information.
 */
#ifdef __mem_pci
#define readb(c) ({ __u8  __v = __raw_readb(__mem_pci(c)); __v; })
#define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \
					__raw_readw(__mem_pci(c))); __v; })
#define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \
					__raw_readl(__mem_pci(c))); __v; })
#define readb_relaxed(addr) readb(addr)
#define readw_relaxed(addr) readw(addr)
#define readl_relaxed(addr) readl(addr)

#define readsb(p,d,l)		__raw_readsb(__mem_pci(p),d,l)
#define readsw(p,d,l)		__raw_readsw(__mem_pci(p),d,l)
#define readsl(p,d,l)		__raw_readsl(__mem_pci(p),d,l)

#define writeb(v,c)		__raw_writeb(v,__mem_pci(c))
#define writew(v,c)		__raw_writew((__force __u16) \
					cpu_to_le16(v),__mem_pci(c))
#define writel(v,c)		__raw_writel((__force __u32) \
					cpu_to_le32(v),__mem_pci(c))

#define writesb(p,d,l)		__raw_writesb(__mem_pci(p),d,l)
#define writesw(p,d,l)		__raw_writesw(__mem_pci(p),d,l)
#define writesl(p,d,l)		__raw_writesl(__mem_pci(p),d,l)

#define memset_io(c,v,l)	_memset_io(__mem_pci(c),(v),(l))
#define memcpy_fromio(a,c,l)	_memcpy_fromio((a),__mem_pci(c),(l))
#define memcpy_toio(c,a,l)	_memcpy_toio(__mem_pci(c),(a),(l))

#elif !defined(readb)

#define readb(c)			(__readwrite_bug("readb"),0)
#define readw(c)			(__readwrite_bug("readw"),0)
#define readl(c)			(__readwrite_bug("readl"),0)
#define writeb(v,c)			__readwrite_bug("writeb")
#define writew(v,c)			__readwrite_bug("writew")
#define writel(v,c)			__readwrite_bug("writel")

#define check_signature(io,sig,len)	(0)

#endif	/* __mem_pci */

/*
 * ioremap and friends.
 *
 * ioremap takes a PCI memory address, as specified in
 * Documentation/IO-mapping.txt.
 *
 */
#ifndef __arch_ioremap
#define ioremap(cookie,size)		__arm_ioremap(cookie, size, MT_DEVICE)
#define ioremap_nocache(cookie,size)	__arm_ioremap(cookie, size, MT_DEVICE)
#define ioremap_cached(cookie,size)	__arm_ioremap(cookie, size, MT_DEVICE_CACHED)
#define ioremap_wc(cookie,size)		__arm_ioremap(cookie, size, MT_DEVICE_WC)
#define iounmap(cookie)			__iounmap(cookie)
#else
#define ioremap(cookie,size)		__arch_ioremap((cookie), (size), MT_DEVICE)
#define ioremap_nocache(cookie,size)	__arch_ioremap((cookie), (size), MT_DEVICE)
#define ioremap_cached(cookie,size)	__arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
#define ioremap_wc(cookie,size)		__arch_ioremap((cookie), (size), MT_DEVICE_WC)
#define iounmap(cookie)			__arch_iounmap(cookie)
#endif

/*
 * io{read,write}{8,16,32} macros
 */
#ifndef ioread8
#define ioread8(p)	({ unsigned int __v = __raw_readb(p); __v; })
#define ioread16(p)	({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __v; })
#define ioread32(p)	({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __v; })

#define iowrite8(v,p)	__raw_writeb(v, p)
#define iowrite16(v,p)	__raw_writew((__force __u16)cpu_to_le16(v), p)
#define iowrite32(v,p)	__raw_writel((__force __u32)cpu_to_le32(v), p)

#define ioread8_rep(p,d,c)	__raw_readsb(p,d,c)
#define ioread16_rep(p,d,c)	__raw_readsw(p,d,c)
#define ioread32_rep(p,d,c)	__raw_readsl(p,d,c)

#define iowrite8_rep(p,s,c)	__raw_writesb(p,s,c)
#define iowrite16_rep(p,s,c)	__raw_writesw(p,s,c)
#define iowrite32_rep(p,s,c)	__raw_writesl(p,s,c)

extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
extern void ioport_unmap(void __iomem *addr);
#endif

struct pci_dev;

extern void __iomem *pci_iomap(struct pci_dev *dev, int bar, unsigned long maxlen);
extern void pci_iounmap(struct pci_dev *dev, void __iomem *addr);

/*
 * can the hardware map this into one segment or not, given no other
 * constraints.
 */
#define BIOVEC_MERGEABLE(vec1, vec2)	\
	((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))

#ifdef CONFIG_MMU
#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
extern int valid_phys_addr_range(unsigned long addr, size_t size);
extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
#endif

/*
 * Convert a physical pointer to a virtual kernel pointer for /dev/mem
 * access
 */
#define xlate_dev_mem_ptr(p)	__va(p)

/*
 * Convert a virtual cached pointer to an uncached pointer
 */
#define xlate_dev_kmem_ptr(p)	p

/*
 * Register ISA memory and port locations for glibc iopl/inb/outb
 * emulation.
 */
extern void register_isa_ports(unsigned int mmio, unsigned int io,
			       unsigned int io_shift);

#endif	/* __KERNEL__ */
#endif	/* __ASM_ARM_IO_H */
Commit	Line	Data
1da177e4	1	/*
4baa9922	2	* arch/arm/include/asm/io.h
1da177e4 LT	3	*
	4	* Copyright (C) 1996-2000 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Modifications:
	11	* 16-Sep-1996 RMK Inlined the inx/outx functions & optimised for both
	12	* constant addresses and variable addresses.
	13	* 04-Dec-1997 RMK Moved a lot of this stuff to the new architecture
	14	* specific IO header files.
	15	* 27-Mar-1999 PJB Second parameter of memcpy_toio is const..
	16	* 04-Apr-1999 PJB Added check_signature.
	17	* 12-Dec-1999 RMK More cleanups
	18	* 18-Jun-2000 RMK Removed virt_to_* and friends definitions
	19	* 05-Oct-2004 BJD Moved memory string functions to use void __iomem
	20	*/
	21	#ifndef __ASM_ARM_IO_H
	22	#define __ASM_ARM_IO_H
	23
	24	#ifdef __KERNEL__
	25
	26	#include <linux/types.h>
	27	#include <asm/byteorder.h>
	28	#include <asm/memory.h>
1da177e4 LT	29
	30	/*
	31	* ISA I/O bus memory addresses are 1:1 with the physical address.
	32	*/
	33	#define isa_virt_to_bus virt_to_phys
	34	#define isa_page_to_bus page_to_phys
	35	#define isa_bus_to_virt phys_to_virt
	36
	37	/*
	38	* Generic IO read/write. These perform native-endian accesses. Note
	39	* that some architectures will want to re-define __raw_{read,write}w.
	40	*/
	41	extern void __raw_writesb(void __iomem addr, const void data, int bytelen);
	42	extern void __raw_writesw(void __iomem addr, const void data, int wordlen);
	43	extern void __raw_writesl(void __iomem addr, const void data, int longlen);
	44
a0d95af5 DS	45	extern void __raw_readsb(const void __iomem addr, void data, int bytelen);
	46	extern void __raw_readsw(const void __iomem addr, void data, int wordlen);
	47	extern void __raw_readsl(const void __iomem addr, void data, int longlen);
1da177e4 LT	48
	49	#define __raw_writeb(v,a) (__chk_io_ptr(a), (volatile unsigned char __force )(a) = (v))
	50	#define __raw_writew(v,a) (__chk_io_ptr(a), (volatile unsigned short __force )(a) = (v))
	51	#define __raw_writel(v,a) (__chk_io_ptr(a), (volatile unsigned int __force )(a) = (v))
	52
	53	#define __raw_readb(a) (__chk_io_ptr(a), (volatile unsigned char __force )(a))
	54	#define __raw_readw(a) (__chk_io_ptr(a), (volatile unsigned short __force )(a))
	55	#define __raw_readl(a) (__chk_io_ptr(a), (volatile unsigned int __force )(a))
	56
67a1901f RK	57	/*
	58	* Architecture ioremap implementation.
	59	*/
3603ab2b RK	60	#define MT_DEVICE 0
	61	#define MT_DEVICE_NONSHARED 1
	62	#define MT_DEVICE_CACHED 2
db5b7169	63	#define MT_DEVICE_WC 3
3603ab2b	64	/*
db5b7169	65	* types 4 onwards can be found in asm/mach/map.h and are undefined
3603ab2b RK	66	* for ioremap
	67	*/
	68
	69	/*
	70	* __arm_ioremap takes CPU physical address.
	71	* __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
	72	*/
	73	extern void __iomem * __arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
	74	extern void __iomem * __arm_ioremap(unsigned long, size_t, unsigned int);
1622605c	75	extern void __iounmap(volatile void __iomem *addr);
67a1901f	76
1da177e4 LT	77	/*
	78	* Bad read/write accesses...
	79	*/
	80	extern void __readwrite_bug(const char *fn);
	81
0560cf5a RK	82	/*
	83	* A typesafe __io() helper
	84	*/
	85	static inline void __iomem *__typesafe_io(unsigned long addr)
	86	{
	87	return (void __iomem *)addr;
	88	}
	89
1da177e4 LT	90	/*
	91	* Now, pick up the machine-defined IO definitions
	92	*/
a09e64fb	93	#include <mach/io.h>
1da177e4	94
1da177e4 LT	95	/*
	96	* IO port access primitives
	97	* -------------------------
	98	*
	99	* The ARM doesn't have special IO access instructions; all IO is memory
	100	* mapped. Note that these are defined to perform little endian accesses
	101	* only. Their primary purpose is to access PCI and ISA peripherals.
	102	*
	103	* Note that for a big endian machine, this implies that the following
c79ebfa8	104	* big endian mode connectivity is in place, as described by numerous
1da177e4 LT	105	* ARM documents:
	106	*
	107	* PCI: D0-D7 D8-D15 D16-D23 D24-D31
	108	* ARM: D24-D31 D16-D23 D8-D15 D0-D7
	109	*
	110	* The machine specific io.h include defines __io to translate an "IO"
	111	* address to a memory address.
	112	*
	113	* Note that we prevent GCC re-ordering or caching values in expressions
	114	* by introducing sequence points into the in*() definitions. Note that
	115	* __raw_* do not guarantee this behaviour.
	116	*
	117	* The {in,out}[bwl] macros are for emulating x86-style PCI/ISA IO space.
	118	*/
	119	#ifdef __io
	120	#define outb(v,p) __raw_writeb(v,__io(p))
05f9869b OK	121	#define outw(v,p) __raw_writew((__force __u16) \
	122	cpu_to_le16(v),__io(p))
	123	#define outl(v,p) __raw_writel((__force __u32) \
	124	cpu_to_le32(v),__io(p))
1da177e4	125
05f9869b OK	126	#define inb(p) ({ __u8 __v = __raw_readb(__io(p)); __v; })
	127	#define inw(p) ({ __u16 __v = le16_to_cpu((__force __le16) \
	128	__raw_readw(__io(p))); __v; })
	129	#define inl(p) ({ __u32 __v = le32_to_cpu((__force __le32) \
	130	__raw_readl(__io(p))); __v; })
1da177e4 LT	131
	132	#define outsb(p,d,l) __raw_writesb(__io(p),d,l)
	133	#define outsw(p,d,l) __raw_writesw(__io(p),d,l)
	134	#define outsl(p,d,l) __raw_writesl(__io(p),d,l)
	135
	136	#define insb(p,d,l) __raw_readsb(__io(p),d,l)
	137	#define insw(p,d,l) __raw_readsw(__io(p),d,l)
	138	#define insl(p,d,l) __raw_readsl(__io(p),d,l)
	139	#endif
	140
	141	#define outb_p(val,port) outb((val),(port))
	142	#define outw_p(val,port) outw((val),(port))
	143	#define outl_p(val,port) outl((val),(port))
	144	#define inb_p(port) inb((port))
	145	#define inw_p(port) inw((port))
	146	#define inl_p(port) inl((port))
	147
	148	#define outsb_p(port,from,len) outsb(port,from,len)
	149	#define outsw_p(port,from,len) outsw(port,from,len)
	150	#define outsl_p(port,from,len) outsl(port,from,len)
	151	#define insb_p(port,to,len) insb(port,to,len)
	152	#define insw_p(port,to,len) insw(port,to,len)
	153	#define insl_p(port,to,len) insl(port,to,len)
	154
	155	/*
	156	* String version of IO memory access ops:
	157	*/
d2f60748 RK	158	extern void _memcpy_fromio(void , const volatile void __iomem , size_t);
	159	extern void _memcpy_toio(volatile void __iomem , const void , size_t);
	160	extern void _memset_io(volatile void __iomem *, int, size_t);
1da177e4 LT	161
	162	#define mmiowb()
	163
	164	/*
	165	* Memory access primitives
	166	* ------------------------
	167	*
	168	* These perform PCI memory accesses via an ioremap region. They don't
	169	* take an address as such, but a cookie.
	170	*
	171	* Again, this are defined to perform little endian accesses. See the
	172	* IO port primitives for more information.
	173	*/
	174	#ifdef __mem_pci
05f9869b OK	175	#define readb(c) ({ __u8 __v = __raw_readb(__mem_pci(c)); __v; })
	176	#define readw(c) ({ __u16 __v = le16_to_cpu((__force __le16) \
	177	__raw_readw(__mem_pci(c))); __v; })
	178	#define readl(c) ({ __u32 __v = le32_to_cpu((__force __le32) \
	179	__raw_readl(__mem_pci(c))); __v; })
1da177e4 LT	180	#define readb_relaxed(addr) readb(addr)
	181	#define readw_relaxed(addr) readw(addr)
	182	#define readl_relaxed(addr) readl(addr)
	183
	184	#define readsb(p,d,l) __raw_readsb(__mem_pci(p),d,l)
	185	#define readsw(p,d,l) __raw_readsw(__mem_pci(p),d,l)
	186	#define readsl(p,d,l) __raw_readsl(__mem_pci(p),d,l)
	187
	188	#define writeb(v,c) __raw_writeb(v,__mem_pci(c))
05f9869b OK	189	#define writew(v,c) __raw_writew((__force __u16) \
	190	cpu_to_le16(v),__mem_pci(c))
	191	#define writel(v,c) __raw_writel((__force __u32) \
	192	cpu_to_le32(v),__mem_pci(c))
1da177e4 LT	193
	194	#define writesb(p,d,l) __raw_writesb(__mem_pci(p),d,l)
	195	#define writesw(p,d,l) __raw_writesw(__mem_pci(p),d,l)
	196	#define writesl(p,d,l) __raw_writesl(__mem_pci(p),d,l)
	197
	198	#define memset_io(c,v,l) _memset_io(__mem_pci(c),(v),(l))
	199	#define memcpy_fromio(a,c,l) _memcpy_fromio((a),__mem_pci(c),(l))
	200	#define memcpy_toio(c,a,l) _memcpy_toio(__mem_pci(c),(a),(l))
	201
1da177e4 LT	202	#elif !defined(readb)
	203
	204	#define readb(c) (__readwrite_bug("readb"),0)
	205	#define readw(c) (__readwrite_bug("readw"),0)
	206	#define readl(c) (__readwrite_bug("readl"),0)
	207	#define writeb(v,c) __readwrite_bug("writeb")
	208	#define writew(v,c) __readwrite_bug("writew")
	209	#define writel(v,c) __readwrite_bug("writel")
	210
1da177e4 LT	211	#define check_signature(io,sig,len) (0)
	212
	213	#endif /* __mem_pci */
	214
1da177e4 LT	215	/*
	216	* ioremap and friends.
	217	*
	218	* ioremap takes a PCI memory address, as specified in
	219	* Documentation/IO-mapping.txt.
9d4ae727	220	*
1da177e4	221	*/
1da177e4	222	#ifndef __arch_ioremap
3603ab2b RK	223	#define ioremap(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE)
	224	#define ioremap_nocache(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE)
	225	#define ioremap_cached(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_CACHED)
1ad77a87	226	#define ioremap_wc(cookie,size) __arm_ioremap(cookie, size, MT_DEVICE_WC)
1da177e4 LT	227	#define iounmap(cookie) __iounmap(cookie)
1da177e4 LT	228	#else
3603ab2b RK	229	#define ioremap(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
	230	#define ioremap_nocache(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE)
	231	#define ioremap_cached(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
1ad77a87	232	#define ioremap_wc(cookie,size) __arch_ioremap((cookie), (size), MT_DEVICE_WC)
1da177e4 LT	233	#define iounmap(cookie) __arch_iounmap(cookie)
	234	#endif
	235
09f0551d RK	236	/*
	237	* io{read,write}{8,16,32} macros
	238	*/
7533fca8	239	#ifndef ioread8
09f0551d	240	#define ioread8(p) ({ unsigned int __v = __raw_readb(p); __v; })
c6b44e50 AV	241	#define ioread16(p) ({ unsigned int __v = le16_to_cpu((__force __le16)__raw_readw(p)); __v; })
c6b44e50 AV	242	#define ioread32(p) ({ unsigned int __v = le32_to_cpu((__force __le32)__raw_readl(p)); __v; })
09f0551d RK	243
09f0551d RK	244	#define iowrite8(v,p) __raw_writeb(v, p)
c6b44e50 AV	245	#define iowrite16(v,p) __raw_writew((__force __u16)cpu_to_le16(v), p)
c6b44e50 AV	246	#define iowrite32(v,p) __raw_writel((__force __u32)cpu_to_le32(v), p)
09f0551d RK	247
	248	#define ioread8_rep(p,d,c) __raw_readsb(p,d,c)
	249	#define ioread16_rep(p,d,c) __raw_readsw(p,d,c)
	250	#define ioread32_rep(p,d,c) __raw_readsl(p,d,c)
	251
	252	#define iowrite8_rep(p,s,c) __raw_writesb(p,s,c)
	253	#define iowrite16_rep(p,s,c) __raw_writesw(p,s,c)
	254	#define iowrite32_rep(p,s,c) __raw_writesl(p,s,c)
	255
	256	extern void __iomem *ioport_map(unsigned long port, unsigned int nr);
	257	extern void ioport_unmap(void __iomem *addr);
7533fca8	258	#endif
09f0551d RK	259
	260	struct pci_dev;
	261
	262	extern void __iomem pci_iomap(struct pci_dev dev, int bar, unsigned long maxlen);
	263	extern void pci_iounmap(struct pci_dev dev, void __iomem addr);
	264
1da177e4 LT	265	/*
	266	* can the hardware map this into one segment or not, given no other
	267	* constraints.
	268	*/
	269	#define BIOVEC_MERGEABLE(vec1, vec2) \
	270	((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
	271
95ba71f7	272	#ifdef CONFIG_MMU
51635ad2 LB	273	#define ARCH_HAS_VALID_PHYS_ADDR_RANGE
	274	extern int valid_phys_addr_range(unsigned long addr, size_t size);
	275	extern int valid_mmap_phys_addr_range(unsigned long pfn, size_t size);
95ba71f7	276	#endif
51635ad2	277
1da177e4 LT	278	/*
	279	* Convert a physical pointer to a virtual kernel pointer for /dev/mem
	280	* access
	281	*/
	282	#define xlate_dev_mem_ptr(p) __va(p)
	283
	284	/*
	285	* Convert a virtual cached pointer to an uncached pointer
	286	*/
	287	#define xlate_dev_kmem_ptr(p) p
	288
1645f20b RK	289	/*
	290	* Register ISA memory and port locations for glibc iopl/inb/outb
	291	* emulation.
	292	*/
	293	extern void register_isa_ports(unsigned int mmio, unsigned int io,
	294	unsigned int io_shift);
	295
1da177e4 LT	296	#endif /* __KERNEL__ */
1da177e4 LT	297	#endif /* __ASM_ARM_IO_H */