[deliverable/linux.git] / arch / arm / include / asm / pgtable-3level.h

/*
 * arch/arm/include/asm/pgtable-3level.h
 *
 * Copyright (C) 2011 ARM Ltd.
 * Author: Catalin Marinas <catalin.marinas@arm.com>
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 */
#ifndef _ASM_PGTABLE_3LEVEL_H
#define _ASM_PGTABLE_3LEVEL_H

/*
 * With LPAE, there are 3 levels of page tables. Each level has 512 entries of
 * 8 bytes each, occupying a 4K page. The first level table covers a range of
 * 512GB, each entry representing 1GB. Since we are limited to 4GB input
 * address range, only 4 entries in the PGD are used.
 *
 * There are enough spare bits in a page table entry for the kernel specific
 * state.
 */
#define PTRS_PER_PTE		512
#define PTRS_PER_PMD		512
#define PTRS_PER_PGD		4

#define PTE_HWTABLE_PTRS	(PTRS_PER_PTE)
#define PTE_HWTABLE_OFF		(0)
#define PTE_HWTABLE_SIZE	(PTRS_PER_PTE * sizeof(u64))

/*
 * PGDIR_SHIFT determines the size a top-level page table entry can map.
 */
#define PGDIR_SHIFT		30

/*
 * PMD_SHIFT determines the size a middle-level page table entry can map.
 */
#define PMD_SHIFT		21

#define PMD_SIZE		(1UL << PMD_SHIFT)
#define PMD_MASK		(~(PMD_SIZE-1))
#define PGDIR_SIZE		(1UL << PGDIR_SHIFT)
#define PGDIR_MASK		(~(PGDIR_SIZE-1))

/*
 * section address mask and size definitions.
 */
#define SECTION_SHIFT		21
#define SECTION_SIZE		(1UL << SECTION_SHIFT)
#define SECTION_MASK		(~(SECTION_SIZE-1))

#define USER_PTRS_PER_PGD	(PAGE_OFFSET / PGDIR_SIZE)

/*
 * Hugetlb definitions.
 */
#define HPAGE_SHIFT		PMD_SHIFT
#define HPAGE_SIZE		(_AC(1, UL) << HPAGE_SHIFT)
#define HPAGE_MASK		(~(HPAGE_SIZE - 1))
#define HUGETLB_PAGE_ORDER	(HPAGE_SHIFT - PAGE_SHIFT)

/*
 * "Linux" PTE definitions for LPAE.
 *
 * These bits overlap with the hardware bits but the naming is preserved for
 * consistency with the classic page table format.
 */
#define L_PTE_VALID		(_AT(pteval_t, 1) << 0)		/* Valid */
#define L_PTE_PRESENT		(_AT(pteval_t, 3) << 0)		/* Present */
#define L_PTE_FILE		(_AT(pteval_t, 1) << 2)		/* only when !PRESENT */
#define L_PTE_USER		(_AT(pteval_t, 1) << 6)		/* AP[1] */
#define L_PTE_RDONLY		(_AT(pteval_t, 1) << 7)		/* AP[2] */
#define L_PTE_SHARED		(_AT(pteval_t, 3) << 8)		/* SH[1:0], inner shareable */
#define L_PTE_YOUNG		(_AT(pteval_t, 1) << 10)	/* AF */
#define L_PTE_XN		(_AT(pteval_t, 1) << 54)	/* XN */
#define L_PTE_DIRTY		(_AT(pteval_t, 1) << 55)	/* unused */
#define L_PTE_SPECIAL		(_AT(pteval_t, 1) << 56)	/* unused */
#define L_PTE_NONE		(_AT(pteval_t, 1) << 57)	/* PROT_NONE */

#define PMD_SECT_VALID		(_AT(pmdval_t, 1) << 0)
#define PMD_SECT_DIRTY		(_AT(pmdval_t, 1) << 55)
#define PMD_SECT_SPLITTING	(_AT(pmdval_t, 1) << 56)
#define PMD_SECT_NONE		(_AT(pmdval_t, 1) << 57)

/*
 * To be used in assembly code with the upper page attributes.
 */
#define L_PTE_XN_HIGH		(1 << (54 - 32))
#define L_PTE_DIRTY_HIGH	(1 << (55 - 32))

/*
 * AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
 */
#define L_PTE_MT_UNCACHED	(_AT(pteval_t, 0) << 2)	/* strongly ordered */
#define L_PTE_MT_BUFFERABLE	(_AT(pteval_t, 1) << 2)	/* normal non-cacheable */
#define L_PTE_MT_WRITETHROUGH	(_AT(pteval_t, 2) << 2)	/* normal inner write-through */
#define L_PTE_MT_WRITEBACK	(_AT(pteval_t, 3) << 2)	/* normal inner write-back */
#define L_PTE_MT_WRITEALLOC	(_AT(pteval_t, 7) << 2)	/* normal inner write-alloc */
#define L_PTE_MT_DEV_SHARED	(_AT(pteval_t, 4) << 2)	/* device */
#define L_PTE_MT_DEV_NONSHARED	(_AT(pteval_t, 4) << 2)	/* device */
#define L_PTE_MT_DEV_WC		(_AT(pteval_t, 1) << 2)	/* normal non-cacheable */
#define L_PTE_MT_DEV_CACHED	(_AT(pteval_t, 3) << 2)	/* normal inner write-back */
#define L_PTE_MT_MASK		(_AT(pteval_t, 7) << 2)

/*
 * Software PGD flags.
 */
#define L_PGD_SWAPPER		(_AT(pgdval_t, 1) << 55)	/* swapper_pg_dir entry */

/*
 * 2nd stage PTE definitions for LPAE.
 */
#define L_PTE_S2_MT_UNCACHED	 (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
#define L_PTE_S2_MT_WRITEBACK	 (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
#define L_PTE_S2_RDONLY		 (_AT(pteval_t, 1) << 6)   /* HAP[1]   */
#define L_PTE_S2_RDWR		 (_AT(pteval_t, 3) << 6)   /* HAP[2:1] */

/*
 * Hyp-mode PL2 PTE definitions for LPAE.
 */
#define L_PTE_HYP		L_PTE_USER

#ifndef __ASSEMBLY__

#define pud_none(pud)		(!pud_val(pud))
#define pud_bad(pud)		(!(pud_val(pud) & 2))
#define pud_present(pud)	(pud_val(pud))
#define pmd_table(pmd)		((pmd_val(pmd) & PMD_TYPE_MASK) == \
						 PMD_TYPE_TABLE)
#define pmd_sect(pmd)		((pmd_val(pmd) & PMD_TYPE_MASK) == \
						 PMD_TYPE_SECT)

#define pud_clear(pudp)			\
	do {				\
		*pudp = __pud(0);	\
		clean_pmd_entry(pudp);	\
	} while (0)

#define set_pud(pudp, pud)		\
	do {				\
		*pudp = pud;		\
		flush_pmd_entry(pudp);	\
	} while (0)

static inline pmd_t *pud_page_vaddr(pud_t pud)
{
	return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
}

/* Find an entry in the second-level page table.. */
#define pmd_index(addr)		(((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
static inline pmd_t *pmd_offset(pud_t *pud, unsigned long addr)
{
	return (pmd_t *)pud_page_vaddr(*pud) + pmd_index(addr);
}

#define pmd_bad(pmd)		(!(pmd_val(pmd) & 2))

#define copy_pmd(pmdpd,pmdps)		\
	do {				\
		*pmdpd = *pmdps;	\
		flush_pmd_entry(pmdpd);	\
	} while (0)

#define pmd_clear(pmdp)			\
	do {				\
		*pmdp = __pmd(0);	\
		clean_pmd_entry(pmdp);	\
	} while (0)

/*
 * For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
 * that are written to a page table but not for ptes created with mk_pte.
 *
 * In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
 * hugetlb_cow, where it is compared with an entry in a page table.
 * This comparison test fails erroneously leading ultimately to a memory leak.
 *
 * To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
 * present before running the comparison.
 */
#define __HAVE_ARCH_PTE_SAME
#define pte_same(pte_a,pte_b)	((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG	\
					: pte_val(pte_a))				\
				== (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG	\
					: pte_val(pte_b)))

#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)|(ext)))

#define pte_huge(pte)		(pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
#define pte_mkhuge(pte)		(__pte(pte_val(pte) & ~PTE_TABLE_BIT))

#define pmd_young(pmd)		(pmd_val(pmd) & PMD_SECT_AF)

#define __HAVE_ARCH_PMD_WRITE
#define pmd_write(pmd)		(!(pmd_val(pmd) & PMD_SECT_RDONLY))

#ifdef CONFIG_TRANSPARENT_HUGEPAGE
#define pmd_trans_huge(pmd)	(pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
#define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING)
#endif

#define PMD_BIT_FUNC(fn,op) \
static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }

PMD_BIT_FUNC(wrprotect,	|= PMD_SECT_RDONLY);
PMD_BIT_FUNC(mkold,	&= ~PMD_SECT_AF);
PMD_BIT_FUNC(mksplitting, |= PMD_SECT_SPLITTING);
PMD_BIT_FUNC(mkwrite,   &= ~PMD_SECT_RDONLY);
PMD_BIT_FUNC(mkdirty,   |= PMD_SECT_DIRTY);
PMD_BIT_FUNC(mkyoung,   |= PMD_SECT_AF);

#define pmd_mkhuge(pmd)		(__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))

#define pmd_pfn(pmd)		(((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
#define pfn_pmd(pfn,prot)	(__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) | pgprot_val(prot)))
#define mk_pmd(page,prot)	pfn_pmd(page_to_pfn(page),prot)

/* represent a notpresent pmd by zero, this is used by pmdp_invalidate */
#define pmd_mknotpresent(pmd)	(__pmd(0))

static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
{
	const pmdval_t mask = PMD_SECT_USER | PMD_SECT_XN | PMD_SECT_RDONLY |
				PMD_SECT_VALID | PMD_SECT_NONE;
	pmd_val(pmd) = (pmd_val(pmd) & ~mask) | (pgprot_val(newprot) & mask);
	return pmd;
}

static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
			      pmd_t *pmdp, pmd_t pmd)
{
	BUG_ON(addr >= TASK_SIZE);

	/* create a faulting entry if PROT_NONE protected */
	if (pmd_val(pmd) & PMD_SECT_NONE)
		pmd_val(pmd) &= ~PMD_SECT_VALID;

	*pmdp = __pmd(pmd_val(pmd) | PMD_SECT_nG);
	flush_pmd_entry(pmdp);
}

static inline int has_transparent_hugepage(void)
{
	return 1;
}

#endif /* __ASSEMBLY__ */

#endif /* _ASM_PGTABLE_3LEVEL_H */
Commit	Line	Data
dcfdae04 CM	1	/*
	2	* arch/arm/include/asm/pgtable-3level.h
	3	*
	4	* Copyright (C) 2011 ARM Ltd.
	5	* Author: Catalin Marinas <catalin.marinas@arm.com>
	6	*
	7	* This program is free software; you can redistribute it and/or modify
	8	* it under the terms of the GNU General Public License version 2 as
	9	* published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; if not, write to the Free Software
	18	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	19	*/
	20	#ifndef _ASM_PGTABLE_3LEVEL_H
	21	#define _ASM_PGTABLE_3LEVEL_H
	22
	23	/*
	24	* With LPAE, there are 3 levels of page tables. Each level has 512 entries of
	25	* 8 bytes each, occupying a 4K page. The first level table covers a range of
	26	* 512GB, each entry representing 1GB. Since we are limited to 4GB input
	27	* address range, only 4 entries in the PGD are used.
	28	*
	29	* There are enough spare bits in a page table entry for the kernel specific
	30	* state.
	31	*/
	32	#define PTRS_PER_PTE 512
	33	#define PTRS_PER_PMD 512
	34	#define PTRS_PER_PGD 4
	35
	36	#define PTE_HWTABLE_PTRS (PTRS_PER_PTE)
	37	#define PTE_HWTABLE_OFF (0)
	38	#define PTE_HWTABLE_SIZE (PTRS_PER_PTE * sizeof(u64))
	39
	40	/*
	41	* PGDIR_SHIFT determines the size a top-level page table entry can map.
	42	*/
	43	#define PGDIR_SHIFT 30
	44
	45	/*
	46	* PMD_SHIFT determines the size a middle-level page table entry can map.
	47	*/
	48	#define PMD_SHIFT 21
	49
	50	#define PMD_SIZE (1UL << PMD_SHIFT)
	51	#define PMD_MASK (~(PMD_SIZE-1))
	52	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	53	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	54
	55	/*
	56	* section address mask and size definitions.
	57	*/
	58	#define SECTION_SHIFT 21
	59	#define SECTION_SIZE (1UL << SECTION_SHIFT)
	60	#define SECTION_MASK (~(SECTION_SIZE-1))
	61
	62	#define USER_PTRS_PER_PGD (PAGE_OFFSET / PGDIR_SIZE)
	63
1355e2a6 CM	64	/*
	65	* Hugetlb definitions.
	66	*/
	67	#define HPAGE_SHIFT PMD_SHIFT
	68	#define HPAGE_SIZE (_AC(1, UL) << HPAGE_SHIFT)
	69	#define HPAGE_MASK (~(HPAGE_SIZE - 1))
	70	#define HUGETLB_PAGE_ORDER (HPAGE_SHIFT - PAGE_SHIFT)
	71
dcfdae04 CM	72	/*
	73	* "Linux" PTE definitions for LPAE.
	74	*
	75	* These bits overlap with the hardware bits but the naming is preserved for
	76	* consistency with the classic page table format.
	77	*/
dbf62d50 WD	78	#define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */
dbf62d50 WD	79	#define L_PTE_PRESENT (_AT(pteval_t, 3) << 0) /* Present */
dcfdae04	80	#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */
dcfdae04 CM	81	#define L_PTE_USER (_AT(pteval_t, 1) << 6) /* AP[1] */
	82	#define L_PTE_RDONLY (_AT(pteval_t, 1) << 7) /* AP[2] */
	83	#define L_PTE_SHARED (_AT(pteval_t, 3) << 8) /* SH[1:0], inner shareable */
	84	#define L_PTE_YOUNG (_AT(pteval_t, 1) << 10) /* AF */
	85	#define L_PTE_XN (_AT(pteval_t, 1) << 54) /* XN */
	86	#define L_PTE_DIRTY (_AT(pteval_t, 1) << 55) /* unused */
	87	#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 56) /* unused */
26ffd0d4	88	#define L_PTE_NONE (_AT(pteval_t, 1) << 57) /* PROT_NONE */
dcfdae04	89
8d962507 CM	90	#define PMD_SECT_VALID (_AT(pmdval_t, 1) << 0)
	91	#define PMD_SECT_DIRTY (_AT(pmdval_t, 1) << 55)
	92	#define PMD_SECT_SPLITTING (_AT(pmdval_t, 1) << 56)
	93	#define PMD_SECT_NONE (_AT(pmdval_t, 1) << 57)
	94
dcfdae04 CM	95	/*
	96	* To be used in assembly code with the upper page attributes.
	97	*/
	98	#define L_PTE_XN_HIGH (1 << (54 - 32))
	99	#define L_PTE_DIRTY_HIGH (1 << (55 - 32))
	100
	101	/*
	102	* AttrIndx[2:0] encoding (mapping attributes defined in the MAIR* registers).
	103	*/
	104	#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0) << 2) /* strongly ordered */
	105	#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
	106	#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 2) << 2) /* normal inner write-through */
	107	#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 3) << 2) /* normal inner write-back */
	108	#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 7) << 2) /* normal inner write-alloc */
	109	#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 4) << 2) /* device */
	110	#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 4) << 2) /* device */
	111	#define L_PTE_MT_DEV_WC (_AT(pteval_t, 1) << 2) /* normal non-cacheable */
	112	#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 3) << 2) /* normal inner write-back */
	113	#define L_PTE_MT_MASK (_AT(pteval_t, 7) << 2)
	114
da028779 CM	115	/*
	116	* Software PGD flags.
	117	*/
	118	#define L_PGD_SWAPPER (_AT(pgdval_t, 1) << 55) /* swapper_pg_dir entry */
	119
cc577c26 CD	120	/*
	121	* 2nd stage PTE definitions for LPAE.
	122	*/
	123	#define L_PTE_S2_MT_UNCACHED (_AT(pteval_t, 0x5) << 2) /* MemAttr[3:0] */
	124	#define L_PTE_S2_MT_WRITETHROUGH (_AT(pteval_t, 0xa) << 2) /* MemAttr[3:0] */
	125	#define L_PTE_S2_MT_WRITEBACK (_AT(pteval_t, 0xf) << 2) /* MemAttr[3:0] */
	126	#define L_PTE_S2_RDONLY (_AT(pteval_t, 1) << 6) /* HAP[1] */
865499ea	127	#define L_PTE_S2_RDWR (_AT(pteval_t, 3) << 6) /* HAP[2:1] */
cc577c26 CD	128
	129	/*
	130	* Hyp-mode PL2 PTE definitions for LPAE.
	131	*/
	132	#define L_PTE_HYP L_PTE_USER
	133
da028779 CM	134	#ifndef __ASSEMBLY__
	135
	136	#define pud_none(pud) (!pud_val(pud))
	137	#define pud_bad(pud) (!(pud_val(pud) & 2))
	138	#define pud_present(pud) (pud_val(pud))
cc577c26 CD	139	#define pmd_table(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
	140	PMD_TYPE_TABLE)
	141	#define pmd_sect(pmd) ((pmd_val(pmd) & PMD_TYPE_MASK) == \
	142	PMD_TYPE_SECT)
da028779 CM	143
	144	#define pud_clear(pudp) \
	145	do { \
	146	*pudp = __pud(0); \
	147	clean_pmd_entry(pudp); \
	148	} while (0)
	149
	150	#define set_pud(pudp, pud) \
	151	do { \
	152	*pudp = pud; \
	153	flush_pmd_entry(pudp); \
	154	} while (0)
	155
	156	static inline pmd_t *pud_page_vaddr(pud_t pud)
	157	{
	158	return __va(pud_val(pud) & PHYS_MASK & (s32)PAGE_MASK);
	159	}
	160
	161	/* Find an entry in the second-level page table.. */
	162	#define pmd_index(addr) (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1))
	163	static inline pmd_t pmd_offset(pud_t pud, unsigned long addr)
	164	{
	165	return (pmd_t )pud_page_vaddr(pud) + pmd_index(addr);
	166	}
	167
	168	#define pmd_bad(pmd) (!(pmd_val(pmd) & 2))
	169
	170	#define copy_pmd(pmdpd,pmdps) \
	171	do { \
	172	pmdpd = pmdps; \
	173	flush_pmd_entry(pmdpd); \
	174	} while (0)
	175
	176	#define pmd_clear(pmdp) \
	177	do { \
	178	*pmdp = __pmd(0); \
	179	clean_pmd_entry(pmdp); \
	180	} while (0)
	181
dde1b651 SC	182	/*
	183	* For 3 levels of paging the PTE_EXT_NG bit will be set for user address ptes
	184	* that are written to a page table but not for ptes created with mk_pte.
	185	*
	186	* In hugetlb_no_page, a new huge pte (new_pte) is generated and passed to
	187	* hugetlb_cow, where it is compared with an entry in a page table.
	188	* This comparison test fails erroneously leading ultimately to a memory leak.
	189	*
	190	* To correct this behaviour, we mask off PTE_EXT_NG for any pte that is
	191	* present before running the comparison.
	192	*/
	193	#define __HAVE_ARCH_PTE_SAME
	194	#define pte_same(pte_a,pte_b) ((pte_present(pte_a) ? pte_val(pte_a) & ~PTE_EXT_NG \
	195	: pte_val(pte_a)) \
	196	== (pte_present(pte_b) ? pte_val(pte_b) & ~PTE_EXT_NG \
	197	: pte_val(pte_b)))
	198
da028779 CM	199	#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,__pte(pte_val(pte)\|(ext)))
da028779 CM	200
1355e2a6 CM	201	#define pte_huge(pte) (pte_val(pte) && !(pte_val(pte) & PTE_TABLE_BIT))
	202	#define pte_mkhuge(pte) (__pte(pte_val(pte) & ~PTE_TABLE_BIT))
	203
8d962507 CM	204	#define pmd_young(pmd) (pmd_val(pmd) & PMD_SECT_AF)
	205
	206	#define __HAVE_ARCH_PMD_WRITE
	207	#define pmd_write(pmd) (!(pmd_val(pmd) & PMD_SECT_RDONLY))
	208
	209	#ifdef CONFIG_TRANSPARENT_HUGEPAGE
	210	#define pmd_trans_huge(pmd) (pmd_val(pmd) && !(pmd_val(pmd) & PMD_TABLE_BIT))
	211	#define pmd_trans_splitting(pmd) (pmd_val(pmd) & PMD_SECT_SPLITTING)
	212	#endif
	213
	214	#define PMD_BIT_FUNC(fn,op) \
	215	static inline pmd_t pmd_##fn(pmd_t pmd) { pmd_val(pmd) op; return pmd; }
	216
	217	PMD_BIT_FUNC(wrprotect, \|= PMD_SECT_RDONLY);
	218	PMD_BIT_FUNC(mkold, &= ~PMD_SECT_AF);
	219	PMD_BIT_FUNC(mksplitting, \|= PMD_SECT_SPLITTING);
	220	PMD_BIT_FUNC(mkwrite, &= ~PMD_SECT_RDONLY);
	221	PMD_BIT_FUNC(mkdirty, \|= PMD_SECT_DIRTY);
	222	PMD_BIT_FUNC(mkyoung, \|= PMD_SECT_AF);
	223
	224	#define pmd_mkhuge(pmd) (__pmd(pmd_val(pmd) & ~PMD_TABLE_BIT))
	225
	226	#define pmd_pfn(pmd) (((pmd_val(pmd) & PMD_MASK) & PHYS_MASK) >> PAGE_SHIFT)
	227	#define pfn_pmd(pfn,prot) (__pmd(((phys_addr_t)(pfn) << PAGE_SHIFT) \| pgprot_val(prot)))
	228	#define mk_pmd(page,prot) pfn_pmd(page_to_pfn(page),prot)
	229
	230	/* represent a notpresent pmd by zero, this is used by pmdp_invalidate */
	231	#define pmd_mknotpresent(pmd) (__pmd(0))
	232
	233	static inline pmd_t pmd_modify(pmd_t pmd, pgprot_t newprot)
	234	{
	235	const pmdval_t mask = PMD_SECT_USER \| PMD_SECT_XN \| PMD_SECT_RDONLY \|
	236	PMD_SECT_VALID \| PMD_SECT_NONE;
	237	pmd_val(pmd) = (pmd_val(pmd) & ~mask) \| (pgprot_val(newprot) & mask);
	238	return pmd;
	239	}
	240
	241	static inline void set_pmd_at(struct mm_struct *mm, unsigned long addr,
	242	pmd_t *pmdp, pmd_t pmd)
	243	{
	244	BUG_ON(addr >= TASK_SIZE);
	245
	246	/* create a faulting entry if PROT_NONE protected */
	247	if (pmd_val(pmd) & PMD_SECT_NONE)
	248	pmd_val(pmd) &= ~PMD_SECT_VALID;
	249
	250	*pmdp = __pmd(pmd_val(pmd) \| PMD_SECT_nG);
	251	flush_pmd_entry(pmdp);
	252	}
	253
	254	static inline int has_transparent_hugepage(void)
	255	{
	256	return 1;
	257	}
	258
da028779 CM	259	#endif /* __ASSEMBLY__ */
da028779 CM	260
dcfdae04	261	#endif /* _ASM_PGTABLE_3LEVEL_H */