[deliverable/linux.git] / arch / arm / include / asm / pgtable.h

/*
 *  arch/arm/include/asm/pgtable.h
 *
 *  Copyright (C) 1995-2002 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */
#ifndef _ASMARM_PGTABLE_H
#define _ASMARM_PGTABLE_H

#include <linux/const.h>
#include <asm-generic/4level-fixup.h>
#include <asm/proc-fns.h>

#ifndef CONFIG_MMU

#include "pgtable-nommu.h"

#else

#include <asm/memory.h>
#include <mach/vmalloc.h>
#include <asm/pgtable-hwdef.h>

/*
 * Just any arbitrary offset to the start of the vmalloc VM area: the
 * current 8MB value just means that there will be a 8MB "hole" after the
 * physical memory until the kernel virtual memory starts.  That means that
 * any out-of-bounds memory accesses will hopefully be caught.
 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
 * area for the same reason. ;)
 *
 * Note that platforms may override VMALLOC_START, but they must provide
 * VMALLOC_END.  VMALLOC_END defines the (exclusive) limit of this space,
 * which may not overlap IO space.
 */
#ifndef VMALLOC_START
#define VMALLOC_OFFSET		(8*1024*1024)
#define VMALLOC_START		(((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
#endif

/*
 * Hardware-wise, we have a two level page table structure, where the first
 * level has 4096 entries, and the second level has 256 entries.  Each entry
 * is one 32-bit word.  Most of the bits in the second level entry are used
 * by hardware, and there aren't any "accessed" and "dirty" bits.
 *
 * Linux on the other hand has a three level page table structure, which can
 * be wrapped to fit a two level page table structure easily - using the PGD
 * and PTE only.  However, Linux also expects one "PTE" table per page, and
 * at least a "dirty" bit.
 *
 * Therefore, we tweak the implementation slightly - we tell Linux that we
 * have 2048 entries in the first level, each of which is 8 bytes (iow, two
 * hardware pointers to the second level.)  The second level contains two
 * hardware PTE tables arranged contiguously, followed by Linux versions
 * which contain the state information Linux needs.  We, therefore, end up
 * with 512 entries in the "PTE" level.
 *
 * This leads to the page tables having the following layout:
 *
 *    pgd             pte
 * |        |
 * +--------+ +0
 * |        |-----> +------------+ +0
 * +- - - - + +4    |  h/w pt 0  |
 * |        |-----> +------------+ +1024
 * +--------+ +8    |  h/w pt 1  |
 * |        |       +------------+ +2048
 * +- - - - +       | Linux pt 0 |
 * |        |       +------------+ +3072
 * +--------+       | Linux pt 1 |
 * |        |       +------------+ +4096
 *
 * See L_PTE_xxx below for definitions of bits in the "Linux pt", and
 * PTE_xxx for definitions of bits appearing in the "h/w pt".
 *
 * PMD_xxx definitions refer to bits in the first level page table.
 *
 * The "dirty" bit is emulated by only granting hardware write permission
 * iff the page is marked "writable" and "dirty" in the Linux PTE.  This
 * means that a write to a clean page will cause a permission fault, and
 * the Linux MM layer will mark the page dirty via handle_pte_fault().
 * For the hardware to notice the permission change, the TLB entry must
 * be flushed, and ptep_set_access_flags() does that for us.
 *
 * The "accessed" or "young" bit is emulated by a similar method; we only
 * allow accesses to the page if the "young" bit is set.  Accesses to the
 * page will cause a fault, and handle_pte_fault() will set the young bit
 * for us as long as the page is marked present in the corresponding Linux
 * PTE entry.  Again, ptep_set_access_flags() will ensure that the TLB is
 * up to date.
 *
 * However, when the "young" bit is cleared, we deny access to the page
 * by clearing the hardware PTE.  Currently Linux does not flush the TLB
 * for us in this case, which means the TLB will retain the transation
 * until either the TLB entry is evicted under pressure, or a context
 * switch which changes the user space mapping occurs.
 */
#define PTRS_PER_PTE		512
#define PTRS_PER_PMD		1
#define PTRS_PER_PGD		2048

/*
 * PMD_SHIFT determines the size of the area a second-level page table can map
 * PGDIR_SHIFT determines what a third-level page table entry can map
 */
#define PMD_SHIFT		21
#define PGDIR_SHIFT		21

#define LIBRARY_TEXT_START	0x0c000000

#ifndef __ASSEMBLY__
extern void __pte_error(const char *file, int line, pte_t);
extern void __pmd_error(const char *file, int line, pmd_t);
extern void __pgd_error(const char *file, int line, pgd_t);

#define pte_ERROR(pte)		__pte_error(__FILE__, __LINE__, pte)
#define pmd_ERROR(pmd)		__pmd_error(__FILE__, __LINE__, pmd)
#define pgd_ERROR(pgd)		__pgd_error(__FILE__, __LINE__, pgd)
#endif /* !__ASSEMBLY__ */

#define PMD_SIZE		(1UL << PMD_SHIFT)
#define PMD_MASK		(~(PMD_SIZE-1))
#define PGDIR_SIZE		(1UL << PGDIR_SHIFT)
#define PGDIR_MASK		(~(PGDIR_SIZE-1))

/*
 * This is the lowest virtual address we can permit any user space
 * mapping to be mapped at.  This is particularly important for
 * non-high vector CPUs.
 */
#define FIRST_USER_ADDRESS	PAGE_SIZE

#define FIRST_USER_PGD_NR	1
#define USER_PTRS_PER_PGD	((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR)

/*
 * section address mask and size definitions.
 */
#define SECTION_SHIFT		20
#define SECTION_SIZE		(1UL << SECTION_SHIFT)
#define SECTION_MASK		(~(SECTION_SIZE-1))

/*
 * ARMv6 supersection address mask and size definitions.
 */
#define SUPERSECTION_SHIFT	24
#define SUPERSECTION_SIZE	(1UL << SUPERSECTION_SHIFT)
#define SUPERSECTION_MASK	(~(SUPERSECTION_SIZE-1))

/*
 * "Linux" PTE definitions.
 *
 * We keep two sets of PTEs - the hardware and the linux version.
 * This allows greater flexibility in the way we map the Linux bits
 * onto the hardware tables, and allows us to have YOUNG and DIRTY
 * bits.
 *
 * The PTE table pointer refers to the hardware entries; the "Linux"
 * entries are stored 1024 bytes below.
 */
#define L_PTE_PRESENT		(_AT(pteval_t, 1) << 0)
#define L_PTE_YOUNG		(_AT(pteval_t, 1) << 1)
#define L_PTE_FILE		(_AT(pteval_t, 1) << 2)	/* only when !PRESENT */
#define L_PTE_DIRTY		(_AT(pteval_t, 1) << 6)
#define L_PTE_WRITE		(_AT(pteval_t, 1) << 7)
#define L_PTE_USER		(_AT(pteval_t, 1) << 8)
#define L_PTE_EXEC		(_AT(pteval_t, 1) << 9)
#define L_PTE_SHARED		(_AT(pteval_t, 1) << 10)	/* shared(v6), coherent(xsc3) */

/*
 * These are the memory types, defined to be compatible with
 * pre-ARMv6 CPUs cacheable and bufferable bits:   XXCB
 */
#define L_PTE_MT_UNCACHED	(_AT(pteval_t, 0x00) << 2)	/* 0000 */
#define L_PTE_MT_BUFFERABLE	(_AT(pteval_t, 0x01) << 2)	/* 0001 */
#define L_PTE_MT_WRITETHROUGH	(_AT(pteval_t, 0x02) << 2)	/* 0010 */
#define L_PTE_MT_WRITEBACK	(_AT(pteval_t, 0x03) << 2)	/* 0011 */
#define L_PTE_MT_MINICACHE	(_AT(pteval_t, 0x06) << 2)	/* 0110 (sa1100, xscale) */
#define L_PTE_MT_WRITEALLOC	(_AT(pteval_t, 0x07) << 2)	/* 0111 */
#define L_PTE_MT_DEV_SHARED	(_AT(pteval_t, 0x04) << 2)	/* 0100 */
#define L_PTE_MT_DEV_NONSHARED	(_AT(pteval_t, 0x0c) << 2)	/* 1100 */
#define L_PTE_MT_DEV_WC		(_AT(pteval_t, 0x09) << 2)	/* 1001 */
#define L_PTE_MT_DEV_CACHED	(_AT(pteval_t, 0x0b) << 2)	/* 1011 */
#define L_PTE_MT_MASK		(_AT(pteval_t, 0x0f) << 2)

#ifndef __ASSEMBLY__

/*
 * The pgprot_* and protection_map entries will be fixed up in runtime
 * to include the cachable and bufferable bits based on memory policy,
 * as well as any architecture dependent bits like global/ASID and SMP
 * shared mapping bits.
 */
#define _L_PTE_DEFAULT	L_PTE_PRESENT | L_PTE_YOUNG

extern pgprot_t		pgprot_user;
extern pgprot_t		pgprot_kernel;

#define _MOD_PROT(p, b)	__pgprot(pgprot_val(p) | (b))

#define PAGE_NONE		pgprot_user
#define PAGE_SHARED		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_WRITE)
#define PAGE_SHARED_EXEC	_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_WRITE | L_PTE_EXEC)
#define PAGE_COPY		_MOD_PROT(pgprot_user, L_PTE_USER)
#define PAGE_COPY_EXEC		_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_EXEC)
#define PAGE_READONLY		_MOD_PROT(pgprot_user, L_PTE_USER)
#define PAGE_READONLY_EXEC	_MOD_PROT(pgprot_user, L_PTE_USER | L_PTE_EXEC)
#define PAGE_KERNEL		pgprot_kernel
#define PAGE_KERNEL_EXEC	_MOD_PROT(pgprot_kernel, L_PTE_EXEC)

#define __PAGE_NONE		__pgprot(_L_PTE_DEFAULT)
#define __PAGE_SHARED		__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_WRITE)
#define __PAGE_SHARED_EXEC	__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_WRITE | L_PTE_EXEC)
#define __PAGE_COPY		__pgprot(_L_PTE_DEFAULT | L_PTE_USER)
#define __PAGE_COPY_EXEC	__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_EXEC)
#define __PAGE_READONLY		__pgprot(_L_PTE_DEFAULT | L_PTE_USER)
#define __PAGE_READONLY_EXEC	__pgprot(_L_PTE_DEFAULT | L_PTE_USER | L_PTE_EXEC)

#define __pgprot_modify(prot,mask,bits)		\
	__pgprot((pgprot_val(prot) & ~(mask)) | (bits))

#define pgprot_noncached(prot) \
	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)

#define pgprot_writecombine(prot) \
	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)

#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
#define pgprot_dmacoherent(prot) \
	__pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_BUFFERABLE)
#define __HAVE_PHYS_MEM_ACCESS_PROT
struct file;
extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
				     unsigned long size, pgprot_t vma_prot);
#else
#define pgprot_dmacoherent(prot) \
	__pgprot_modify(prot, L_PTE_MT_MASK|L_PTE_EXEC, L_PTE_MT_UNCACHED)
#endif

#endif /* __ASSEMBLY__ */

/*
 * The table below defines the page protection levels that we insert into our
 * Linux page table version.  These get translated into the best that the
 * architecture can perform.  Note that on most ARM hardware:
 *  1) We cannot do execute protection
 *  2) If we could do execute protection, then read is implied
 *  3) write implies read permissions
 */
#define __P000  __PAGE_NONE
#define __P001  __PAGE_READONLY
#define __P010  __PAGE_COPY
#define __P011  __PAGE_COPY
#define __P100  __PAGE_READONLY_EXEC
#define __P101  __PAGE_READONLY_EXEC
#define __P110  __PAGE_COPY_EXEC
#define __P111  __PAGE_COPY_EXEC

#define __S000  __PAGE_NONE
#define __S001  __PAGE_READONLY
#define __S010  __PAGE_SHARED
#define __S011  __PAGE_SHARED
#define __S100  __PAGE_READONLY_EXEC
#define __S101  __PAGE_READONLY_EXEC
#define __S110  __PAGE_SHARED_EXEC
#define __S111  __PAGE_SHARED_EXEC

#ifndef __ASSEMBLY__
/*
 * ZERO_PAGE is a global shared page that is always zero: used
 * for zero-mapped memory areas etc..
 */
extern struct page *empty_zero_page;
#define ZERO_PAGE(vaddr)	(empty_zero_page)


extern pgd_t swapper_pg_dir[PTRS_PER_PGD];

/* to find an entry in a page-table-directory */
#define pgd_index(addr)		((addr) >> PGDIR_SHIFT)

#define pgd_offset(mm, addr)	((mm)->pgd + pgd_index(addr))

/* to find an entry in a kernel page-table-directory */
#define pgd_offset_k(addr)	pgd_offset(&init_mm, addr)

/*
 * The "pgd_xxx()" functions here are trivial for a folded two-level
 * setup: the pgd is never bad, and a pmd always exists (as it's folded
 * into the pgd entry)
 */
#define pgd_none(pgd)		(0)
#define pgd_bad(pgd)		(0)
#define pgd_present(pgd)	(1)
#define pgd_clear(pgdp)		do { } while (0)
#define set_pgd(pgd,pgdp)	do { } while (0)


/* Find an entry in the second-level page table.. */
#define pmd_offset(dir, addr)	((pmd_t *)(dir))

#define pmd_none(pmd)		(!pmd_val(pmd))
#define pmd_present(pmd)	(pmd_val(pmd))
#define pmd_bad(pmd)		(pmd_val(pmd) & 2)

#define copy_pmd(pmdpd,pmdps)		\
	do {				\
		pmdpd[0] = pmdps[0];	\
		pmdpd[1] = pmdps[1];	\
		flush_pmd_entry(pmdpd);	\
	} while (0)

#define pmd_clear(pmdp)			\
	do {				\
		pmdp[0] = __pmd(0);	\
		pmdp[1] = __pmd(0);	\
		clean_pmd_entry(pmdp);	\
	} while (0)

static inline pte_t *pmd_page_vaddr(pmd_t pmd)
{
	phys_addr_t ptr;

	ptr = pmd_val(pmd) & ~(PTRS_PER_PTE * sizeof(void *) - 1);
	ptr += PTRS_PER_PTE * sizeof(void *);

	return __va(ptr);
}

#define pmd_page(pmd)		pfn_to_page(__phys_to_pfn(pmd_val(pmd)))

/* we don't need complex calculations here as the pmd is folded into the pgd */
#define pmd_addr_end(addr,end)	(end)


#ifndef CONFIG_HIGHPTE
#define __pte_map(pmd)		pmd_page_vaddr(*(pmd))
#define __pte_unmap(pte)	do { } while (0)
#else
#define __pte_map(pmd)		((pte_t *)kmap_atomic(pmd_page(*(pmd))) + PTRS_PER_PTE)
#define __pte_unmap(pte)	kunmap_atomic((pte - PTRS_PER_PTE))
#endif

#define pte_index(addr)		(((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))

#define pte_offset_kernel(pmd,addr)	(pmd_page_vaddr(*(pmd)) + pte_index(addr))

#define pte_offset_map(pmd,addr)	(__pte_map(pmd) + pte_index(addr))
#define pte_unmap(pte)			__pte_unmap(pte)

#define pte_pfn(pte)		(pte_val(pte) >> PAGE_SHIFT)
#define pfn_pte(pfn,prot)	__pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))

#define pte_page(pte)		pfn_to_page(pte_pfn(pte))
#define mk_pte(page,prot)	pfn_pte(page_to_pfn(page), prot)

#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
#define pte_clear(mm,addr,ptep)	set_pte_ext(ptep, __pte(0), 0)

#if __LINUX_ARM_ARCH__ < 6
static inline void __sync_icache_dcache(pte_t pteval)
{
}
#else
extern void __sync_icache_dcache(pte_t pteval);
#endif

static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
			      pte_t *ptep, pte_t pteval)
{
	if (addr >= TASK_SIZE)
		set_pte_ext(ptep, pteval, 0);
	else {
		__sync_icache_dcache(pteval);
		set_pte_ext(ptep, pteval, PTE_EXT_NG);
	}
}

#define pte_none(pte)		(!pte_val(pte))
#define pte_present(pte)	(pte_val(pte) & L_PTE_PRESENT)
#define pte_write(pte)		(pte_val(pte) & L_PTE_WRITE)
#define pte_dirty(pte)		(pte_val(pte) & L_PTE_DIRTY)
#define pte_young(pte)		(pte_val(pte) & L_PTE_YOUNG)
#define pte_exec(pte)		(pte_val(pte) & L_PTE_EXEC)
#define pte_special(pte)	(0)

#define pte_present_user(pte) \
	((pte_val(pte) & (L_PTE_PRESENT | L_PTE_USER)) == \
	 (L_PTE_PRESENT | L_PTE_USER))

#define PTE_BIT_FUNC(fn,op) \
static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }

PTE_BIT_FUNC(wrprotect, &= ~L_PTE_WRITE);
PTE_BIT_FUNC(mkwrite,   |= L_PTE_WRITE);
PTE_BIT_FUNC(mkclean,   &= ~L_PTE_DIRTY);
PTE_BIT_FUNC(mkdirty,   |= L_PTE_DIRTY);
PTE_BIT_FUNC(mkold,     &= ~L_PTE_YOUNG);
PTE_BIT_FUNC(mkyoung,   |= L_PTE_YOUNG);

static inline pte_t pte_mkspecial(pte_t pte) { return pte; }

static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
	const pteval_t mask = L_PTE_EXEC | L_PTE_WRITE | L_PTE_USER;
	pte_val(pte) = (pte_val(pte) & ~mask) | (pgprot_val(newprot) & mask);
	return pte;
}

/*
 * Encode and decode a swap entry.  Swap entries are stored in the Linux
 * page tables as follows:
 *
 *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 *   <--------------- offset --------------------> <- type --> 0 0 0
 *
 * This gives us up to 63 swap files and 32GB per swap file.  Note that
 * the offset field is always non-zero.
 */
#define __SWP_TYPE_SHIFT	3
#define __SWP_TYPE_BITS		6
#define __SWP_TYPE_MASK		((1 << __SWP_TYPE_BITS) - 1)
#define __SWP_OFFSET_SHIFT	(__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)

#define __swp_type(x)		(((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
#define __swp_offset(x)		((x).val >> __SWP_OFFSET_SHIFT)
#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) | ((offset) << __SWP_OFFSET_SHIFT) })

#define __pte_to_swp_entry(pte)	((swp_entry_t) { pte_val(pte) })
#define __swp_entry_to_pte(swp)	((pte_t) { (swp).val })

/*
 * It is an error for the kernel to have more swap files than we can
 * encode in the PTEs.  This ensures that we know when MAX_SWAPFILES
 * is increased beyond what we presently support.
 */
#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)

/*
 * Encode and decode a file entry.  File entries are stored in the Linux
 * page tables as follows:
 *
 *   3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
 *   1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
 *   <----------------------- offset ------------------------> 1 0 0
 */
#define pte_file(pte)		(pte_val(pte) & L_PTE_FILE)
#define pte_to_pgoff(x)		(pte_val(x) >> 3)
#define pgoff_to_pte(x)		__pte(((x) << 3) | L_PTE_FILE)

#define PTE_FILE_MAX_BITS	29

/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
/* FIXME: this is not correct */
#define kern_addr_valid(addr)	(1)

#include <asm-generic/pgtable.h>

/*
 * We provide our own arch_get_unmapped_area to cope with VIPT caches.
 */
#define HAVE_ARCH_UNMAPPED_AREA

/*
 * remap a physical page `pfn' of size `size' with page protection `prot'
 * into virtual address `from'
 */
#define io_remap_pfn_range(vma,from,pfn,size,prot) \
		remap_pfn_range(vma, from, pfn, size, prot)

#define pgtable_cache_init() do { } while (0)

#endif /* !__ASSEMBLY__ */

#endif /* CONFIG_MMU */

#endif /* _ASMARM_PGTABLE_H */
Commit	Line	Data
1da177e4	1	/*
4baa9922	2	* arch/arm/include/asm/pgtable.h
1da177e4 LT	3	*
	4	* Copyright (C) 1995-2002 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*/
	10	#ifndef _ASMARM_PGTABLE_H
	11	#define _ASMARM_PGTABLE_H
	12
f6e3354d	13	#include <linux/const.h>
1da177e4	14	#include <asm-generic/4level-fixup.h>
002547b4 RK	15	#include <asm/proc-fns.h>
	16
	17	#ifndef CONFIG_MMU
	18
	19	#include "pgtable-nommu.h"
	20
	21	#else
1da177e4 LT	22
1da177e4 LT	23	#include <asm/memory.h>
a09e64fb	24	#include <mach/vmalloc.h>
ad1ae2fe	25	#include <asm/pgtable-hwdef.h>
1da177e4	26
5c3073e6 RK	27	/*
	28	* Just any arbitrary offset to the start of the vmalloc VM area: the
	29	* current 8MB value just means that there will be a 8MB "hole" after the
	30	* physical memory until the kernel virtual memory starts. That means that
	31	* any out-of-bounds memory accesses will hopefully be caught.
	32	* The vmalloc() routines leaves a hole of 4kB between each vmalloced
	33	* area for the same reason. ;)
	34	*
	35	* Note that platforms may override VMALLOC_START, but they must provide
	36	* VMALLOC_END. VMALLOC_END defines the (exclusive) limit of this space,
	37	* which may not overlap IO space.
	38	*/
	39	#ifndef VMALLOC_START
	40	#define VMALLOC_OFFSET (810241024)
	41	#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))
	42	#endif
	43
1da177e4 LT	44	/*
	45	* Hardware-wise, we have a two level page table structure, where the first
	46	* level has 4096 entries, and the second level has 256 entries. Each entry
	47	* is one 32-bit word. Most of the bits in the second level entry are used
	48	* by hardware, and there aren't any "accessed" and "dirty" bits.
	49	*
	50	* Linux on the other hand has a three level page table structure, which can
	51	* be wrapped to fit a two level page table structure easily - using the PGD
	52	* and PTE only. However, Linux also expects one "PTE" table per page, and
	53	* at least a "dirty" bit.
	54	*
	55	* Therefore, we tweak the implementation slightly - we tell Linux that we
	56	* have 2048 entries in the first level, each of which is 8 bytes (iow, two
	57	* hardware pointers to the second level.) The second level contains two
	58	* hardware PTE tables arranged contiguously, followed by Linux versions
	59	* which contain the state information Linux needs. We, therefore, end up
	60	* with 512 entries in the "PTE" level.
	61	*
	62	* This leads to the page tables having the following layout:
	63	*
	64	* pgd pte
	65	* \| \|
	66	* +--------+ +0
	67	* \| \|-----> +------------+ +0
	68	* +- - - - + +4 \| h/w pt 0 \|
	69	* \| \|-----> +------------+ +1024
	70	* +--------+ +8 \| h/w pt 1 \|
	71	* \| \| +------------+ +2048
	72	* +- - - - + \| Linux pt 0 \|
	73	* \| \| +------------+ +3072
	74	* +--------+ \| Linux pt 1 \|
	75	* \| \| +------------+ +4096
	76	*
	77	* See L_PTE_xxx below for definitions of bits in the "Linux pt", and
	78	* PTE_xxx for definitions of bits appearing in the "h/w pt".
	79	*
	80	* PMD_xxx definitions refer to bits in the first level page table.
	81	*
	82	* The "dirty" bit is emulated by only granting hardware write permission
	83	* iff the page is marked "writable" and "dirty" in the Linux PTE. This
	84	* means that a write to a clean page will cause a permission fault, and
	85	* the Linux MM layer will mark the page dirty via handle_pte_fault().
	86	* For the hardware to notice the permission change, the TLB entry must
f0e47c22	87	* be flushed, and ptep_set_access_flags() does that for us.
1da177e4 LT	88	*
	89	* The "accessed" or "young" bit is emulated by a similar method; we only
	90	* allow accesses to the page if the "young" bit is set. Accesses to the
	91	* page will cause a fault, and handle_pte_fault() will set the young bit
	92	* for us as long as the page is marked present in the corresponding Linux
f0e47c22 MS	93	* PTE entry. Again, ptep_set_access_flags() will ensure that the TLB is
f0e47c22 MS	94	* up to date.
1da177e4 LT	95	*
	96	* However, when the "young" bit is cleared, we deny access to the page
	97	* by clearing the hardware PTE. Currently Linux does not flush the TLB
	98	* for us in this case, which means the TLB will retain the transation
	99	* until either the TLB entry is evicted under pressure, or a context
	100	* switch which changes the user space mapping occurs.
	101	*/
	102	#define PTRS_PER_PTE 512
	103	#define PTRS_PER_PMD 1
	104	#define PTRS_PER_PGD 2048
	105
	106	/*
	107	* PMD_SHIFT determines the size of the area a second-level page table can map
	108	* PGDIR_SHIFT determines what a third-level page table entry can map
	109	*/
	110	#define PMD_SHIFT 21
	111	#define PGDIR_SHIFT 21
	112
	113	#define LIBRARY_TEXT_START 0x0c000000
	114
	115	#ifndef __ASSEMBLY__
69529c0e RK	116	extern void __pte_error(const char *file, int line, pte_t);
	117	extern void __pmd_error(const char *file, int line, pmd_t);
	118	extern void __pgd_error(const char *file, int line, pgd_t);
1da177e4	119
69529c0e RK	120	#define pte_ERROR(pte) __pte_error(__FILE__, __LINE__, pte)
	121	#define pmd_ERROR(pmd) __pmd_error(__FILE__, __LINE__, pmd)
	122	#define pgd_ERROR(pgd) __pgd_error(__FILE__, __LINE__, pgd)
1da177e4 LT	123	#endif /* !__ASSEMBLY__ */
	124
	125	#define PMD_SIZE (1UL << PMD_SHIFT)
	126	#define PMD_MASK (~(PMD_SIZE-1))
	127	#define PGDIR_SIZE (1UL << PGDIR_SHIFT)
	128	#define PGDIR_MASK (~(PGDIR_SIZE-1))
	129
6119be0b HD	130	/*
	131	* This is the lowest virtual address we can permit any user space
	132	* mapping to be mapped at. This is particularly important for
	133	* non-high vector CPUs.
	134	*/
	135	#define FIRST_USER_ADDRESS PAGE_SIZE
	136
1da177e4 LT	137	#define FIRST_USER_PGD_NR 1
	138	#define USER_PTRS_PER_PGD ((TASK_SIZE/PGDIR_SIZE) - FIRST_USER_PGD_NR)
	139
4052ebb7 GD	140	/*
	141	* section address mask and size definitions.
	142	*/
	143	#define SECTION_SHIFT 20
	144	#define SECTION_SIZE (1UL << SECTION_SHIFT)
	145	#define SECTION_MASK (~(SECTION_SIZE-1))
	146
1da177e4 LT	147	/*
	148	* ARMv6 supersection address mask and size definitions.
	149	*/
	150	#define SUPERSECTION_SHIFT 24
	151	#define SUPERSECTION_SIZE (1UL << SUPERSECTION_SHIFT)
	152	#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
	153
1da177e4 LT	154	/*
	155	* "Linux" PTE definitions.
	156	*
	157	* We keep two sets of PTEs - the hardware and the linux version.
	158	* This allows greater flexibility in the way we map the Linux bits
	159	* onto the hardware tables, and allows us to have YOUNG and DIRTY
	160	* bits.
	161	*
	162	* The PTE table pointer refers to the hardware entries; the "Linux"
	163	* entries are stored 1024 bytes below.
	164	*/
f6e3354d RK	165	#define L_PTE_PRESENT (_AT(pteval_t, 1) << 0)
	166	#define L_PTE_YOUNG (_AT(pteval_t, 1) << 1)
	167	#define L_PTE_FILE (_AT(pteval_t, 1) << 2) /* only when !PRESENT */
	168	#define L_PTE_DIRTY (_AT(pteval_t, 1) << 6)
	169	#define L_PTE_WRITE (_AT(pteval_t, 1) << 7)
	170	#define L_PTE_USER (_AT(pteval_t, 1) << 8)
	171	#define L_PTE_EXEC (_AT(pteval_t, 1) << 9)
	172	#define L_PTE_SHARED (_AT(pteval_t, 1) << 10) /* shared(v6), coherent(xsc3) */
1da177e4	173
bb30f36f RK	174	/*
	175	* These are the memory types, defined to be compatible with
	176	* pre-ARMv6 CPUs cacheable and bufferable bits: XXCB
bb30f36f	177	*/
f6e3354d RK	178	#define L_PTE_MT_UNCACHED (_AT(pteval_t, 0x00) << 2) /* 0000 */
	179	#define L_PTE_MT_BUFFERABLE (_AT(pteval_t, 0x01) << 2) /* 0001 */
	180	#define L_PTE_MT_WRITETHROUGH (_AT(pteval_t, 0x02) << 2) /* 0010 */
	181	#define L_PTE_MT_WRITEBACK (_AT(pteval_t, 0x03) << 2) /* 0011 */
	182	#define L_PTE_MT_MINICACHE (_AT(pteval_t, 0x06) << 2) /* 0110 (sa1100, xscale) */
	183	#define L_PTE_MT_WRITEALLOC (_AT(pteval_t, 0x07) << 2) /* 0111 */
	184	#define L_PTE_MT_DEV_SHARED (_AT(pteval_t, 0x04) << 2) /* 0100 */
	185	#define L_PTE_MT_DEV_NONSHARED (_AT(pteval_t, 0x0c) << 2) /* 1100 */
	186	#define L_PTE_MT_DEV_WC (_AT(pteval_t, 0x09) << 2) /* 1001 */
	187	#define L_PTE_MT_DEV_CACHED (_AT(pteval_t, 0x0b) << 2) /* 1011 */
	188	#define L_PTE_MT_MASK (_AT(pteval_t, 0x0f) << 2)
bb30f36f	189
1da177e4 LT	190	#ifndef __ASSEMBLY__
1da177e4 LT	191
1da177e4	192	/*
44b18693 I	193	* The pgprot_* and protection_map entries will be fixed up in runtime
	194	* to include the cachable and bufferable bits based on memory policy,
	195	* as well as any architecture dependent bits like global/ASID and SMP
	196	* shared mapping bits.
1da177e4	197	*/
bb30f36f	198	#define _L_PTE_DEFAULT L_PTE_PRESENT \| L_PTE_YOUNG
1da177e4	199
44b18693	200	extern pgprot_t pgprot_user;
1da177e4 LT	201	extern pgprot_t pgprot_kernel;
1da177e4 LT	202
8ec53663	203	#define _MOD_PROT(p, b) __pgprot(pgprot_val(p) \| (b))
1da177e4	204
8ec53663 RK	205	#define PAGE_NONE pgprot_user
	206	#define PAGE_SHARED _MOD_PROT(pgprot_user, L_PTE_USER \| L_PTE_WRITE)
	207	#define PAGE_SHARED_EXEC _MOD_PROT(pgprot_user, L_PTE_USER \| L_PTE_WRITE \| L_PTE_EXEC)
	208	#define PAGE_COPY _MOD_PROT(pgprot_user, L_PTE_USER)
	209	#define PAGE_COPY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER \| L_PTE_EXEC)
	210	#define PAGE_READONLY _MOD_PROT(pgprot_user, L_PTE_USER)
	211	#define PAGE_READONLY_EXEC _MOD_PROT(pgprot_user, L_PTE_USER \| L_PTE_EXEC)
	212	#define PAGE_KERNEL pgprot_kernel
	213	#define PAGE_KERNEL_EXEC _MOD_PROT(pgprot_kernel, L_PTE_EXEC)
	214
	215	#define __PAGE_NONE __pgprot(_L_PTE_DEFAULT)
	216	#define __PAGE_SHARED __pgprot(_L_PTE_DEFAULT \| L_PTE_USER \| L_PTE_WRITE)
	217	#define __PAGE_SHARED_EXEC __pgprot(_L_PTE_DEFAULT \| L_PTE_USER \| L_PTE_WRITE \| L_PTE_EXEC)
	218	#define __PAGE_COPY __pgprot(_L_PTE_DEFAULT \| L_PTE_USER)
	219	#define __PAGE_COPY_EXEC __pgprot(_L_PTE_DEFAULT \| L_PTE_USER \| L_PTE_EXEC)
	220	#define __PAGE_READONLY __pgprot(_L_PTE_DEFAULT \| L_PTE_USER)
	221	#define __PAGE_READONLY_EXEC __pgprot(_L_PTE_DEFAULT \| L_PTE_USER \| L_PTE_EXEC)
44b18693	222
eb9b2b69 RK	223	#define __pgprot_modify(prot,mask,bits) \
	224	__pgprot((pgprot_val(prot) & ~(mask)) \| (bits))
	225
	226	#define pgprot_noncached(prot) \
	227	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_UNCACHED)
	228
	229	#define pgprot_writecombine(prot) \
	230	__pgprot_modify(prot, L_PTE_MT_MASK, L_PTE_MT_BUFFERABLE)
	231
	232	#ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE
	233	#define pgprot_dmacoherent(prot) \
	234	__pgprot_modify(prot, L_PTE_MT_MASK\|L_PTE_EXEC, L_PTE_MT_BUFFERABLE)
	235	#define __HAVE_PHYS_MEM_ACCESS_PROT
	236	struct file;
	237	extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
	238	unsigned long size, pgprot_t vma_prot);
	239	#else
	240	#define pgprot_dmacoherent(prot) \
	241	__pgprot_modify(prot, L_PTE_MT_MASK\|L_PTE_EXEC, L_PTE_MT_UNCACHED)
	242	#endif
	243
1da177e4 LT	244	#endif /* __ASSEMBLY__ */
	245
	246	/*
	247	* The table below defines the page protection levels that we insert into our
	248	* Linux page table version. These get translated into the best that the
	249	* architecture can perform. Note that on most ARM hardware:
	250	* 1) We cannot do execute protection
	251	* 2) If we could do execute protection, then read is implied
	252	* 3) write implies read permissions
	253	*/
44b18693 I	254	#define __P000 __PAGE_NONE
	255	#define __P001 __PAGE_READONLY
	256	#define __P010 __PAGE_COPY
	257	#define __P011 __PAGE_COPY
8ec53663 RK	258	#define __P100 __PAGE_READONLY_EXEC
	259	#define __P101 __PAGE_READONLY_EXEC
	260	#define __P110 __PAGE_COPY_EXEC
	261	#define __P111 __PAGE_COPY_EXEC
44b18693 I	262
	263	#define __S000 __PAGE_NONE
	264	#define __S001 __PAGE_READONLY
	265	#define __S010 __PAGE_SHARED
	266	#define __S011 __PAGE_SHARED
8ec53663 RK	267	#define __S100 __PAGE_READONLY_EXEC
	268	#define __S101 __PAGE_READONLY_EXEC
	269	#define __S110 __PAGE_SHARED_EXEC
	270	#define __S111 __PAGE_SHARED_EXEC
1da177e4 LT	271
	272	#ifndef __ASSEMBLY__
	273	/*
	274	* ZERO_PAGE is a global shared page that is always zero: used
	275	* for zero-mapped memory areas etc..
	276	*/
	277	extern struct page *empty_zero_page;
	278	#define ZERO_PAGE(vaddr) (empty_zero_page)
	279
4eec4b13 RK	280
	281	extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
	282
	283	/* to find an entry in a page-table-directory */
	284	#define pgd_index(addr) ((addr) >> PGDIR_SHIFT)
	285
	286	#define pgd_offset(mm, addr) ((mm)->pgd + pgd_index(addr))
	287
	288	/* to find an entry in a kernel page-table-directory */
	289	#define pgd_offset_k(addr) pgd_offset(&init_mm, addr)
	290
	291	/*
	292	* The "pgd_xxx()" functions here are trivial for a folded two-level
	293	* setup: the pgd is never bad, and a pmd always exists (as it's folded
	294	* into the pgd entry)
	295	*/
	296	#define pgd_none(pgd) (0)
	297	#define pgd_bad(pgd) (0)
	298	#define pgd_present(pgd) (1)
	299	#define pgd_clear(pgdp) do { } while (0)
	300	#define set_pgd(pgd,pgdp) do { } while (0)
	301
	302
b510b049 RK	303	/* Find an entry in the second-level page table.. */
b510b049 RK	304	#define pmd_offset(dir, addr) ((pmd_t *)(dir))
1da177e4	305
b510b049 RK	306	#define pmd_none(pmd) (!pmd_val(pmd))
	307	#define pmd_present(pmd) (pmd_val(pmd))
	308	#define pmd_bad(pmd) (pmd_val(pmd) & 2)
	309
	310	#define copy_pmd(pmdpd,pmdps) \
	311	do { \
	312	pmdpd[0] = pmdps[0]; \
	313	pmdpd[1] = pmdps[1]; \
	314	flush_pmd_entry(pmdpd); \
	315	} while (0)
	316
	317	#define pmd_clear(pmdp) \
	318	do { \
	319	pmdp[0] = __pmd(0); \
	320	pmdp[1] = __pmd(0); \
	321	clean_pmd_entry(pmdp); \
	322	} while (0)
	323
	324	static inline pte_t *pmd_page_vaddr(pmd_t pmd)
	325	{
97092e0c	326	phys_addr_t ptr;
b510b049 RK	327
	328	ptr = pmd_val(pmd) & ~(PTRS_PER_PTE * sizeof(void *) - 1);
	329	ptr += PTRS_PER_PTE * sizeof(void *);
	330
	331	return __va(ptr);
	332	}
	333
	334	#define pmd_page(pmd) pfn_to_page(__phys_to_pfn(pmd_val(pmd)))
	335
	336	/* we don't need complex calculations here as the pmd is folded into the pgd */
	337	#define pmd_addr_end(addr,end) (end)
65cec8e3	338
65cec8e3 RK	339
65cec8e3 RK	340	#ifndef CONFIG_HIGHPTE
b510b049	341	#define __pte_map(pmd) pmd_page_vaddr(*(pmd))
ece0e2b6	342	#define __pte_unmap(pte) do { } while (0)
65cec8e3	343	#else
b510b049	344	#define __pte_map(pmd) ((pte_t )kmap_atomic(pmd_page((pmd))) + PTRS_PER_PTE)
ece0e2b6	345	#define __pte_unmap(pte) kunmap_atomic((pte - PTRS_PER_PTE))
65cec8e3	346	#endif
1da177e4	347
b510b049 RK	348	#define pte_index(addr) (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
	349
	350	#define pte_offset_kernel(pmd,addr) (pmd_page_vaddr(*(pmd)) + pte_index(addr))
	351
	352	#define pte_offset_map(pmd,addr) (__pte_map(pmd) + pte_index(addr))
	353	#define pte_unmap(pte) __pte_unmap(pte)
	354
	355	#define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
	356	#define pfn_pte(pfn,prot) __pte(((pfn) << PAGE_SHIFT) \| pgprot_val(prot))
	357
	358	#define pte_page(pte) pfn_to_page(pte_pfn(pte))
	359	#define mk_pte(page,prot) pfn_pte(page_to_pfn(page), prot)
	360
ad1ae2fe	361	#define set_pte_ext(ptep,pte,ext) cpu_set_pte_ext(ptep,pte,ext)
b510b049	362	#define pte_clear(mm,addr,ptep) set_pte_ext(ptep, __pte(0), 0)
ad1ae2fe	363
6012191a CM	364	#if __LINUX_ARM_ARCH__ < 6
	365	static inline void __sync_icache_dcache(pte_t pteval)
	366	{
	367	}
	368	#else
	369	extern void __sync_icache_dcache(pte_t pteval);
	370	#endif
	371
	372	static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
	373	pte_t *ptep, pte_t pteval)
	374	{
	375	if (addr >= TASK_SIZE)
	376	set_pte_ext(ptep, pteval, 0);
	377	else {
	378	__sync_icache_dcache(pteval);
	379	set_pte_ext(ptep, pteval, PTE_EXT_NG);
	380	}
	381	}
1da177e4	382
b510b049	383	#define pte_none(pte) (!pte_val(pte))
1da177e4	384	#define pte_present(pte) (pte_val(pte) & L_PTE_PRESENT)
1da177e4	385	#define pte_write(pte) (pte_val(pte) & L_PTE_WRITE)
1da177e4 LT	386	#define pte_dirty(pte) (pte_val(pte) & L_PTE_DIRTY)
1da177e4 LT	387	#define pte_young(pte) (pte_val(pte) & L_PTE_YOUNG)
6012191a	388	#define pte_exec(pte) (pte_val(pte) & L_PTE_EXEC)
7e675137	389	#define pte_special(pte) (0)
1da177e4	390
6012191a CM	391	#define pte_present_user(pte) \
	392	((pte_val(pte) & (L_PTE_PRESENT \| L_PTE_USER)) == \
	393	(L_PTE_PRESENT \| L_PTE_USER))
	394
1da177e4 LT	395	#define PTE_BIT_FUNC(fn,op) \
	396	static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
	397
1da177e4 LT	398	PTE_BIT_FUNC(wrprotect, &= ~L_PTE_WRITE);
1da177e4 LT	399	PTE_BIT_FUNC(mkwrite, \|= L_PTE_WRITE);
1da177e4 LT	400	PTE_BIT_FUNC(mkclean, &= ~L_PTE_DIRTY);
	401	PTE_BIT_FUNC(mkdirty, \|= L_PTE_DIRTY);
	402	PTE_BIT_FUNC(mkold, &= ~L_PTE_YOUNG);
	403	PTE_BIT_FUNC(mkyoung, \|= L_PTE_YOUNG);
	404
7e675137 NP	405	static inline pte_t pte_mkspecial(pte_t pte) { return pte; }
7e675137 NP	406
1da177e4 LT	407	static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
1da177e4 LT	408	{
f6e3354d	409	const pteval_t mask = L_PTE_EXEC \| L_PTE_WRITE \| L_PTE_USER;
1da177e4 LT	410	pte_val(pte) = (pte_val(pte) & ~mask) \| (pgprot_val(newprot) & mask);
	411	return pte;
	412	}
	413
fb93a1c7 RK	414	/*
	415	* Encode and decode a swap entry. Swap entries are stored in the Linux
	416	* page tables as follows:
	417	*
	418	* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
	419	* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
6a00cded	420	* <--------------- offset --------------------> <- type --> 0 0 0
1da177e4	421	*
6a00cded	422	* This gives us up to 63 swap files and 32GB per swap file. Note that
fb93a1c7	423	* the offset field is always non-zero.
1da177e4	424	*/
6a00cded RK	425	#define __SWP_TYPE_SHIFT 3
6a00cded RK	426	#define __SWP_TYPE_BITS 6
fb93a1c7 RK	427	#define __SWP_TYPE_MASK ((1 << __SWP_TYPE_BITS) - 1)
	428	#define __SWP_OFFSET_SHIFT (__SWP_TYPE_BITS + __SWP_TYPE_SHIFT)
	429
	430	#define __swp_type(x) (((x).val >> __SWP_TYPE_SHIFT) & __SWP_TYPE_MASK)
	431	#define __swp_offset(x) ((x).val >> __SWP_OFFSET_SHIFT)
	432	#define __swp_entry(type,offset) ((swp_entry_t) { ((type) << __SWP_TYPE_SHIFT) \| ((offset) << __SWP_OFFSET_SHIFT) })
	433
1da177e4 LT	434	#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
	435	#define __swp_entry_to_pte(swp) ((pte_t) { (swp).val })
	436
fb93a1c7 RK	437	/*
	438	* It is an error for the kernel to have more swap files than we can
	439	* encode in the PTEs. This ensures that we know when MAX_SWAPFILES
	440	* is increased beyond what we presently support.
	441	*/
	442	#define MAX_SWAPFILES_CHECK() BUILD_BUG_ON(MAX_SWAPFILES_SHIFT > __SWP_TYPE_BITS)
	443
65b1bfc1 RK	444	/*
	445	* Encode and decode a file entry. File entries are stored in the Linux
	446	* page tables as follows:
	447	*
	448	* 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1
	449	* 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
6a00cded	450	* <----------------------- offset ------------------------> 1 0 0
65b1bfc1 RK	451	*/
65b1bfc1 RK	452	#define pte_file(pte) (pte_val(pte) & L_PTE_FILE)
6a00cded RK	453	#define pte_to_pgoff(x) (pte_val(x) >> 3)
6a00cded RK	454	#define pgoff_to_pte(x) __pte(((x) << 3) \| L_PTE_FILE)
65b1bfc1	455
6a00cded	456	#define PTE_FILE_MAX_BITS 29
65b1bfc1	457
1da177e4 LT	458	/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
	459	/* FIXME: this is not correct */
	460	#define kern_addr_valid(addr) (1)
	461
	462	#include <asm-generic/pgtable.h>
	463
	464	/*
	465	* We provide our own arch_get_unmapped_area to cope with VIPT caches.
	466	*/
	467	#define HAVE_ARCH_UNMAPPED_AREA
	468
	469	/*
33bf5610	470	* remap a physical page `pfn' of size `size' with page protection `prot'
1da177e4 LT	471	* into virtual address `from'
1da177e4 LT	472	*/
1da177e4 LT	473	#define io_remap_pfn_range(vma,from,pfn,size,prot) \
	474	remap_pfn_range(vma, from, pfn, size, prot)
	475
1da177e4 LT	476	#define pgtable_cache_init() do { } while (0)
	477
	478	#endif /* !__ASSEMBLY__ */
	479
002547b4 RK	480	#endif /* CONFIG_MMU */
002547b4 RK	481
1da177e4	482	#endif /* _ASMARM_PGTABLE_H */